drm/amd/display: Fix MPO & pipe split on 3-pipe dcn2x
[WHY] DML is incorrectly initialized with 4 pipes on 3 pipe configs RequiredDPPCLK is halved on unsplit pipe due to an incorrectly handled 3 pipe case, causing underflow with 2 planes & pipe split (MPO, 8K + 2nd display) [HOW] Set correct number of DPP/OTGs for dml init to generate correct DPP topology Double RequiredDPPCLK after clock is halved for pipe split and find_secondary_pipe fails to fix underflow Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2482,9 +2482,10 @@ bool dcn20_fast_validate_bw(
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/* pipe not split previously needs split */
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hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
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ASSERT(hsplit_pipe);
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if (!hsplit_pipe)
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if (!hsplit_pipe) {
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context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
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continue;
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}
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if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
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if (!dcn20_split_stream_for_odm(
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&context->res_ctx, dc->res_pool,
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@ -1609,6 +1609,7 @@ static bool construct(
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struct dc_context *ctx = dc->ctx;
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struct irq_service_init_data init_data;
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uint32_t pipe_fuses = read_pipe_fuses(ctx);
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uint32_t num_pipes;
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ctx->dc_bios->regs = &bios_regs;
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@ -1722,6 +1723,14 @@ static bool construct(
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pool->base.pp_smu = dcn21_pp_smu_create(ctx);
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num_pipes = dcn2_1_ip.max_num_dpp;
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for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
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if (pipe_fuses & 1 << i)
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num_pipes--;
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dcn2_1_ip.max_num_dpp = num_pipes;
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dcn2_1_ip.max_num_otg = num_pipes;
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dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
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init_data.ctx = dc->ctx;
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