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usb: phy: msm: Remove unused pclk_src_name

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There are no references to 'pclk_src_name' in plaform code,
so it is unused.

Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Ivan T. Ivanov 2014-04-28 16:34:12 +03:00 committed by Felipe Balbi
parent 971232cf7c
commit ff0e4a68c9
2 changed files with 1 additions and 30 deletions
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26
drivers/usb/phy/phy-msm-usb.c
View File

@ -464,9 +464,6 @@ static int msm_otg_suspend(struct msm_otg *motg)
if (!IS_ERR(motg->core_clk))
clk_disable_unprepare(motg->core_clk);
if (!IS_ERR(motg->pclk_src))
clk_disable_unprepare(motg->pclk_src);
if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
motg->pdata->otg_control == OTG_PMIC_CONTROL) {
msm_hsusb_ldo_set_mode(motg, 0);
@ -496,9 +493,6 @@ static int msm_otg_resume(struct msm_otg *motg)
if (!atomic_read(&motg->in_lpm))
return 0;
if (!IS_ERR(motg->pclk_src))
clk_prepare_enable(motg->pclk_src);
clk_prepare_enable(motg->pclk);
clk_prepare_enable(motg->clk);
if (!IS_ERR(motg->core_clk))
@ -1396,17 +1390,8 @@ static int msm_otg_probe(struct platform_device *pdev)
* If USB Core is running its protocol engine based on CORE CLK,
* CORE CLK must be running at >55Mhz for correct HSUSB
* operation and USB core cannot tolerate frequency changes on
* CORE CLK. For such USB cores, vote for maximum clk frequency
* on pclk source
* CORE CLK.
*/
motg->pclk_src = ERR_PTR(-ENOENT);
if (motg->pdata->pclk_src_name) {
motg->pclk_src = devm_clk_get(&pdev->dev,
motg->pdata->pclk_src_name);
if (IS_ERR(motg->pclk_src))
return PTR_ERR(motg->pclk_src);
}
motg->pclk = devm_clk_get(&pdev->dev, "usb_hs_pclk");
if (IS_ERR(motg->pclk)) {
dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
@ -1446,10 +1431,6 @@ static int msm_otg_probe(struct platform_device *pdev)
motg->v1p8 = regs[2].consumer;
clk_set_rate(motg->clk, 60000000);
if (!IS_ERR(motg->pclk_src)) {
clk_set_rate(motg->pclk_src, INT_MAX);
clk_prepare_enable(motg->pclk_src);
}
clk_prepare_enable(motg->clk);
clk_prepare_enable(motg->pclk);
@ -1525,8 +1506,6 @@ disable_clks:
clk_disable_unprepare(motg->clk);
if (!IS_ERR(motg->core_clk))
clk_disable_unprepare(motg->core_clk);
if (!IS_ERR(motg->pclk_src))
clk_disable_unprepare(motg->pclk_src);
return ret;
}
@ -1571,9 +1550,6 @@ static int msm_otg_remove(struct platform_device *pdev)
clk_disable_unprepare(motg->clk);
if (!IS_ERR(motg->core_clk))
clk_disable_unprepare(motg->core_clk);
if (!IS_ERR(motg->pclk_src))
clk_disable_unprepare(motg->pclk_src);
msm_hsusb_ldo_init(motg, 0);
pm_runtime_set_suspended(&pdev->dev);

5
include/linux/usb/msm_hsusb.h
View File

@ -106,8 +106,6 @@ enum usb_chg_type {
* @power_budget: VBUS power budget in mA (0 will be treated as 500mA).
* @mode: Supported mode (OTG/peripheral/host).
* @otg_control: OTG switch controlled by user/Id pin
* @pclk_src_name: pclk is derived from ebi1_usb_clk in case of 7x27 and 8k
* dfab_usb_hs_clk in case of 8660 and 8960.
*/
struct msm_otg_platform_data {
int *phy_init_seq;
@ -117,7 +115,6 @@ struct msm_otg_platform_data {
enum otg_control_type otg_control;
enum msm_usb_phy_type phy_type;
void (*setup_gpio)(enum usb_otg_state state);
char *pclk_src_name;
int (*link_clk_reset)(struct clk *link_clk, bool assert);
int (*phy_clk_reset)(struct clk *phy_clk);
};
@ -129,7 +126,6 @@ struct msm_otg_platform_data {
* @irq: IRQ number assigned for HSUSB controller.
* @clk: clock struct of usb_hs_clk.
* @pclk: clock struct of usb_hs_pclk.
* @pclk_src: pclk source for voting.
* @phy_reset_clk: clock struct of usb_phy_clk.
* @core_clk: clock struct of usb_hs_core_clk.
* @regs: ioremapped register base address.
@ -150,7 +146,6 @@ struct msm_otg {
int irq;
struct clk *clk;
struct clk *pclk;
struct clk *pclk_src;
struct clk *phy_reset_clk;
struct clk *core_clk;
void __iomem *regs;