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ASoC: Disable register synchronisation for low frequency WM8996 SYSCLK

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With a low frequency SYSCLK and a fast I2C clock register synchronisation
may occasionally take too long to take effect, causing I/O issues. Disable
synchronisation in order to avoid any issues.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@kernel.org
This commit is contained in:
Mark Brown 2012-01-18 19:17:06 +00:00
parent 495174a8ff
commit fed2200711
2 changed files with 8 additions and 0 deletions
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4
sound/soc/codecs/wm8996.c
View File

@ -2007,6 +2007,7 @@ static int wm8996_set_sysclk(struct snd_soc_dai *dai,
struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
int lfclk = 0;
int ratediv = 0;
int sync = WM8996_REG_SYNC;
int src;
int old;
@ -2051,6 +2052,7 @@ static int wm8996_set_sysclk(struct snd_soc_dai *dai,
case 32000:
case 32768:
lfclk = WM8996_LFCLK_ENA;
sync = 0;
break;
default:
dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
@ -2064,6 +2066,8 @@ static int wm8996_set_sysclk(struct snd_soc_dai *dai,
WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
snd_soc_update_bits(codec, WM8996_CONTROL_INTERFACE_1,
WM8996_REG_SYNC, sync);
snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
WM8996_SYSCLK_ENA, old);

4
sound/soc/codecs/wm8996.h
View File

@ -1567,6 +1567,10 @@ int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
/*
* R257 (0x101) - Control Interface (1)
*/
#define WM8996_REG_SYNC 0x8000 /* REG_SYNC */
#define WM8996_REG_SYNC_MASK 0x8000 /* REG_SYNC */
#define WM8996_REG_SYNC_SHIFT 15 /* REG_SYNC */
#define WM8996_REG_SYNC_WIDTH 1 /* REG_SYNC */
#define WM8996_AUTO_INC 0x0004 /* AUTO_INC */
#define WM8996_AUTO_INC_MASK 0x0004 /* AUTO_INC */
#define WM8996_AUTO_INC_SHIFT 2 /* AUTO_INC */