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drm/nouveau/sec2: utilise engine PRI address from TOP

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Turing has its SEC2 instance in an alternate location, and this avoids
needing to duplicate the code here for it.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2019-02-12 22:28:13 +10:00
parent 1a34693490
commit fdad518362
4 changed files with 20 additions and 10 deletions
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2
drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h
View File

@ -5,6 +5,8 @@
struct nvkm_sec2 { struct nvkm_sec2 {
struct nvkm_engine engine; struct nvkm_engine engine;
u32 addr;
struct nvkm_falcon *falcon; struct nvkm_falcon *falcon;
struct nvkm_msgqueue *queue; struct nvkm_msgqueue *queue;
struct work_struct work; struct work_struct work;

23
drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c
View File

@ -22,6 +22,7 @@
#include "priv.h" #include "priv.h"
#include <core/msgqueue.h> #include <core/msgqueue.h>
#include <subdev/top.h>
#include <engine/falcon.h> #include <engine/falcon.h>
static void * static void *
@ -39,18 +40,18 @@ nvkm_sec2_intr(struct nvkm_engine *engine)
struct nvkm_sec2 *sec2 = nvkm_sec2(engine); struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
struct nvkm_subdev *subdev = &engine->subdev; struct nvkm_subdev *subdev = &engine->subdev;
struct nvkm_device *device = subdev->device; struct nvkm_device *device = subdev->device;
u32 disp = nvkm_rd32(device, 0x8701c); u32 disp = nvkm_rd32(device, sec2->addr + 0x01c);
u32 intr = nvkm_rd32(device, 0x87008) & disp & ~(disp >> 16); u32 intr = nvkm_rd32(device, sec2->addr + 0x008) & disp & ~(disp >> 16);
if (intr & 0x00000040) { if (intr & 0x00000040) {
schedule_work(&sec2->work); schedule_work(&sec2->work);
nvkm_wr32(device, 0x87004, 0x00000040); nvkm_wr32(device, sec2->addr + 0x004, 0x00000040);
intr &= ~0x00000040; intr &= ~0x00000040;
} }
if (intr) { if (intr) {
nvkm_error(subdev, "unhandled intr %08x\n", intr); nvkm_error(subdev, "unhandled intr %08x\n", intr);
nvkm_wr32(device, 0x87004, intr); nvkm_wr32(device, sec2->addr + 0x004, intr);
} }
} }
@ -74,8 +75,15 @@ static int
nvkm_sec2_oneinit(struct nvkm_engine *engine) nvkm_sec2_oneinit(struct nvkm_engine *engine)
{ {
struct nvkm_sec2 *sec2 = nvkm_sec2(engine); struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
return nvkm_falcon_v1_new(&sec2->engine.subdev, "SEC2", 0x87000, struct nvkm_subdev *subdev = &sec2->engine.subdev;
&sec2->falcon);
if (!sec2->addr) {
sec2->addr = nvkm_top_addr(subdev->device, subdev->index);
if (WARN_ON(!sec2->addr))
return -EINVAL;
}
return nvkm_falcon_v1_new(subdev, "SEC2", sec2->addr, &sec2->falcon);
} }
static int static int
@ -95,13 +103,14 @@ nvkm_sec2 = {
}; };
int int
nvkm_sec2_new_(struct nvkm_device *device, int index, nvkm_sec2_new_(struct nvkm_device *device, int index, u32 addr,
struct nvkm_sec2 **psec2) struct nvkm_sec2 **psec2)
{ {
struct nvkm_sec2 *sec2; struct nvkm_sec2 *sec2;
if (!(sec2 = *psec2 = kzalloc(sizeof(*sec2), GFP_KERNEL))) if (!(sec2 = *psec2 = kzalloc(sizeof(*sec2), GFP_KERNEL)))
return -ENOMEM; return -ENOMEM;
sec2->addr = addr;
INIT_WORK(&sec2->work, nvkm_sec2_recv); INIT_WORK(&sec2->work, nvkm_sec2_recv);
return nvkm_engine_ctor(&nvkm_sec2, device, index, true, &sec2->engine); return nvkm_engine_ctor(&nvkm_sec2, device, index, true, &sec2->engine);

2
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
View File

@ -26,5 +26,5 @@ int
gp102_sec2_new(struct nvkm_device *device, int index, gp102_sec2_new(struct nvkm_device *device, int index,
struct nvkm_sec2 **psec2) struct nvkm_sec2 **psec2)
{ {
return nvkm_sec2_new_(device, index, psec2); return nvkm_sec2_new_(device, index, 0, psec2);
} }

3
drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h
View File

@ -5,6 +5,5 @@
#define nvkm_sec2(p) container_of((p), struct nvkm_sec2, engine) #define nvkm_sec2(p) container_of((p), struct nvkm_sec2, engine)
int nvkm_sec2_new_(struct nvkm_device *, int, struct nvkm_sec2 **); int nvkm_sec2_new_(struct nvkm_device *, int, u32 addr, struct nvkm_sec2 **);
#endif #endif