Merge branches 'spear/clock' and 'imx/clock' into next/clock
Updated to resolve dependencies. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
fcd8d84a58
@ -17,14 +17,14 @@ Introduction
|
||||
SPEAr (Platform)
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||||
- SPEAr3XX (3XX SOC series, based on ARM9)
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||||
- SPEAr300 (SOC)
|
||||
- SPEAr300_EVB (Evaluation Board)
|
||||
- SPEAr300 Evaluation Board
|
||||
- SPEAr310 (SOC)
|
||||
- SPEAr310_EVB (Evaluation Board)
|
||||
- SPEAr310 Evaluation Board
|
||||
- SPEAr320 (SOC)
|
||||
- SPEAr320_EVB (Evaluation Board)
|
||||
- SPEAr320 Evaluation Board
|
||||
- SPEAr6XX (6XX SOC series, based on ARM9)
|
||||
- SPEAr600 (SOC)
|
||||
- SPEAr600_EVB (Evaluation Board)
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||||
- SPEAr600 Evaluation Board
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||||
- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
|
||||
- SPEAr1300 (SOC)
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||||
|
||||
@ -51,10 +51,11 @@ Introduction
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||||
Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
|
||||
spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
|
||||
specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
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mach-spear* also contains board specific files for each machine type.
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mach-spear* doesn't contains board specific files as they fully support
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Flattened Device Tree.
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||||
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Document Author
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---------------
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Viresh Kumar, (c) 2010 ST Microelectronics
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Viresh Kumar <viresh.kumar@st.com>, (c) 2010-2012 ST Microelectronics
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18
Documentation/devicetree/bindings/arm/spear-timer.txt
Normal file
18
Documentation/devicetree/bindings/arm/spear-timer.txt
Normal file
@ -0,0 +1,18 @@
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* SPEAr ARM Timer
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||||
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** Timer node required properties:
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||||
- compatible : Should be:
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||||
"st,spear-timer"
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- reg: Address range of the timer registers
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- interrupt-parent: Should be the phandle for the interrupt controller
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that services interrupts for this device
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- interrupt: Should contain the timer interrupt number
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||||
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Example:
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timer@f0000000 {
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compatible = "st,spear-timer";
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reg = <0xf0000000 0x400>;
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interrupts = <2>;
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};
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@ -6,3 +6,21 @@ Boards with the ST SPEAr600 SoC shall have the following properties:
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Required root node property:
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compatible = "st,spear600";
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Boards with the ST SPEAr300 SoC shall have the following properties:
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Required root node property:
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compatible = "st,spear300";
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Boards with the ST SPEAr310 SoC shall have the following properties:
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Required root node property:
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compatible = "st,spear310";
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Boards with the ST SPEAr320 SoC shall have the following properties:
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Required root node property:
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compatible = "st,spear320";
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@ -0,0 +1,95 @@
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* Freescale IOMUX Controller (IOMUXC) for i.MX
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The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
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to share one PAD to several functional blocks. The sharing is done by
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multiplexing the PAD input/output signals. For each PAD there are up to
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8 muxing options (called ALT modes). Since different modules require
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different PAD settings (like pull up, keeper, etc) the IOMUXC controls
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also the PAD settings parameters.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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Freescale IMX pin configuration node is a node of a group of pins which can be
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used for a specific device or function. This node represents both mux and config
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of the pins in that group. The 'mux' selects the function mode(also named mux
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mode) this pin can work on and the 'config' configures various pad settings
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such as pull-up, open drain, drive strength, etc.
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Required properties for iomux controller:
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- compatible: "fsl,<soc>-iomuxc"
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Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
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Required properties for pin configuration node:
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- fsl,pins: two integers array, represents a group of pins mux and config
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setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
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pin working on a specific function, CONFIG is the pad setting value like
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||||
pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid
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||||
pins and functions of each SoC.
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Bits used for CONFIG:
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NO_PAD_CTL(1 << 31): indicate this pin does not need config.
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SION(1 << 30): Software Input On Field.
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Force the selected mux mode input path no matter of MUX_MODE functionality.
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By default the input path is determined by functionality of the selected
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mux mode (regular).
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Other bits are used for PAD setting.
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Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
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of bits definitions.
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NOTE:
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Some requirements for using fsl,imx-pinctrl binding:
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1. We have pin function node defined under iomux controller node to represent
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what pinmux functions this SoC supports.
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2. The pin configuration node intends to work on a specific function should
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to be defined under that specific function node.
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The function node's name should represent well about what function
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this group of pins in this pin configuration node are working on.
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3. The driver can use the function node's name and pin configuration node's
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name describe the pin function and group hierarchy.
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For example, Linux IMX pinctrl driver takes the function node's name
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as the function name and pin configuration node's name as group name to
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create the map table.
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4. Each pin configuration node should have a phandle, devices can set pins
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configurations by referring to the phandle of that pin configuration node.
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Examples:
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usdhc@0219c000 { /* uSDHC4 */
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fsl,card-wired;
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vmmc-supply = <®_3p3v>;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc4_1>;
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};
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iomuxc@020e0000 {
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compatible = "fsl,imx6q-iomuxc";
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reg = <0x020e0000 0x4000>;
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/* shared pinctrl settings */
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usdhc4 {
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pinctrl_usdhc4_1: usdhc4grp-1 {
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fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
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1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
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1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
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1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
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1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
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1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
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1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
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1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
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1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
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1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
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};
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};
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....
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};
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Refer to the IOMUXC controller chapter in imx6q datasheet,
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0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
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80Ohm driver strength and Fast Slew Rate.
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User should refer to each SoC spec to set the correct value.
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TODO: when dtc macro support is available, we can change above raw data
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to dt macro which can get better readability in dts file.
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1628
Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
Normal file
1628
Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
Normal file
File diff suppressed because it is too large
Load Diff
918
Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
Normal file
918
Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
Normal file
@ -0,0 +1,918 @@
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* Freescale MXS Pin Controller
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The pins controlled by mxs pin controller are organized in banks, each bank
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has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
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function is GPIO. The configuration on the pins includes drive strength,
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voltage and pull-up.
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Required properties:
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- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
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- reg: Should contain the register physical address and length for the
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pin controller.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices.
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The node of mxs pin controller acts as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for
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a group of pins, and only affects those parameters that are explicitly listed.
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In other words, a subnode that describes a drive strength parameter implies no
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information about pull-up. For this reason, even seemingly boolean values are
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actually tristates in this binding: unspecified, off, or on. Unspecified is
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represented as an absent property, and off/on are represented as integer
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values 0 and 1.
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Those subnodes under mxs pin controller node will fall into two categories.
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One is to set up a group of pins for a function, both mux selection and pin
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configurations, and it's called group node in the binding document. The other
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one is to adjust the pin configuration for some particular pins that need a
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different configuration than what is defined in group node. The binding
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document calls this type of node config node.
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On mxs, there is no hardware pin group. The pin group in this binding only
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means a group of pins put together for particular peripheral to work in
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particular function, like SSP0 functioning as mmc0-8bit. That said, the
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group node should include all the pins needed for one function rather than
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having these pins defined in several group nodes. It also means each of
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"pinctrl-*" phandle in client device node should only have one group node
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pointed in there, while the phandle can have multiple config node referenced
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there to adjust configurations for some pins in the group.
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Required subnode-properties:
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- fsl,pinmux-ids: An integer array. Each integer in the array specify a pin
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with given mux function, with bank, pin and mux packed as below.
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[15..12] : bank number
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[11..4] : pin number
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[3..0] : mux selection
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This integer with mux selection packed is used as an entity by both group
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and config nodes to identify a pin. The mux selection in the integer takes
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effects only on group node, and will get ignored by driver with config node,
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since config node is only meant to set up pin configurations.
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Valid values for these integers are listed below.
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- reg: Should be the index of the group nodes for same function. This property
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is required only for group nodes, and should not be present in any config
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nodes.
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Optional subnode-properties:
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- fsl,drive-strength: Integer.
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0: 4 mA
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1: 8 mA
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2: 12 mA
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3: 16 mA
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- fsl,voltage: Integer.
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0: 1.8 V
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1: 3.3 V
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- fsl,pull-up: Integer.
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0: Disable the internal pull-up
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1: Enable the internal pull-up
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Examples:
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pinctrl@80018000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx28-pinctrl";
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reg = <0x80018000 2000>;
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mmc0_8bit_pins_a: mmc0-8bit@0 {
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reg = <0>;
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fsl,pinmux-ids = <
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0x2000 0x2010 0x2020 0x2030
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0x2040 0x2050 0x2060 0x2070
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0x2080 0x2090 0x20a0>;
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fsl,drive-strength = <1>;
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||||
fsl,voltage = <1>;
|
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fsl,pull-up = <1>;
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||||
};
|
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|
||||
mmc_cd_cfg: mmc-cd-cfg {
|
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fsl,pinmux-ids = <0x2090>;
|
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fsl,pull-up = <0>;
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||||
};
|
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|
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mmc_sck_cfg: mmc-sck-cfg {
|
||||
fsl,pinmux-ids = <0x20a0>;
|
||||
fsl,drive-strength = <2>;
|
||||
fsl,pull-up = <0>;
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};
|
||||
};
|
||||
|
||||
In this example, group node mmc0-8bit defines a group of pins for mxs SSP0
|
||||
to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations
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applied on all these pins. And config nodes mmc-cd-cfg and mmc-sck-cfg are
|
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adjusting the configuration for pins card-detection and clock from what group
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||||
node mmc0-8bit defines. Only the configuration properties to be adjusted need
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||||
to be listed in the config nodes.
|
||||
|
||||
Valid values for i.MX28 pinmux-id:
|
||||
|
||||
pinmux id
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||||
------ --
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MX28_PAD_GPMI_D00__GPMI_D0 0x0000
|
||||
MX28_PAD_GPMI_D01__GPMI_D1 0x0010
|
||||
MX28_PAD_GPMI_D02__GPMI_D2 0x0020
|
||||
MX28_PAD_GPMI_D03__GPMI_D3 0x0030
|
||||
MX28_PAD_GPMI_D04__GPMI_D4 0x0040
|
||||
MX28_PAD_GPMI_D05__GPMI_D5 0x0050
|
||||
MX28_PAD_GPMI_D06__GPMI_D6 0x0060
|
||||
MX28_PAD_GPMI_D07__GPMI_D7 0x0070
|
||||
MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
|
||||
MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
|
||||
MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
|
||||
MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130
|
||||
MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140
|
||||
MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150
|
||||
MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160
|
||||
MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170
|
||||
MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180
|
||||
MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190
|
||||
MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0
|
||||
MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0
|
||||
MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0
|
||||
MX28_PAD_LCD_D00__LCD_D0 0x1000
|
||||
MX28_PAD_LCD_D01__LCD_D1 0x1010
|
||||
MX28_PAD_LCD_D02__LCD_D2 0x1020
|
||||
MX28_PAD_LCD_D03__LCD_D3 0x1030
|
||||
MX28_PAD_LCD_D04__LCD_D4 0x1040
|
||||
MX28_PAD_LCD_D05__LCD_D5 0x1050
|
||||
MX28_PAD_LCD_D06__LCD_D6 0x1060
|
||||
MX28_PAD_LCD_D07__LCD_D7 0x1070
|
||||
MX28_PAD_LCD_D08__LCD_D8 0x1080
|
||||
MX28_PAD_LCD_D09__LCD_D9 0x1090
|
||||
MX28_PAD_LCD_D10__LCD_D10 0x10a0
|
||||
MX28_PAD_LCD_D11__LCD_D11 0x10b0
|
||||
MX28_PAD_LCD_D12__LCD_D12 0x10c0
|
||||
MX28_PAD_LCD_D13__LCD_D13 0x10d0
|
||||
MX28_PAD_LCD_D14__LCD_D14 0x10e0
|
||||
MX28_PAD_LCD_D15__LCD_D15 0x10f0
|
||||
MX28_PAD_LCD_D16__LCD_D16 0x1100
|
||||
MX28_PAD_LCD_D17__LCD_D17 0x1110
|
||||
MX28_PAD_LCD_D18__LCD_D18 0x1120
|
||||
MX28_PAD_LCD_D19__LCD_D19 0x1130
|
||||
MX28_PAD_LCD_D20__LCD_D20 0x1140
|
||||
MX28_PAD_LCD_D21__LCD_D21 0x1150
|
||||
MX28_PAD_LCD_D22__LCD_D22 0x1160
|
||||
MX28_PAD_LCD_D23__LCD_D23 0x1170
|
||||
MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180
|
||||
MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190
|
||||
MX28_PAD_LCD_RS__LCD_RS 0x11a0
|
||||
MX28_PAD_LCD_CS__LCD_CS 0x11b0
|
||||
MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0
|
||||
MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0
|
||||
MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0
|
||||
MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0
|
||||
MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000
|
||||
MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010
|
||||
MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020
|
||||
MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030
|
||||
MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040
|
||||
MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050
|
||||
MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060
|
||||
MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070
|
||||
MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080
|
||||
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090
|
||||
MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0
|
||||
MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0
|
||||
MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0
|
||||
MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0
|
||||
MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0
|
||||
MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100
|
||||
MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110
|
||||
MX28_PAD_SSP2_MISO__SSP2_D0 0x2120
|
||||
MX28_PAD_SSP2_SS0__SSP2_D3 0x2130
|
||||
MX28_PAD_SSP2_SS1__SSP2_D4 0x2140
|
||||
MX28_PAD_SSP2_SS2__SSP2_D5 0x2150
|
||||
MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180
|
||||
MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190
|
||||
MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0
|
||||
MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0
|
||||
MX28_PAD_AUART0_RX__AUART0_RX 0x3000
|
||||
MX28_PAD_AUART0_TX__AUART0_TX 0x3010
|
||||
MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020
|
||||
MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030
|
||||
MX28_PAD_AUART1_RX__AUART1_RX 0x3040
|
||||
MX28_PAD_AUART1_TX__AUART1_TX 0x3050
|
||||
MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060
|
||||
MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070
|
||||
MX28_PAD_AUART2_RX__AUART2_RX 0x3080
|
||||
MX28_PAD_AUART2_TX__AUART2_TX 0x3090
|
||||
MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0
|
||||
MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0
|
||||
MX28_PAD_AUART3_RX__AUART3_RX 0x30c0
|
||||
MX28_PAD_AUART3_TX__AUART3_TX 0x30d0
|
||||
MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0
|
||||
MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0
|
||||
MX28_PAD_PWM0__PWM_0 0x3100
|
||||
MX28_PAD_PWM1__PWM_1 0x3110
|
||||
MX28_PAD_PWM2__PWM_2 0x3120
|
||||
MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140
|
||||
MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150
|
||||
MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160
|
||||
MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170
|
||||
MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180
|
||||
MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190
|
||||
MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0
|
||||
MX28_PAD_SPDIF__SPDIF_TX 0x31b0
|
||||
MX28_PAD_PWM3__PWM_3 0x31c0
|
||||
MX28_PAD_PWM4__PWM_4 0x31d0
|
||||
MX28_PAD_LCD_RESET__LCD_RESET 0x31e0
|
||||
MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000
|
||||
MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010
|
||||
MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020
|
||||
MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030
|
||||
MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040
|
||||
MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050
|
||||
MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060
|
||||
MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070
|
||||
MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080
|
||||
MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090
|
||||
MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0
|
||||
MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0
|
||||
MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0
|
||||
MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0
|
||||
MX28_PAD_ENET0_COL__ENET0_COL 0x40e0
|
||||
MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0
|
||||
MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100
|
||||
MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140
|
||||
MX28_PAD_EMI_D00__EMI_DATA0 0x5000
|
||||
MX28_PAD_EMI_D01__EMI_DATA1 0x5010
|
||||
MX28_PAD_EMI_D02__EMI_DATA2 0x5020
|
||||
MX28_PAD_EMI_D03__EMI_DATA3 0x5030
|
||||
MX28_PAD_EMI_D04__EMI_DATA4 0x5040
|
||||
MX28_PAD_EMI_D05__EMI_DATA5 0x5050
|
||||
MX28_PAD_EMI_D06__EMI_DATA6 0x5060
|
||||
MX28_PAD_EMI_D07__EMI_DATA7 0x5070
|
||||
MX28_PAD_EMI_D08__EMI_DATA8 0x5080
|
||||
MX28_PAD_EMI_D09__EMI_DATA9 0x5090
|
||||
MX28_PAD_EMI_D10__EMI_DATA10 0x50a0
|
||||
MX28_PAD_EMI_D11__EMI_DATA11 0x50b0
|
||||
MX28_PAD_EMI_D12__EMI_DATA12 0x50c0
|
||||
MX28_PAD_EMI_D13__EMI_DATA13 0x50d0
|
||||
MX28_PAD_EMI_D14__EMI_DATA14 0x50e0
|
||||
MX28_PAD_EMI_D15__EMI_DATA15 0x50f0
|
||||
MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100
|
||||
MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110
|
||||
MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120
|
||||
MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130
|
||||
MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140
|
||||
MX28_PAD_EMI_CLK__EMI_CLK 0x5150
|
||||
MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160
|
||||
MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170
|
||||
MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0
|
||||
MX28_PAD_EMI_A00__EMI_ADDR0 0x6000
|
||||
MX28_PAD_EMI_A01__EMI_ADDR1 0x6010
|
||||
MX28_PAD_EMI_A02__EMI_ADDR2 0x6020
|
||||
MX28_PAD_EMI_A03__EMI_ADDR3 0x6030
|
||||
MX28_PAD_EMI_A04__EMI_ADDR4 0x6040
|
||||
MX28_PAD_EMI_A05__EMI_ADDR5 0x6050
|
||||
MX28_PAD_EMI_A06__EMI_ADDR6 0x6060
|
||||
MX28_PAD_EMI_A07__EMI_ADDR7 0x6070
|
||||
MX28_PAD_EMI_A08__EMI_ADDR8 0x6080
|
||||
MX28_PAD_EMI_A09__EMI_ADDR9 0x6090
|
||||
MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0
|
||||
MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0
|
||||
MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0
|
||||
MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0
|
||||
MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0
|
||||
MX28_PAD_EMI_BA0__EMI_BA0 0x6100
|
||||
MX28_PAD_EMI_BA1__EMI_BA1 0x6110
|
||||
MX28_PAD_EMI_BA2__EMI_BA2 0x6120
|
||||
MX28_PAD_EMI_CASN__EMI_CASN 0x6130
|
||||
MX28_PAD_EMI_RASN__EMI_RASN 0x6140
|
||||
MX28_PAD_EMI_WEN__EMI_WEN 0x6150
|
||||
MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160
|
||||
MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170
|
||||
MX28_PAD_EMI_CKE__EMI_CKE 0x6180
|
||||
MX28_PAD_GPMI_D00__SSP1_D0 0x0001
|
||||
MX28_PAD_GPMI_D01__SSP1_D1 0x0011
|
||||
MX28_PAD_GPMI_D02__SSP1_D2 0x0021
|
||||
MX28_PAD_GPMI_D03__SSP1_D3 0x0031
|
||||
MX28_PAD_GPMI_D04__SSP1_D4 0x0041
|
||||
MX28_PAD_GPMI_D05__SSP1_D5 0x0051
|
||||
MX28_PAD_GPMI_D06__SSP1_D6 0x0061
|
||||
MX28_PAD_GPMI_D07__SSP1_D7 0x0071
|
||||
MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101
|
||||
MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111
|
||||
MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121
|
||||
MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131
|
||||
MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141
|
||||
MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151
|
||||
MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161
|
||||
MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171
|
||||
MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181
|
||||
MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191
|
||||
MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1
|
||||
MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1
|
||||
MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1
|
||||
MX28_PAD_LCD_D03__ETM_DA8 0x1031
|
||||
MX28_PAD_LCD_D04__ETM_DA9 0x1041
|
||||
MX28_PAD_LCD_D08__ETM_DA3 0x1081
|
||||
MX28_PAD_LCD_D09__ETM_DA4 0x1091
|
||||
MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141
|
||||
MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151
|
||||
MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161
|
||||
MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171
|
||||
MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181
|
||||
MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191
|
||||
MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1
|
||||
MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1
|
||||
MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1
|
||||
MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1
|
||||
MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1
|
||||
MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041
|
||||
MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051
|
||||
MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061
|
||||
MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071
|
||||
MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1
|
||||
MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1
|
||||
MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1
|
||||
MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1
|
||||
MX28_PAD_SSP2_SCK__AUART2_RX 0x2101
|
||||
MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111
|
||||
MX28_PAD_SSP2_MISO__AUART3_RX 0x2121
|
||||
MX28_PAD_SSP2_SS0__AUART3_TX 0x2131
|
||||
MX28_PAD_SSP2_SS1__SSP2_D1 0x2141
|
||||
MX28_PAD_SSP2_SS2__SSP2_D2 0x2151
|
||||
MX28_PAD_SSP3_SCK__AUART4_TX 0x2181
|
||||
MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191
|
||||
MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1
|
||||
MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1
|
||||
MX28_PAD_AUART0_RX__I2C0_SCL 0x3001
|
||||
MX28_PAD_AUART0_TX__I2C0_SDA 0x3011
|
||||
MX28_PAD_AUART0_CTS__AUART4_RX 0x3021
|
||||
MX28_PAD_AUART0_RTS__AUART4_TX 0x3031
|
||||
MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041
|
||||
MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051
|
||||
MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061
|
||||
MX28_PAD_AUART1_RTS__USB0_ID 0x3071
|
||||
MX28_PAD_AUART2_RX__SSP3_D1 0x3081
|
||||
MX28_PAD_AUART2_TX__SSP3_D2 0x3091
|
||||
MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1
|
||||
MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1
|
||||
MX28_PAD_AUART3_RX__CAN0_TX 0x30c1
|
||||
MX28_PAD_AUART3_TX__CAN0_RX 0x30d1
|
||||
MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1
|
||||
MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1
|
||||
MX28_PAD_PWM0__I2C1_SCL 0x3101
|
||||
MX28_PAD_PWM1__I2C1_SDA 0x3111
|
||||
MX28_PAD_PWM2__USB0_ID 0x3121
|
||||
MX28_PAD_SAIF0_MCLK__PWM_3 0x3141
|
||||
MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151
|
||||
MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161
|
||||
MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171
|
||||
MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181
|
||||
MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191
|
||||
MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1
|
||||
MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1
|
||||
MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001
|
||||
MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011
|
||||
MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021
|
||||
MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031
|
||||
MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041
|
||||
MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051
|
||||
MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061
|
||||
MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071
|
||||
MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081
|
||||
MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091
|
||||
MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1
|
||||
MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1
|
||||
MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1
|
||||
MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1
|
||||
MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1
|
||||
MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1
|
||||
MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122
|
||||
MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132
|
||||
MX28_PAD_GPMI_RDY0__USB0_ID 0x0142
|
||||
MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162
|
||||
MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172
|
||||
MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2
|
||||
MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2
|
||||
MX28_PAD_LCD_D00__ETM_DA0 0x1002
|
||||
MX28_PAD_LCD_D01__ETM_DA1 0x1012
|
||||
MX28_PAD_LCD_D02__ETM_DA2 0x1022
|
||||
MX28_PAD_LCD_D03__ETM_DA3 0x1032
|
||||
MX28_PAD_LCD_D04__ETM_DA4 0x1042
|
||||
MX28_PAD_LCD_D05__ETM_DA5 0x1052
|
||||
MX28_PAD_LCD_D06__ETM_DA6 0x1062
|
||||
MX28_PAD_LCD_D07__ETM_DA7 0x1072
|
||||
MX28_PAD_LCD_D08__ETM_DA8 0x1082
|
||||
MX28_PAD_LCD_D09__ETM_DA9 0x1092
|
||||
MX28_PAD_LCD_D10__ETM_DA10 0x10a2
|
||||
MX28_PAD_LCD_D11__ETM_DA11 0x10b2
|
||||
MX28_PAD_LCD_D12__ETM_DA12 0x10c2
|
||||
MX28_PAD_LCD_D13__ETM_DA13 0x10d2
|
||||
MX28_PAD_LCD_D14__ETM_DA14 0x10e2
|
||||
MX28_PAD_LCD_D15__ETM_DA15 0x10f2
|
||||
MX28_PAD_LCD_D16__ETM_DA7 0x1102
|
||||
MX28_PAD_LCD_D17__ETM_DA6 0x1112
|
||||
MX28_PAD_LCD_D18__ETM_DA5 0x1122
|
||||
MX28_PAD_LCD_D19__ETM_DA4 0x1132
|
||||
MX28_PAD_LCD_D20__ETM_DA3 0x1142
|
||||
MX28_PAD_LCD_D21__ETM_DA2 0x1152
|
||||
MX28_PAD_LCD_D22__ETM_DA1 0x1162
|
||||
MX28_PAD_LCD_D23__ETM_DA0 0x1172
|
||||
MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182
|
||||
MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192
|
||||
MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2
|
||||
MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2
|
||||
MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2
|
||||
MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2
|
||||
MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2
|
||||
MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2
|
||||
MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102
|
||||
MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112
|
||||
MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122
|
||||
MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132
|
||||
MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142
|
||||
MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152
|
||||
MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182
|
||||
MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192
|
||||
MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2
|
||||
MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2
|
||||
MX28_PAD_AUART0_RX__DUART_CTS 0x3002
|
||||
MX28_PAD_AUART0_TX__DUART_RTS 0x3012
|
||||
MX28_PAD_AUART0_CTS__DUART_RX 0x3022
|
||||
MX28_PAD_AUART0_RTS__DUART_TX 0x3032
|
||||
MX28_PAD_AUART1_RX__PWM_0 0x3042
|
||||
MX28_PAD_AUART1_TX__PWM_1 0x3052
|
||||
MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062
|
||||
MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072
|
||||
MX28_PAD_AUART2_RX__SSP3_D4 0x3082
|
||||
MX28_PAD_AUART2_TX__SSP3_D5 0x3092
|
||||
MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2
|
||||
MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2
|
||||
MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2
|
||||
MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2
|
||||
MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2
|
||||
MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2
|
||||
MX28_PAD_PWM0__DUART_RX 0x3102
|
||||
MX28_PAD_PWM1__DUART_TX 0x3112
|
||||
MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122
|
||||
MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142
|
||||
MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152
|
||||
MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162
|
||||
MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172
|
||||
MX28_PAD_I2C0_SCL__DUART_RX 0x3182
|
||||
MX28_PAD_I2C0_SDA__DUART_TX 0x3192
|
||||
MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2
|
||||
MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2
|
||||
MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002
|
||||
MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012
|
||||
MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022
|
||||
MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032
|
||||
MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052
|
||||
MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092
|
||||
MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2
|
||||
MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2
|
||||
MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2
|
||||
MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2
|
||||
MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2
|
||||
MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2
|
||||
MX28_PAD_GPMI_D00__GPIO_0_0 0x0003
|
||||
MX28_PAD_GPMI_D01__GPIO_0_1 0x0013
|
||||
MX28_PAD_GPMI_D02__GPIO_0_2 0x0023
|
||||
MX28_PAD_GPMI_D03__GPIO_0_3 0x0033
|
||||
MX28_PAD_GPMI_D04__GPIO_0_4 0x0043
|
||||
MX28_PAD_GPMI_D05__GPIO_0_5 0x0053
|
||||
MX28_PAD_GPMI_D06__GPIO_0_6 0x0063
|
||||
MX28_PAD_GPMI_D07__GPIO_0_7 0x0073
|
||||
MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103
|
||||
MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113
|
||||
MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123
|
||||
MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133
|
||||
MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143
|
||||
MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153
|
||||
MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163
|
||||
MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173
|
||||
MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183
|
||||
MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193
|
||||
MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3
|
||||
MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3
|
||||
MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3
|
||||
MX28_PAD_LCD_D00__GPIO_1_0 0x1003
|
||||
MX28_PAD_LCD_D01__GPIO_1_1 0x1013
|
||||
MX28_PAD_LCD_D02__GPIO_1_2 0x1023
|
||||
MX28_PAD_LCD_D03__GPIO_1_3 0x1033
|
||||
MX28_PAD_LCD_D04__GPIO_1_4 0x1043
|
||||
MX28_PAD_LCD_D05__GPIO_1_5 0x1053
|
||||
MX28_PAD_LCD_D06__GPIO_1_6 0x1063
|
||||
MX28_PAD_LCD_D07__GPIO_1_7 0x1073
|
||||
MX28_PAD_LCD_D08__GPIO_1_8 0x1083
|
||||
MX28_PAD_LCD_D09__GPIO_1_9 0x1093
|
||||
MX28_PAD_LCD_D10__GPIO_1_10 0x10a3
|
||||
MX28_PAD_LCD_D11__GPIO_1_11 0x10b3
|
||||
MX28_PAD_LCD_D12__GPIO_1_12 0x10c3
|
||||
MX28_PAD_LCD_D13__GPIO_1_13 0x10d3
|
||||
MX28_PAD_LCD_D14__GPIO_1_14 0x10e3
|
||||
MX28_PAD_LCD_D15__GPIO_1_15 0x10f3
|
||||
MX28_PAD_LCD_D16__GPIO_1_16 0x1103
|
||||
MX28_PAD_LCD_D17__GPIO_1_17 0x1113
|
||||
MX28_PAD_LCD_D18__GPIO_1_18 0x1123
|
||||
MX28_PAD_LCD_D19__GPIO_1_19 0x1133
|
||||
MX28_PAD_LCD_D20__GPIO_1_20 0x1143
|
||||
MX28_PAD_LCD_D21__GPIO_1_21 0x1153
|
||||
MX28_PAD_LCD_D22__GPIO_1_22 0x1163
|
||||
MX28_PAD_LCD_D23__GPIO_1_23 0x1173
|
||||
MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183
|
||||
MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193
|
||||
MX28_PAD_LCD_RS__GPIO_1_26 0x11a3
|
||||
MX28_PAD_LCD_CS__GPIO_1_27 0x11b3
|
||||
MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3
|
||||
MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3
|
||||
MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3
|
||||
MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3
|
||||
MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003
|
||||
MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013
|
||||
MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023
|
||||
MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033
|
||||
MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043
|
||||
MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053
|
||||
MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063
|
||||
MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073
|
||||
MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083
|
||||
MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093
|
||||
MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3
|
||||
MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3
|
||||
MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3
|
||||
MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3
|
||||
MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3
|
||||
MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103
|
||||
MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113
|
||||
MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123
|
||||
MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133
|
||||
MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143
|
||||
MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153
|
||||
MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183
|
||||
MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193
|
||||
MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3
|
||||
MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3
|
||||
MX28_PAD_AUART0_RX__GPIO_3_0 0x3003
|
||||
MX28_PAD_AUART0_TX__GPIO_3_1 0x3013
|
||||
MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023
|
||||
MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033
|
||||
MX28_PAD_AUART1_RX__GPIO_3_4 0x3043
|
||||
MX28_PAD_AUART1_TX__GPIO_3_5 0x3053
|
||||
MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063
|
||||
MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073
|
||||
MX28_PAD_AUART2_RX__GPIO_3_8 0x3083
|
||||
MX28_PAD_AUART2_TX__GPIO_3_9 0x3093
|
||||
MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3
|
||||
MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3
|
||||
MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3
|
||||
MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3
|
||||
MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3
|
||||
MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3
|
||||
MX28_PAD_PWM0__GPIO_3_16 0x3103
|
||||
MX28_PAD_PWM1__GPIO_3_17 0x3113
|
||||
MX28_PAD_PWM2__GPIO_3_18 0x3123
|
||||
MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143
|
||||
MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153
|
||||
MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163
|
||||
MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173
|
||||
MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183
|
||||
MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193
|
||||
MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3
|
||||
MX28_PAD_SPDIF__GPIO_3_27 0x31b3
|
||||
MX28_PAD_PWM3__GPIO_3_28 0x31c3
|
||||
MX28_PAD_PWM4__GPIO_3_29 0x31d3
|
||||
MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3
|
||||
MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003
|
||||
MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013
|
||||
MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023
|
||||
MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033
|
||||
MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043
|
||||
MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053
|
||||
MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063
|
||||
MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073
|
||||
MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083
|
||||
MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093
|
||||
MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3
|
||||
MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3
|
||||
MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3
|
||||
MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3
|
||||
MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3
|
||||
MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3
|
||||
MX28_PAD_ENET_CLK__GPIO_4_16 0x4103
|
||||
MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143
|
||||
|
||||
Valid values for i.MX23 pinmux-id:
|
||||
|
||||
pinmux id
|
||||
------ --
|
||||
MX23_PAD_GPMI_D00__GPMI_D00 0x0000
|
||||
MX23_PAD_GPMI_D01__GPMI_D01 0x0010
|
||||
MX23_PAD_GPMI_D02__GPMI_D02 0x0020
|
||||
MX23_PAD_GPMI_D03__GPMI_D03 0x0030
|
||||
MX23_PAD_GPMI_D04__GPMI_D04 0x0040
|
||||
MX23_PAD_GPMI_D05__GPMI_D05 0x0050
|
||||
MX23_PAD_GPMI_D06__GPMI_D06 0x0060
|
||||
MX23_PAD_GPMI_D07__GPMI_D07 0x0070
|
||||
MX23_PAD_GPMI_D08__GPMI_D08 0x0080
|
||||
MX23_PAD_GPMI_D09__GPMI_D09 0x0090
|
||||
MX23_PAD_GPMI_D10__GPMI_D10 0x00a0
|
||||
MX23_PAD_GPMI_D11__GPMI_D11 0x00b0
|
||||
MX23_PAD_GPMI_D12__GPMI_D12 0x00c0
|
||||
MX23_PAD_GPMI_D13__GPMI_D13 0x00d0
|
||||
MX23_PAD_GPMI_D14__GPMI_D14 0x00e0
|
||||
MX23_PAD_GPMI_D15__GPMI_D15 0x00f0
|
||||
MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100
|
||||
MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110
|
||||
MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
|
||||
MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130
|
||||
MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140
|
||||
MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150
|
||||
MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160
|
||||
MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170
|
||||
MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180
|
||||
MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190
|
||||
MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0
|
||||
MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0
|
||||
MX23_PAD_AUART1_RX__AUART1_RX 0x01c0
|
||||
MX23_PAD_AUART1_TX__AUART1_TX 0x01d0
|
||||
MX23_PAD_I2C_SCL__I2C_SCL 0x01e0
|
||||
MX23_PAD_I2C_SDA__I2C_SDA 0x01f0
|
||||
MX23_PAD_LCD_D00__LCD_D00 0x1000
|
||||
MX23_PAD_LCD_D01__LCD_D01 0x1010
|
||||
MX23_PAD_LCD_D02__LCD_D02 0x1020
|
||||
MX23_PAD_LCD_D03__LCD_D03 0x1030
|
||||
MX23_PAD_LCD_D04__LCD_D04 0x1040
|
||||
MX23_PAD_LCD_D05__LCD_D05 0x1050
|
||||
MX23_PAD_LCD_D06__LCD_D06 0x1060
|
||||
MX23_PAD_LCD_D07__LCD_D07 0x1070
|
||||
MX23_PAD_LCD_D08__LCD_D08 0x1080
|
||||
MX23_PAD_LCD_D09__LCD_D09 0x1090
|
||||
MX23_PAD_LCD_D10__LCD_D10 0x10a0
|
||||
MX23_PAD_LCD_D11__LCD_D11 0x10b0
|
||||
MX23_PAD_LCD_D12__LCD_D12 0x10c0
|
||||
MX23_PAD_LCD_D13__LCD_D13 0x10d0
|
||||
MX23_PAD_LCD_D14__LCD_D14 0x10e0
|
||||
MX23_PAD_LCD_D15__LCD_D15 0x10f0
|
||||
MX23_PAD_LCD_D16__LCD_D16 0x1100
|
||||
MX23_PAD_LCD_D17__LCD_D17 0x1110
|
||||
MX23_PAD_LCD_RESET__LCD_RESET 0x1120
|
||||
MX23_PAD_LCD_RS__LCD_RS 0x1130
|
||||
MX23_PAD_LCD_WR__LCD_WR 0x1140
|
||||
MX23_PAD_LCD_CS__LCD_CS 0x1150
|
||||
MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160
|
||||
MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170
|
||||
MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180
|
||||
MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190
|
||||
MX23_PAD_PWM0__PWM0 0x11a0
|
||||
MX23_PAD_PWM1__PWM1 0x11b0
|
||||
MX23_PAD_PWM2__PWM2 0x11c0
|
||||
MX23_PAD_PWM3__PWM3 0x11d0
|
||||
MX23_PAD_PWM4__PWM4 0x11e0
|
||||
MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000
|
||||
MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010
|
||||
MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020
|
||||
MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030
|
||||
MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040
|
||||
MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050
|
||||
MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060
|
||||
MX23_PAD_ROTARYA__ROTARYA 0x2070
|
||||
MX23_PAD_ROTARYB__ROTARYB 0x2080
|
||||
MX23_PAD_EMI_A00__EMI_A00 0x2090
|
||||
MX23_PAD_EMI_A01__EMI_A01 0x20a0
|
||||
MX23_PAD_EMI_A02__EMI_A02 0x20b0
|
||||
MX23_PAD_EMI_A03__EMI_A03 0x20c0
|
||||
MX23_PAD_EMI_A04__EMI_A04 0x20d0
|
||||
MX23_PAD_EMI_A05__EMI_A05 0x20e0
|
||||
MX23_PAD_EMI_A06__EMI_A06 0x20f0
|
||||
MX23_PAD_EMI_A07__EMI_A07 0x2100
|
||||
MX23_PAD_EMI_A08__EMI_A08 0x2110
|
||||
MX23_PAD_EMI_A09__EMI_A09 0x2120
|
||||
MX23_PAD_EMI_A10__EMI_A10 0x2130
|
||||
MX23_PAD_EMI_A11__EMI_A11 0x2140
|
||||
MX23_PAD_EMI_A12__EMI_A12 0x2150
|
||||
MX23_PAD_EMI_BA0__EMI_BA0 0x2160
|
||||
MX23_PAD_EMI_BA1__EMI_BA1 0x2170
|
||||
MX23_PAD_EMI_CASN__EMI_CASN 0x2180
|
||||
MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190
|
||||
MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0
|
||||
MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0
|
||||
MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0
|
||||
MX23_PAD_EMI_CKE__EMI_CKE 0x21d0
|
||||
MX23_PAD_EMI_RASN__EMI_RASN 0x21e0
|
||||
MX23_PAD_EMI_WEN__EMI_WEN 0x21f0
|
||||
MX23_PAD_EMI_D00__EMI_D00 0x3000
|
||||
MX23_PAD_EMI_D01__EMI_D01 0x3010
|
||||
MX23_PAD_EMI_D02__EMI_D02 0x3020
|
||||
MX23_PAD_EMI_D03__EMI_D03 0x3030
|
||||
MX23_PAD_EMI_D04__EMI_D04 0x3040
|
||||
MX23_PAD_EMI_D05__EMI_D05 0x3050
|
||||
MX23_PAD_EMI_D06__EMI_D06 0x3060
|
||||
MX23_PAD_EMI_D07__EMI_D07 0x3070
|
||||
MX23_PAD_EMI_D08__EMI_D08 0x3080
|
||||
MX23_PAD_EMI_D09__EMI_D09 0x3090
|
||||
MX23_PAD_EMI_D10__EMI_D10 0x30a0
|
||||
MX23_PAD_EMI_D11__EMI_D11 0x30b0
|
||||
MX23_PAD_EMI_D12__EMI_D12 0x30c0
|
||||
MX23_PAD_EMI_D13__EMI_D13 0x30d0
|
||||
MX23_PAD_EMI_D14__EMI_D14 0x30e0
|
||||
MX23_PAD_EMI_D15__EMI_D15 0x30f0
|
||||
MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100
|
||||
MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110
|
||||
MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120
|
||||
MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130
|
||||
MX23_PAD_EMI_CLK__EMI_CLK 0x3140
|
||||
MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150
|
||||
MX23_PAD_GPMI_D00__LCD_D8 0x0001
|
||||
MX23_PAD_GPMI_D01__LCD_D9 0x0011
|
||||
MX23_PAD_GPMI_D02__LCD_D10 0x0021
|
||||
MX23_PAD_GPMI_D03__LCD_D11 0x0031
|
||||
MX23_PAD_GPMI_D04__LCD_D12 0x0041
|
||||
MX23_PAD_GPMI_D05__LCD_D13 0x0051
|
||||
MX23_PAD_GPMI_D06__LCD_D14 0x0061
|
||||
MX23_PAD_GPMI_D07__LCD_D15 0x0071
|
||||
MX23_PAD_GPMI_D08__LCD_D18 0x0081
|
||||
MX23_PAD_GPMI_D09__LCD_D19 0x0091
|
||||
MX23_PAD_GPMI_D10__LCD_D20 0x00a1
|
||||
MX23_PAD_GPMI_D11__LCD_D21 0x00b1
|
||||
MX23_PAD_GPMI_D12__LCD_D22 0x00c1
|
||||
MX23_PAD_GPMI_D13__LCD_D23 0x00d1
|
||||
MX23_PAD_GPMI_D14__AUART2_RX 0x00e1
|
||||
MX23_PAD_GPMI_D15__AUART2_TX 0x00f1
|
||||
MX23_PAD_GPMI_CLE__LCD_D16 0x0101
|
||||
MX23_PAD_GPMI_ALE__LCD_D17 0x0111
|
||||
MX23_PAD_GPMI_CE2N__ATA_A2 0x0121
|
||||
MX23_PAD_AUART1_RTS__IR_CLK 0x01b1
|
||||
MX23_PAD_AUART1_RX__IR_RX 0x01c1
|
||||
MX23_PAD_AUART1_TX__IR_TX 0x01d1
|
||||
MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1
|
||||
MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1
|
||||
MX23_PAD_LCD_D00__ETM_DA8 0x1001
|
||||
MX23_PAD_LCD_D01__ETM_DA9 0x1011
|
||||
MX23_PAD_LCD_D02__ETM_DA10 0x1021
|
||||
MX23_PAD_LCD_D03__ETM_DA11 0x1031
|
||||
MX23_PAD_LCD_D04__ETM_DA12 0x1041
|
||||
MX23_PAD_LCD_D05__ETM_DA13 0x1051
|
||||
MX23_PAD_LCD_D06__ETM_DA14 0x1061
|
||||
MX23_PAD_LCD_D07__ETM_DA15 0x1071
|
||||
MX23_PAD_LCD_D08__ETM_DA0 0x1081
|
||||
MX23_PAD_LCD_D09__ETM_DA1 0x1091
|
||||
MX23_PAD_LCD_D10__ETM_DA2 0x10a1
|
||||
MX23_PAD_LCD_D11__ETM_DA3 0x10b1
|
||||
MX23_PAD_LCD_D12__ETM_DA4 0x10c1
|
||||
MX23_PAD_LCD_D13__ETM_DA5 0x10d1
|
||||
MX23_PAD_LCD_D14__ETM_DA6 0x10e1
|
||||
MX23_PAD_LCD_D15__ETM_DA7 0x10f1
|
||||
MX23_PAD_LCD_RESET__ETM_TCTL 0x1121
|
||||
MX23_PAD_LCD_RS__ETM_TCLK 0x1131
|
||||
MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161
|
||||
MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171
|
||||
MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181
|
||||
MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191
|
||||
MX23_PAD_PWM0__ROTARYA 0x11a1
|
||||
MX23_PAD_PWM1__ROTARYB 0x11b1
|
||||
MX23_PAD_PWM2__GPMI_RDY3 0x11c1
|
||||
MX23_PAD_PWM3__ETM_TCTL 0x11d1
|
||||
MX23_PAD_PWM4__ETM_TCLK 0x11e1
|
||||
MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011
|
||||
MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031
|
||||
MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041
|
||||
MX23_PAD_ROTARYA__AUART2_RTS 0x2071
|
||||
MX23_PAD_ROTARYB__AUART2_CTS 0x2081
|
||||
MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002
|
||||
MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012
|
||||
MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022
|
||||
MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032
|
||||
MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042
|
||||
MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052
|
||||
MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062
|
||||
MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072
|
||||
MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082
|
||||
MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092
|
||||
MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2
|
||||
MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2
|
||||
MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2
|
||||
MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132
|
||||
MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142
|
||||
MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182
|
||||
MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2
|
||||
MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2
|
||||
MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2
|
||||
MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2
|
||||
MX23_PAD_I2C_SCL__AUART1_TX 0x01e2
|
||||
MX23_PAD_I2C_SDA__AUART1_RX 0x01f2
|
||||
MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082
|
||||
MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092
|
||||
MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2
|
||||
MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2
|
||||
MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2
|
||||
MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2
|
||||
MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2
|
||||
MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2
|
||||
MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102
|
||||
MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122
|
||||
MX23_PAD_PWM0__DUART_RX 0x11a2
|
||||
MX23_PAD_PWM1__DUART_TX 0x11b2
|
||||
MX23_PAD_PWM3__AUART1_CTS 0x11d2
|
||||
MX23_PAD_PWM4__AUART1_RTS 0x11e2
|
||||
MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002
|
||||
MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012
|
||||
MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022
|
||||
MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032
|
||||
MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042
|
||||
MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052
|
||||
MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062
|
||||
MX23_PAD_ROTARYA__SPDIF 0x2072
|
||||
MX23_PAD_ROTARYB__GPMI_CE3N 0x2082
|
||||
MX23_PAD_GPMI_D00__GPIO_0_0 0x0003
|
||||
MX23_PAD_GPMI_D01__GPIO_0_1 0x0013
|
||||
MX23_PAD_GPMI_D02__GPIO_0_2 0x0023
|
||||
MX23_PAD_GPMI_D03__GPIO_0_3 0x0033
|
||||
MX23_PAD_GPMI_D04__GPIO_0_4 0x0043
|
||||
MX23_PAD_GPMI_D05__GPIO_0_5 0x0053
|
||||
MX23_PAD_GPMI_D06__GPIO_0_6 0x0063
|
||||
MX23_PAD_GPMI_D07__GPIO_0_7 0x0073
|
||||
MX23_PAD_GPMI_D08__GPIO_0_8 0x0083
|
||||
MX23_PAD_GPMI_D09__GPIO_0_9 0x0093
|
||||
MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3
|
||||
MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3
|
||||
MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3
|
||||
MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3
|
||||
MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3
|
||||
MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3
|
||||
MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103
|
||||
MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113
|
||||
MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123
|
||||
MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133
|
||||
MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143
|
||||
MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153
|
||||
MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163
|
||||
MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173
|
||||
MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183
|
||||
MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193
|
||||
MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3
|
||||
MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3
|
||||
MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3
|
||||
MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3
|
||||
MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3
|
||||
MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3
|
||||
MX23_PAD_LCD_D00__GPIO_1_0 0x1003
|
||||
MX23_PAD_LCD_D01__GPIO_1_1 0x1013
|
||||
MX23_PAD_LCD_D02__GPIO_1_2 0x1023
|
||||
MX23_PAD_LCD_D03__GPIO_1_3 0x1033
|
||||
MX23_PAD_LCD_D04__GPIO_1_4 0x1043
|
||||
MX23_PAD_LCD_D05__GPIO_1_5 0x1053
|
||||
MX23_PAD_LCD_D06__GPIO_1_6 0x1063
|
||||
MX23_PAD_LCD_D07__GPIO_1_7 0x1073
|
||||
MX23_PAD_LCD_D08__GPIO_1_8 0x1083
|
||||
MX23_PAD_LCD_D09__GPIO_1_9 0x1093
|
||||
MX23_PAD_LCD_D10__GPIO_1_10 0x10a3
|
||||
MX23_PAD_LCD_D11__GPIO_1_11 0x10b3
|
||||
MX23_PAD_LCD_D12__GPIO_1_12 0x10c3
|
||||
MX23_PAD_LCD_D13__GPIO_1_13 0x10d3
|
||||
MX23_PAD_LCD_D14__GPIO_1_14 0x10e3
|
||||
MX23_PAD_LCD_D15__GPIO_1_15 0x10f3
|
||||
MX23_PAD_LCD_D16__GPIO_1_16 0x1103
|
||||
MX23_PAD_LCD_D17__GPIO_1_17 0x1113
|
||||
MX23_PAD_LCD_RESET__GPIO_1_18 0x1123
|
||||
MX23_PAD_LCD_RS__GPIO_1_19 0x1133
|
||||
MX23_PAD_LCD_WR__GPIO_1_20 0x1143
|
||||
MX23_PAD_LCD_CS__GPIO_1_21 0x1153
|
||||
MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163
|
||||
MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173
|
||||
MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183
|
||||
MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193
|
||||
MX23_PAD_PWM0__GPIO_1_26 0x11a3
|
||||
MX23_PAD_PWM1__GPIO_1_27 0x11b3
|
||||
MX23_PAD_PWM2__GPIO_1_28 0x11c3
|
||||
MX23_PAD_PWM3__GPIO_1_29 0x11d3
|
||||
MX23_PAD_PWM4__GPIO_1_30 0x11e3
|
||||
MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003
|
||||
MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013
|
||||
MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023
|
||||
MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033
|
||||
MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043
|
||||
MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053
|
||||
MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063
|
||||
MX23_PAD_ROTARYA__GPIO_2_7 0x2073
|
||||
MX23_PAD_ROTARYB__GPIO_2_8 0x2083
|
||||
MX23_PAD_EMI_A00__GPIO_2_9 0x2093
|
||||
MX23_PAD_EMI_A01__GPIO_2_10 0x20a3
|
||||
MX23_PAD_EMI_A02__GPIO_2_11 0x20b3
|
||||
MX23_PAD_EMI_A03__GPIO_2_12 0x20c3
|
||||
MX23_PAD_EMI_A04__GPIO_2_13 0x20d3
|
||||
MX23_PAD_EMI_A05__GPIO_2_14 0x20e3
|
||||
MX23_PAD_EMI_A06__GPIO_2_15 0x20f3
|
||||
MX23_PAD_EMI_A07__GPIO_2_16 0x2103
|
||||
MX23_PAD_EMI_A08__GPIO_2_17 0x2113
|
||||
MX23_PAD_EMI_A09__GPIO_2_18 0x2123
|
||||
MX23_PAD_EMI_A10__GPIO_2_19 0x2133
|
||||
MX23_PAD_EMI_A11__GPIO_2_20 0x2143
|
||||
MX23_PAD_EMI_A12__GPIO_2_21 0x2153
|
||||
MX23_PAD_EMI_BA0__GPIO_2_22 0x2163
|
||||
MX23_PAD_EMI_BA1__GPIO_2_23 0x2173
|
||||
MX23_PAD_EMI_CASN__GPIO_2_24 0x2183
|
||||
MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193
|
||||
MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3
|
||||
MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3
|
||||
MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3
|
||||
MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3
|
||||
MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3
|
||||
MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3
|
||||
@ -0,0 +1,132 @@
|
||||
NVIDIA Tegra20 pinmux controller
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,tegra20-pinmux"
|
||||
- reg: Should contain the register physical address and length for each of
|
||||
the tri-state, mux, pull-up/down, and pad control register sets.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Tegra's pin configuration nodes act as a container for an abitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, tristate, drive strength, etc.
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function or tristate parameter. For this
|
||||
reason, even seemingly boolean values are actually tristates in this binding:
|
||||
unspecified, off, or on. Unspecified is represented as an absent property,
|
||||
and off/on are represented as integer values 0 and 1.
|
||||
|
||||
Required subnode-properties:
|
||||
- nvidia,pins : An array of strings. Each string contains the name of a pin or
|
||||
group. Valid values for these names are listed below.
|
||||
|
||||
Optional subnode-properties:
|
||||
- nvidia,function: A string containing the name of the function to mux to the
|
||||
pin or group. Valid values for function names are listed below. See the Tegra
|
||||
TRM to determine which are valid for each pin or group.
|
||||
- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
|
||||
0: none, 1: down, 2: up.
|
||||
- nvidia,tristate: Integer.
|
||||
0: drive, 1: tristate.
|
||||
- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
|
||||
0: no, 1: yes.
|
||||
- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
|
||||
0: no, 1: yes.
|
||||
- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
|
||||
most power. Controls the drive power or current. See "Low Power Mode"
|
||||
or "LPMD1" and "LPMD0" in the Tegra TRM.
|
||||
- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
|
||||
The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
|
||||
Tegra TRM.
|
||||
- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
|
||||
The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
|
||||
Tegra TRM.
|
||||
- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
|
||||
fastest. The range of valid values depends on the pingroup. See
|
||||
"DRVDN_SLWR" in the Tegra TRM.
|
||||
- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
|
||||
fastest. The range of valid values depends on the pingroup. See
|
||||
"DRVUP_SLWF" in the Tegra TRM.
|
||||
|
||||
Note that many of these properties are only valid for certain specific pins
|
||||
or groups. See the Tegra TRM and various pinmux spreadsheets for complete
|
||||
details regarding which groups support which functionality. The Linux pinctrl
|
||||
driver may also be a useful reference, since it consolidates, disambiguates,
|
||||
and corrects data from all those sources.
|
||||
|
||||
Valid values for pin and group names are:
|
||||
|
||||
mux groups:
|
||||
|
||||
These all support nvidia,function, nvidia,tristate, and many support
|
||||
nvidia,pull.
|
||||
|
||||
ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
|
||||
ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
|
||||
gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
|
||||
ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
|
||||
ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
|
||||
lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
|
||||
owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
|
||||
spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
|
||||
uca, ucb, uda.
|
||||
|
||||
tristate groups:
|
||||
|
||||
These only support nvidia,pull.
|
||||
|
||||
ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
|
||||
ld19_18, ld21_20, ld23_22.
|
||||
|
||||
drive groups:
|
||||
|
||||
With some exceptions, these support nvidia,high-speed-mode,
|
||||
nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
|
||||
nvidia,pull-up-strength, nvidia,slew_rate-rising, nvidia,slew_rate-falling.
|
||||
|
||||
drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
|
||||
drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
|
||||
drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
|
||||
drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
|
||||
drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
|
||||
drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
|
||||
drive_uda.
|
||||
|
||||
Example:
|
||||
|
||||
pinctrl@70000000 {
|
||||
compatible = "nvidia,tegra20-pinmux";
|
||||
reg = < 0x70000014 0x10 /* Tri-state registers */
|
||||
0x70000080 0x20 /* Mux registers */
|
||||
0x700000a0 0x14 /* Pull-up/down registers */
|
||||
0x70000868 0xa8 >; /* Pad control registers */
|
||||
};
|
||||
|
||||
Example board file extract:
|
||||
|
||||
pinctrl@70000000 {
|
||||
sdio4_default: sdio4_default {
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma", "gme";
|
||||
nvidia,function = "sdio4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio4_default>;
|
||||
};
|
||||
@ -0,0 +1,132 @@
|
||||
NVIDIA Tegra30 pinmux controller
|
||||
|
||||
The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
|
||||
as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
|
||||
that binding as a baseline, and only documents the differences between the
|
||||
two bindings.
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,tegra30-pinmux"
|
||||
- reg: Should contain the register physical address and length for each of
|
||||
the pad control and mux registers.
|
||||
|
||||
Tegra30 adds the following optional properties for pin configuration subnodes:
|
||||
- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
|
||||
- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
|
||||
- nvidia,lock: Integer. Lock the pin configuration against further changes
|
||||
until reset. 0: no, 1: yes.
|
||||
- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
|
||||
|
||||
As with Tegra20, see the Tegra TRM for complete details regarding which groups
|
||||
support which functionality.
|
||||
|
||||
Valid values for pin and group names are:
|
||||
|
||||
per-pin mux groups:
|
||||
|
||||
These all support nvidia,function, nvidia,tristate, nvidia,pull,
|
||||
nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
|
||||
nvidia,io-reset.
|
||||
|
||||
clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3,
|
||||
dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0,
|
||||
gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
|
||||
sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1,
|
||||
uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5,
|
||||
lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2,
|
||||
sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7,
|
||||
lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5,
|
||||
lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3,
|
||||
lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0,
|
||||
gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
|
||||
gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
|
||||
gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
|
||||
gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4,
|
||||
gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1,
|
||||
gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
|
||||
uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2,
|
||||
gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7,
|
||||
vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5,
|
||||
vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
|
||||
lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0,
|
||||
dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5,
|
||||
lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
|
||||
ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
|
||||
ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3,
|
||||
dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0,
|
||||
kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
|
||||
kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
|
||||
kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
|
||||
kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
|
||||
kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
|
||||
vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
|
||||
sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0,
|
||||
pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7,
|
||||
lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
|
||||
clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1,
|
||||
spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6,
|
||||
spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3,
|
||||
sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
|
||||
sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4,
|
||||
sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0,
|
||||
sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
|
||||
sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
|
||||
cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7,
|
||||
cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4,
|
||||
clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7,
|
||||
pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
|
||||
pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
|
||||
pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1,
|
||||
clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr,
|
||||
pwr_int_n.
|
||||
|
||||
drive groups:
|
||||
|
||||
These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
|
||||
nvidia,slew_rate-rising, nvidia,slew_rate-falling. Most but not all
|
||||
support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
|
||||
|
||||
ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,
|
||||
dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg,
|
||||
gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
|
||||
uart3, uda, vi1.
|
||||
|
||||
Example:
|
||||
|
||||
pinctrl@70000000 {
|
||||
compatible = "nvidia,tegra30-pinmux";
|
||||
reg = < 0x70000868 0xd0 /* Pad control registers */
|
||||
0x70003000 0x3e0 >; /* Mux registers */
|
||||
};
|
||||
|
||||
Example board file extract:
|
||||
|
||||
pinctrl@70000000 {
|
||||
sdmmc4_default: pinmux {
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4",
|
||||
"sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc4_dat0_paa0 {
|
||||
nvidia,pins = "sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@78000400 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc4_default>;
|
||||
};
|
||||
128
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
Normal file
128
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
Normal file
@ -0,0 +1,128 @@
|
||||
== Introduction ==
|
||||
|
||||
Hardware modules that control pin multiplexing or configuration parameters
|
||||
such as pull-up/down, tri-state, drive-strength etc are designated as pin
|
||||
controllers. Each pin controller must be represented as a node in device tree,
|
||||
just like any other hardware module.
|
||||
|
||||
Hardware modules whose signals are affected by pin configuration are
|
||||
designated client devices. Again, each client device must be represented as a
|
||||
node in device tree, just like any other hardware module.
|
||||
|
||||
For a client device to operate correctly, certain pin controllers must
|
||||
set up certain specific pin configurations. Some client devices need a
|
||||
single static pin configuration, e.g. set up during initialization. Others
|
||||
need to reconfigure pins at run-time, for example to tri-state pins when the
|
||||
device is inactive. Hence, each client device can define a set of named
|
||||
states. The number and names of those states is defined by the client device's
|
||||
own binding.
|
||||
|
||||
The common pinctrl bindings defined in this file provide an infrastructure
|
||||
for client device device tree nodes to map those state names to the pin
|
||||
configuration used by those states.
|
||||
|
||||
Note that pin controllers themselves may also be client devices of themselves.
|
||||
For example, a pin controller may set up its own "active" state when the
|
||||
driver loads. This would allow representing a board's static pin configuration
|
||||
in a single place, rather than splitting it across multiple client device
|
||||
nodes. The decision to do this or not somewhat rests with the author of
|
||||
individual board device tree files, and any requirements imposed by the
|
||||
bindings for the individual client devices in use by that board, i.e. whether
|
||||
they require certain specific named states for dynamic pin configuration.
|
||||
|
||||
== Pinctrl client devices ==
|
||||
|
||||
For each client device individually, every pin state is assigned an integer
|
||||
ID. These numbers start at 0, and are contiguous. For each state ID, a unique
|
||||
property exists to define the pin configuration. Each state may also be
|
||||
assigned a name. When names are used, another property exists to map from
|
||||
those names to the integer IDs.
|
||||
|
||||
Each client device's own binding determines the set of states the must be
|
||||
defined in its device tree node, and whether to define the set of state
|
||||
IDs that must be provided, or whether to define the set of state names that
|
||||
must be provided.
|
||||
|
||||
Required properties:
|
||||
pinctrl-0: List of phandles, each pointing at a pin configuration
|
||||
node. These referenced pin configuration nodes must be child
|
||||
nodes of the pin controller that they configure. Multiple
|
||||
entries may exist in this list so that multiple pin
|
||||
controllers may be configured, or so that a state may be built
|
||||
from multiple nodes for a single pin controller, each
|
||||
contributing part of the overall configuration. See the next
|
||||
section of this document for details of the format of these
|
||||
pin configuration nodes.
|
||||
|
||||
In some cases, it may be useful to define a state, but for it
|
||||
to be empty. This may be required when a common IP block is
|
||||
used in an SoC either without a pin controller, or where the
|
||||
pin controller does not affect the HW module in question. If
|
||||
the binding for that IP block requires certain pin states to
|
||||
exist, they must still be defined, but may be left empty.
|
||||
|
||||
Optional properties:
|
||||
pinctrl-1: List of phandles, each pointing at a pin configuration
|
||||
node within a pin controller.
|
||||
...
|
||||
pinctrl-n: List of phandles, each pointing at a pin configuration
|
||||
node within a pin controller.
|
||||
pinctrl-names: The list of names to assign states. List entry 0 defines the
|
||||
name for integer state ID 0, list entry 1 for state ID 1, and
|
||||
so on.
|
||||
|
||||
For example:
|
||||
|
||||
/* For a client device requiring named states */
|
||||
device {
|
||||
pinctrl-names = "active", "idle";
|
||||
pinctrl-0 = <&state_0_node_a>;
|
||||
pinctrl-1 = <&state_1_node_a &state_1_node_b>;
|
||||
};
|
||||
|
||||
/* For the same device if using state IDs */
|
||||
device {
|
||||
pinctrl-0 = <&state_0_node_a>;
|
||||
pinctrl-1 = <&state_1_node_a &state_1_node_b>;
|
||||
};
|
||||
|
||||
/*
|
||||
* For an IP block whose binding supports pin configuration,
|
||||
* but in use on an SoC that doesn't have any pin control hardware
|
||||
*/
|
||||
device {
|
||||
pinctrl-names = "active", "idle";
|
||||
pinctrl-0 = <>;
|
||||
pinctrl-1 = <>;
|
||||
};
|
||||
|
||||
== Pin controller devices ==
|
||||
|
||||
Pin controller devices should contain the pin configuration nodes that client
|
||||
devices reference.
|
||||
|
||||
For example:
|
||||
|
||||
pincontroller {
|
||||
... /* Standard DT properties for the device itself elided */
|
||||
|
||||
state_0_node_a {
|
||||
...
|
||||
};
|
||||
state_1_node_a {
|
||||
...
|
||||
};
|
||||
state_1_node_b {
|
||||
...
|
||||
};
|
||||
}
|
||||
|
||||
The contents of each of those pin configuration child nodes is defined
|
||||
entirely by the binding for the individual pin controller device. There
|
||||
exists no common standard for this content.
|
||||
|
||||
The pin configuration nodes need not be direct children of the pin controller
|
||||
device; they may be grandchildren, for example. Whether this is legal, and
|
||||
whether there is any interaction between the child and intermediate parent
|
||||
nodes, is again defined entirely by the binding for the individual pin
|
||||
controller device.
|
||||
108
Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
Normal file
108
Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
Normal file
@ -0,0 +1,108 @@
|
||||
ST Microelectronics, SPEAr pinmux controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "st,spear300-pinmux"
|
||||
: "st,spear310-pinmux"
|
||||
: "st,spear320-pinmux"
|
||||
- reg : Address range of the pinctrl registers
|
||||
- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
|
||||
- Its values for SPEAr300:
|
||||
- NAND_MODE : <0>
|
||||
- NOR_MODE : <1>
|
||||
- PHOTO_FRAME_MODE : <2>
|
||||
- LEND_IP_PHONE_MODE : <3>
|
||||
- HEND_IP_PHONE_MODE : <4>
|
||||
- LEND_WIFI_PHONE_MODE : <5>
|
||||
- HEND_WIFI_PHONE_MODE : <6>
|
||||
- ATA_PABX_WI2S_MODE : <7>
|
||||
- ATA_PABX_I2S_MODE : <8>
|
||||
- CAML_LCDW_MODE : <9>
|
||||
- CAMU_LCD_MODE : <10>
|
||||
- CAMU_WLCD_MODE : <11>
|
||||
- CAML_LCD_MODE : <12>
|
||||
- Its values for SPEAr320:
|
||||
- AUTO_NET_SMII_MODE : <0>
|
||||
- AUTO_NET_MII_MODE : <1>
|
||||
- AUTO_EXP_MODE : <2>
|
||||
- SMALL_PRINTERS_MODE : <3>
|
||||
- EXTENDED_MODE : <4>
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the common
|
||||
pinctrl bindings used by client devices.
|
||||
|
||||
SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each
|
||||
of these subnodes represents muxing for a pin, a group, or a list of pins or
|
||||
groups.
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Required subnode-properties:
|
||||
- st,pins : An array of strings. Each string contains the name of a pin or
|
||||
group.
|
||||
- st,function: A string containing the name of the function to mux to the pin or
|
||||
group. See the SPEAr's TRM to determine which are valid for each pin or group.
|
||||
|
||||
Valid values for group and function names can be found from looking at the
|
||||
group and function arrays in driver files:
|
||||
drivers/pinctrl/spear/pinctrl-spear3*0.c
|
||||
|
||||
Valid values for group names are:
|
||||
For All SPEAr3xx machines:
|
||||
"firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp",
|
||||
"gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp",
|
||||
"gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp",
|
||||
"timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp"
|
||||
|
||||
For SPEAr300 machines:
|
||||
"fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp",
|
||||
"clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp",
|
||||
"dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp",
|
||||
"gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
|
||||
|
||||
For SPEAr310 machines:
|
||||
"emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp",
|
||||
"uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp"
|
||||
|
||||
For SPEAr320 machines:
|
||||
"clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp",
|
||||
"sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp",
|
||||
"uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp",
|
||||
"uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp",
|
||||
"uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp",
|
||||
"uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp",
|
||||
"uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp",
|
||||
"uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
|
||||
"uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp",
|
||||
"uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp",
|
||||
"uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp",
|
||||
"can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp",
|
||||
"pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp",
|
||||
"pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp",
|
||||
"pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp",
|
||||
"pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp",
|
||||
"pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp",
|
||||
"pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp",
|
||||
"ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp",
|
||||
"ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp",
|
||||
"ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp",
|
||||
"rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
|
||||
"i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
|
||||
|
||||
Valid values for function names are:
|
||||
For All SPEAr3xx machines:
|
||||
"firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
|
||||
"uart0", "timer_0_1", "timer_2_3"
|
||||
|
||||
For SPEAr300 machines:
|
||||
"fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1"
|
||||
|
||||
For SPEAr310 machines:
|
||||
"emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0",
|
||||
"rs485_1", "tdm"
|
||||
|
||||
For SPEAr320 machines:
|
||||
"clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem",
|
||||
"uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
|
||||
"can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
|
||||
"mii0_1", "i2c1", "i2c2"
|
||||
@ -1,5 +0,0 @@
|
||||
NVIDIA Tegra 2 pinmux controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "nvidia,tegra20-pinmux"
|
||||
|
||||
@ -280,3 +280,7 @@ REGULATOR
|
||||
CLOCK
|
||||
devm_clk_get()
|
||||
devm_clk_put()
|
||||
|
||||
PINCTRL
|
||||
devm_pinctrl_get()
|
||||
devm_pinctrl_put()
|
||||
|
||||
@ -152,11 +152,9 @@ static const struct foo_group foo_groups[] = {
|
||||
};
|
||||
|
||||
|
||||
static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
|
||||
static int foo_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
if (selector >= ARRAY_SIZE(foo_groups))
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
return ARRAY_SIZE(foo_groups);
|
||||
}
|
||||
|
||||
static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
|
||||
@ -175,7 +173,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
|
||||
}
|
||||
|
||||
static struct pinctrl_ops foo_pctrl_ops = {
|
||||
.list_groups = foo_list_groups,
|
||||
.get_groups_count = foo_get_groups_count,
|
||||
.get_group_name = foo_get_group_name,
|
||||
.get_group_pins = foo_get_group_pins,
|
||||
};
|
||||
@ -186,13 +184,12 @@ static struct pinctrl_desc foo_desc = {
|
||||
.pctlops = &foo_pctrl_ops,
|
||||
};
|
||||
|
||||
The pin control subsystem will call the .list_groups() function repeatedly
|
||||
beginning on 0 until it returns non-zero to determine legal selectors, then
|
||||
it will call the other functions to retrieve the name and pins of the group.
|
||||
Maintaining the data structure of the groups is up to the driver, this is
|
||||
just a simple example - in practice you may need more entries in your group
|
||||
structure, for example specific register ranges associated with each group
|
||||
and so on.
|
||||
The pin control subsystem will call the .get_groups_count() function to
|
||||
determine total number of legal selectors, then it will call the other functions
|
||||
to retrieve the name and pins of the group. Maintaining the data structure of
|
||||
the groups is up to the driver, this is just a simple example - in practice you
|
||||
may need more entries in your group structure, for example specific register
|
||||
ranges associated with each group and so on.
|
||||
|
||||
|
||||
Pin configuration
|
||||
@ -606,11 +603,9 @@ static const struct foo_group foo_groups[] = {
|
||||
};
|
||||
|
||||
|
||||
static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
|
||||
static int foo_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
if (selector >= ARRAY_SIZE(foo_groups))
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
return ARRAY_SIZE(foo_groups);
|
||||
}
|
||||
|
||||
static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
|
||||
@ -629,7 +624,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
|
||||
}
|
||||
|
||||
static struct pinctrl_ops foo_pctrl_ops = {
|
||||
.list_groups = foo_list_groups,
|
||||
.get_groups_count = foo_get_groups_count,
|
||||
.get_group_name = foo_get_group_name,
|
||||
.get_group_pins = foo_get_group_pins,
|
||||
};
|
||||
@ -640,7 +635,7 @@ struct foo_pmx_func {
|
||||
const unsigned num_groups;
|
||||
};
|
||||
|
||||
static const char * const spi0_groups[] = { "spi0_1_grp" };
|
||||
static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
|
||||
static const char * const i2c0_groups[] = { "i2c0_grp" };
|
||||
static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
|
||||
"mmc0_3_grp" };
|
||||
@ -663,11 +658,9 @@ static const struct foo_pmx_func foo_functions[] = {
|
||||
},
|
||||
};
|
||||
|
||||
int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
|
||||
int foo_get_functions_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
if (selector >= ARRAY_SIZE(foo_functions))
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
return ARRAY_SIZE(foo_functions);
|
||||
}
|
||||
|
||||
const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
|
||||
@ -703,7 +696,7 @@ void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
|
||||
}
|
||||
|
||||
struct pinmux_ops foo_pmxops = {
|
||||
.list_functions = foo_list_funcs,
|
||||
.get_functions_count = foo_get_functions_count,
|
||||
.get_function_name = foo_get_fname,
|
||||
.get_function_groups = foo_get_groups,
|
||||
.enable = foo_enable,
|
||||
@ -786,7 +779,7 @@ and spi on the second function mapping:
|
||||
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
static const struct pinctrl_map __initdata mapping[] = {
|
||||
static const struct pinctrl_map mapping[] __initconst = {
|
||||
{
|
||||
.dev_name = "foo-spi.0",
|
||||
.name = PINCTRL_STATE_DEFAULT,
|
||||
@ -952,13 +945,13 @@ case), we define a mapping like this:
|
||||
The result of grabbing this mapping from the device with something like
|
||||
this (see next paragraph):
|
||||
|
||||
p = pinctrl_get(dev);
|
||||
p = devm_pinctrl_get(dev);
|
||||
s = pinctrl_lookup_state(p, "8bit");
|
||||
ret = pinctrl_select_state(p, s);
|
||||
|
||||
or more simply:
|
||||
|
||||
p = pinctrl_get_select(dev, "8bit");
|
||||
p = devm_pinctrl_get_select(dev, "8bit");
|
||||
|
||||
Will be that you activate all the three bottom records in the mapping at
|
||||
once. Since they share the same name, pin controller device, function and
|
||||
@ -992,7 +985,7 @@ foo_probe()
|
||||
/* Allocate a state holder named "foo" etc */
|
||||
struct foo_state *foo = ...;
|
||||
|
||||
foo->p = pinctrl_get(&device);
|
||||
foo->p = devm_pinctrl_get(&device);
|
||||
if (IS_ERR(foo->p)) {
|
||||
/* FIXME: clean up "foo" here */
|
||||
return PTR_ERR(foo->p);
|
||||
@ -1000,24 +993,17 @@ foo_probe()
|
||||
|
||||
foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
|
||||
if (IS_ERR(foo->s)) {
|
||||
pinctrl_put(foo->p);
|
||||
/* FIXME: clean up "foo" here */
|
||||
return PTR_ERR(s);
|
||||
}
|
||||
|
||||
ret = pinctrl_select_state(foo->s);
|
||||
if (ret < 0) {
|
||||
pinctrl_put(foo->p);
|
||||
/* FIXME: clean up "foo" here */
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
foo_remove()
|
||||
{
|
||||
pinctrl_put(state->p);
|
||||
}
|
||||
|
||||
This get/lookup/select/put sequence can just as well be handled by bus drivers
|
||||
if you don't want each and every driver to handle it and you know the
|
||||
arrangement on your bus.
|
||||
@ -1029,6 +1015,11 @@ The semantics of the pinctrl APIs are:
|
||||
kernel memory to hold the pinmux state. All mapping table parsing or similar
|
||||
slow operations take place within this API.
|
||||
|
||||
- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
|
||||
to be called automatically on the retrieved pointer when the associated
|
||||
device is removed. It is recommended to use this function over plain
|
||||
pinctrl_get().
|
||||
|
||||
- pinctrl_lookup_state() is called in process context to obtain a handle to a
|
||||
specific state for a the client device. This operation may be slow too.
|
||||
|
||||
@ -1041,14 +1032,30 @@ The semantics of the pinctrl APIs are:
|
||||
|
||||
- pinctrl_put() frees all information associated with a pinctrl handle.
|
||||
|
||||
- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
|
||||
explicitly destroy a pinctrl object returned by devm_pinctrl_get().
|
||||
However, use of this function will be rare, due to the automatic cleanup
|
||||
that will occur even without calling it.
|
||||
|
||||
pinctrl_get() must be paired with a plain pinctrl_put().
|
||||
pinctrl_get() may not be paired with devm_pinctrl_put().
|
||||
devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
|
||||
devm_pinctrl_get() may not be paired with plain pinctrl_put().
|
||||
|
||||
Usually the pin control core handled the get/put pair and call out to the
|
||||
device drivers bookkeeping operations, like checking available functions and
|
||||
the associated pins, whereas the enable/disable pass on to the pin controller
|
||||
driver which takes care of activating and/or deactivating the mux setting by
|
||||
quickly poking some registers.
|
||||
|
||||
The pins are allocated for your device when you issue the pinctrl_get() call,
|
||||
after this you should be able to see this in the debugfs listing of all pins.
|
||||
The pins are allocated for your device when you issue the devm_pinctrl_get()
|
||||
call, after this you should be able to see this in the debugfs listing of all
|
||||
pins.
|
||||
|
||||
NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
|
||||
requested pinctrl handles, for example if the pinctrl driver has not yet
|
||||
registered. Thus make sure that the error path in your driver gracefully
|
||||
cleans up and is ready to retry the probing later in the startup process.
|
||||
|
||||
|
||||
System pin control hogging
|
||||
@ -1094,13 +1101,13 @@ it, disables and releases it, and muxes it in on the pins defined by group B:
|
||||
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
foo_switch()
|
||||
{
|
||||
struct pinctrl *p;
|
||||
struct pinctrl_state *s1, *s2;
|
||||
struct pinctrl *p;
|
||||
struct pinctrl_state *s1, *s2;
|
||||
|
||||
foo_probe()
|
||||
{
|
||||
/* Setup */
|
||||
p = pinctrl_get(&device);
|
||||
p = devm_pinctrl_get(&device);
|
||||
if (IS_ERR(p))
|
||||
...
|
||||
|
||||
@ -1111,7 +1118,10 @@ foo_switch()
|
||||
s2 = pinctrl_lookup_state(foo->p, "pos-B");
|
||||
if (IS_ERR(s2))
|
||||
...
|
||||
}
|
||||
|
||||
foo_switch()
|
||||
{
|
||||
/* Enable on position A */
|
||||
ret = pinctrl_select_state(s1);
|
||||
if (ret < 0)
|
||||
@ -1125,8 +1135,6 @@ foo_switch()
|
||||
...
|
||||
|
||||
...
|
||||
|
||||
pinctrl_put(p);
|
||||
}
|
||||
|
||||
The above has to be done from process context.
|
||||
|
||||
23
MAINTAINERS
23
MAINTAINERS
@ -5242,6 +5242,14 @@ M: Linus Walleij <linus.walleij@linaro.org>
|
||||
S: Maintained
|
||||
F: drivers/pinctrl/
|
||||
|
||||
PIN CONTROLLER - ST SPEAR
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.st.com/spear
|
||||
S: Maintained
|
||||
F: driver/pinctrl/spear/
|
||||
|
||||
PKTCDVD DRIVER
|
||||
M: Peter Osterlund <petero2@telia.com>
|
||||
S: Maintained
|
||||
@ -6336,21 +6344,6 @@ W: http://www.st.com/spear
|
||||
S: Maintained
|
||||
F: drivers/clk/spear/
|
||||
|
||||
SPEAR PAD MULTIPLEXING SUPPORT
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.st.com/spear
|
||||
S: Maintained
|
||||
F: arch/arm/plat-spear/include/plat/padmux.h
|
||||
F: arch/arm/plat-spear/padmux.c
|
||||
F: arch/arm/mach-spear*/spear*xx.c
|
||||
F: arch/arm/mach-spear*/include/mach/generic.h
|
||||
F: arch/arm/mach-spear3xx/spear3*0.c
|
||||
F: arch/arm/mach-spear3xx/spear3*0_evb.c
|
||||
F: arch/arm/mach-spear6xx/spear600.c
|
||||
F: arch/arm/mach-spear6xx/spear600_evb.c
|
||||
|
||||
SPI SUBSYSTEM
|
||||
M: Grant Likely <grant.likely@secretlab.ca>
|
||||
L: spi-devel-general@lists.sourceforge.net
|
||||
|
||||
@ -470,6 +470,7 @@ config ARCH_MXS
|
||||
select CLKSRC_MMIO
|
||||
select COMMON_CLK
|
||||
select HAVE_CLK_PREPARE
|
||||
select PINCTRL
|
||||
help
|
||||
Support for Freescale MXS-based family of processors
|
||||
|
||||
|
||||
246
arch/arm/boot/dts/spear300-evb.dts
Normal file
246
arch/arm/boot/dts/spear300-evb.dts
Normal file
@ -0,0 +1,246 @@
|
||||
/*
|
||||
* DTS file for SPEAr300 Evaluation Baord
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "spear300.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ST SPEAr300 Evaluation Board";
|
||||
compatible = "st,spear300-evb", "st,spear300";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memory {
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
pinmux@99000000 {
|
||||
st,pinmux-mode = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
i2c0 {
|
||||
st,pins = "i2c0_grp";
|
||||
st,function = "i2c0";
|
||||
};
|
||||
ssp0 {
|
||||
st,pins = "ssp0_grp";
|
||||
st,function = "ssp0";
|
||||
};
|
||||
mii0 {
|
||||
st,pins = "mii0_grp";
|
||||
st,function = "mii0";
|
||||
};
|
||||
uart0 {
|
||||
st,pins = "uart0_grp";
|
||||
st,function = "uart0";
|
||||
};
|
||||
clcd {
|
||||
st,pins = "clcd_pfmode_grp";
|
||||
st,function = "clcd";
|
||||
};
|
||||
sdhci {
|
||||
st,pins = "sdhci_4bit_grp";
|
||||
st,function = "sdhci";
|
||||
};
|
||||
gpio1 {
|
||||
st,pins = "gpio1_4_to_7_grp",
|
||||
"gpio1_0_to_3_grp";
|
||||
st,function = "gpio1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clcd@60000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
dma@fc400000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
fsmc: flash@94000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gmac: eth@e0800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@70000000 {
|
||||
int-gpio = <&gpio1 0 0>;
|
||||
power-gpio = <&gpio1 2 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
smi: flash@fc000000 {
|
||||
status = "okay";
|
||||
clock-rate=<50000000>;
|
||||
|
||||
flash@f8000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xf8000000 0x800000>;
|
||||
st,smi-fast-mode;
|
||||
|
||||
partition@0 {
|
||||
label = "xloader";
|
||||
reg = <0x0 0x10000>;
|
||||
};
|
||||
partition@10000 {
|
||||
label = "u-boot";
|
||||
reg = <0x10000 0x40000>;
|
||||
};
|
||||
partition@50000 {
|
||||
label = "linux";
|
||||
reg = <0x50000 0x2c0000>;
|
||||
};
|
||||
partition@310000 {
|
||||
label = "rootfs";
|
||||
reg = <0x310000 0x4f0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@d0100000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ehci@e1800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ohci@e1900000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ohci@e2100000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
apb {
|
||||
gpio0: gpio@fc980000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gpio1: gpio@a9000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@d0180000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
kbd@a0000000 {
|
||||
linux,keymap = < 0x00000001
|
||||
0x00010002
|
||||
0x00020003
|
||||
0x00030004
|
||||
0x00040005
|
||||
0x00050006
|
||||
0x00060007
|
||||
0x00070008
|
||||
0x00080009
|
||||
0x0100000a
|
||||
0x0101000c
|
||||
0x0102000d
|
||||
0x0103000e
|
||||
0x0104000f
|
||||
0x01050010
|
||||
0x01060011
|
||||
0x01070012
|
||||
0x01080013
|
||||
0x02000014
|
||||
0x02010015
|
||||
0x02020016
|
||||
0x02030017
|
||||
0x02040018
|
||||
0x02050019
|
||||
0x0206001a
|
||||
0x0207001b
|
||||
0x0208001c
|
||||
0x0300001d
|
||||
0x0301001e
|
||||
0x0302001f
|
||||
0x03030020
|
||||
0x03040021
|
||||
0x03050022
|
||||
0x03060023
|
||||
0x03070024
|
||||
0x03080025
|
||||
0x04000026
|
||||
0x04010027
|
||||
0x04020028
|
||||
0x04030029
|
||||
0x0404002a
|
||||
0x0405002b
|
||||
0x0406002c
|
||||
0x0407002d
|
||||
0x0408002e
|
||||
0x0500002f
|
||||
0x05010030
|
||||
0x05020031
|
||||
0x05030032
|
||||
0x05040033
|
||||
0x05050034
|
||||
0x05060035
|
||||
0x05070036
|
||||
0x05080037
|
||||
0x06000038
|
||||
0x06010039
|
||||
0x0602003a
|
||||
0x0603003b
|
||||
0x0604003c
|
||||
0x0605003d
|
||||
0x0606003e
|
||||
0x0607003f
|
||||
0x06080040
|
||||
0x07000041
|
||||
0x07010042
|
||||
0x07020043
|
||||
0x07030044
|
||||
0x07040045
|
||||
0x07050046
|
||||
0x07060047
|
||||
0x07070048
|
||||
0x07080049
|
||||
0x0800004a
|
||||
0x0801004b
|
||||
0x0802004c
|
||||
0x0803004d
|
||||
0x0804004e
|
||||
0x0805004f
|
||||
0x08060050
|
||||
0x08070051
|
||||
0x08080052 >;
|
||||
autorepeat;
|
||||
st,mode = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
rtc@fc900000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@d0000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wdt@fc880000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
77
arch/arm/boot/dts/spear300.dtsi
Normal file
77
arch/arm/boot/dts/spear300.dtsi
Normal file
@ -0,0 +1,77 @@
|
||||
/*
|
||||
* DTS file for SPEAr300 SoC
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "spear3xx.dtsi"
|
||||
|
||||
/ {
|
||||
ahb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x60000000 0x60000000 0x50000000
|
||||
0xd0000000 0xd0000000 0x30000000>;
|
||||
|
||||
pinmux@99000000 {
|
||||
compatible = "st,spear300-pinmux";
|
||||
reg = <0x99000000 0x1000>;
|
||||
};
|
||||
|
||||
clcd@60000000 {
|
||||
compatible = "arm,clcd-pl110", "arm,primecell";
|
||||
reg = <0x60000000 0x1000>;
|
||||
interrupts = <30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fsmc: flash@94000000 {
|
||||
compatible = "st,spear600-fsmc-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x94000000 0x1000 /* FSMC Register */
|
||||
0x80000000 0x0010>; /* NAND Base */
|
||||
reg-names = "fsmc_regs", "nand_data";
|
||||
st,ale-off = <0x20000>;
|
||||
st,cle-off = <0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@70000000 {
|
||||
compatible = "st,sdhci-spear";
|
||||
reg = <0x70000000 0x100>;
|
||||
interrupts = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
apb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0xa0000000 0xa0000000 0x10000000
|
||||
0xd0000000 0xd0000000 0x30000000>;
|
||||
|
||||
gpio1: gpio@a9000000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
gpio-controller;
|
||||
reg = <0xa9000000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
kbd@a0000000 {
|
||||
compatible = "st,spear300-kbd";
|
||||
reg = <0xa0000000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
188
arch/arm/boot/dts/spear310-evb.dts
Normal file
188
arch/arm/boot/dts/spear310-evb.dts
Normal file
@ -0,0 +1,188 @@
|
||||
/*
|
||||
* DTS file for SPEAr310 Evaluation Baord
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "spear310.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ST SPEAr310 Evaluation Board";
|
||||
compatible = "st,spear310-evb", "st,spear310";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memory {
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
pinmux@b4000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
gpio0 {
|
||||
st,pins = "gpio0_pin0_grp",
|
||||
"gpio0_pin1_grp",
|
||||
"gpio0_pin2_grp",
|
||||
"gpio0_pin3_grp",
|
||||
"gpio0_pin4_grp",
|
||||
"gpio0_pin5_grp";
|
||||
st,function = "gpio0";
|
||||
};
|
||||
i2c0 {
|
||||
st,pins = "i2c0_grp";
|
||||
st,function = "i2c0";
|
||||
};
|
||||
mii0 {
|
||||
st,pins = "mii0_grp";
|
||||
st,function = "mii0";
|
||||
};
|
||||
ssp0 {
|
||||
st,pins = "ssp0_grp";
|
||||
st,function = "ssp0";
|
||||
};
|
||||
uart0 {
|
||||
st,pins = "uart0_grp";
|
||||
st,function = "uart0";
|
||||
};
|
||||
emi {
|
||||
st,pins = "emi_cs_0_to_5_grp";
|
||||
st,function = "emi";
|
||||
};
|
||||
fsmc {
|
||||
st,pins = "fsmc_grp";
|
||||
st,function = "fsmc";
|
||||
};
|
||||
uart1 {
|
||||
st,pins = "uart1_grp";
|
||||
st,function = "uart1";
|
||||
};
|
||||
uart2 {
|
||||
st,pins = "uart2_grp";
|
||||
st,function = "uart2";
|
||||
};
|
||||
uart3 {
|
||||
st,pins = "uart3_grp";
|
||||
st,function = "uart3";
|
||||
};
|
||||
uart4 {
|
||||
st,pins = "uart4_grp";
|
||||
st,function = "uart4";
|
||||
};
|
||||
uart5 {
|
||||
st,pins = "uart5_grp";
|
||||
st,function = "uart5";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dma@fc400000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
fsmc: flash@44000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gmac: eth@e0800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
smi: flash@fc000000 {
|
||||
status = "okay";
|
||||
clock-rate=<50000000>;
|
||||
|
||||
flash@f8000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xf8000000 0x800000>;
|
||||
st,smi-fast-mode;
|
||||
|
||||
partition@0 {
|
||||
label = "xloader";
|
||||
reg = <0x0 0x10000>;
|
||||
};
|
||||
partition@10000 {
|
||||
label = "u-boot";
|
||||
reg = <0x10000 0x40000>;
|
||||
};
|
||||
partition@50000 {
|
||||
label = "linux";
|
||||
reg = <0x50000 0x2c0000>;
|
||||
};
|
||||
partition@310000 {
|
||||
label = "rootfs";
|
||||
reg = <0x310000 0x4f0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@d0100000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ehci@e1800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ohci@e1900000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ohci@e2100000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
apb {
|
||||
gpio0: gpio@fc980000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@d0180000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
rtc@fc900000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@d0000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@b2000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@b2080000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@b2100000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@b2180000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@b2200000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wdt@fc880000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
80
arch/arm/boot/dts/spear310.dtsi
Normal file
80
arch/arm/boot/dts/spear310.dtsi
Normal file
@ -0,0 +1,80 @@
|
||||
/*
|
||||
* DTS file for SPEAr310 SoC
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "spear3xx.dtsi"
|
||||
|
||||
/ {
|
||||
ahb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x40000000 0x40000000 0x10000000
|
||||
0xb0000000 0xb0000000 0x10000000
|
||||
0xd0000000 0xd0000000 0x30000000>;
|
||||
|
||||
pinmux@b4000000 {
|
||||
compatible = "st,spear310-pinmux";
|
||||
reg = <0xb4000000 0x1000>;
|
||||
};
|
||||
|
||||
fsmc: flash@44000000 {
|
||||
compatible = "st,spear600-fsmc-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x44000000 0x1000 /* FSMC Register */
|
||||
0x40000000 0x0010>; /* NAND Base */
|
||||
reg-names = "fsmc_regs", "nand_data";
|
||||
st,ale-off = <0x10000>;
|
||||
st,cle-off = <0x20000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
apb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0xb0000000 0xb0000000 0x10000000
|
||||
0xd0000000 0xd0000000 0x30000000>;
|
||||
|
||||
serial@b2000000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xb2000000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@b2080000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xb2080000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@b2100000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xb2100000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@b2180000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xb2180000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@b2200000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xb2200000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
198
arch/arm/boot/dts/spear320-evb.dts
Normal file
198
arch/arm/boot/dts/spear320-evb.dts
Normal file
@ -0,0 +1,198 @@
|
||||
/*
|
||||
* DTS file for SPEAr320 Evaluation Baord
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "spear320.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ST SPEAr300 Evaluation Board";
|
||||
compatible = "st,spear300-evb", "st,spear300";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memory {
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
pinmux@b3000000 {
|
||||
st,pinmux-mode = <3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
state_default: pinmux {
|
||||
i2c0 {
|
||||
st,pins = "i2c0_grp";
|
||||
st,function = "i2c0";
|
||||
};
|
||||
mii0 {
|
||||
st,pins = "mii0_grp";
|
||||
st,function = "mii0";
|
||||
};
|
||||
ssp0 {
|
||||
st,pins = "ssp0_grp";
|
||||
st,function = "ssp0";
|
||||
};
|
||||
uart0 {
|
||||
st,pins = "uart0_grp";
|
||||
st,function = "uart0";
|
||||
};
|
||||
sdhci {
|
||||
st,pins = "sdhci_cd_51_grp";
|
||||
st,function = "sdhci";
|
||||
};
|
||||
i2s {
|
||||
st,pins = "i2s_grp";
|
||||
st,function = "i2s";
|
||||
};
|
||||
uart1 {
|
||||
st,pins = "uart1_grp";
|
||||
st,function = "uart1";
|
||||
};
|
||||
uart2 {
|
||||
st,pins = "uart2_grp";
|
||||
st,function = "uart2";
|
||||
};
|
||||
can0 {
|
||||
st,pins = "can0_grp";
|
||||
st,function = "can0";
|
||||
};
|
||||
can1 {
|
||||
st,pins = "can1_grp";
|
||||
st,function = "can1";
|
||||
};
|
||||
mii2 {
|
||||
st,pins = "mii2_grp";
|
||||
st,function = "mii2";
|
||||
};
|
||||
pwm0_1 {
|
||||
st,pins = "pwm0_1_pin_14_15_grp";
|
||||
st,function = "pwm0_1";
|
||||
};
|
||||
pwm2 {
|
||||
st,pins = "pwm2_pin_13_grp";
|
||||
st,function = "pwm2";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clcd@90000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
dma@fc400000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
fsmc: flash@4c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gmac: eth@e0800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@70000000 {
|
||||
power-gpio = <&gpio0 2 1>;
|
||||
power_always_enb;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
smi: flash@fc000000 {
|
||||
status = "okay";
|
||||
clock-rate=<50000000>;
|
||||
|
||||
flash@f8000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xf8000000 0x800000>;
|
||||
st,smi-fast-mode;
|
||||
|
||||
partition@0 {
|
||||
label = "xloader";
|
||||
reg = <0x0 0x10000>;
|
||||
};
|
||||
partition@10000 {
|
||||
label = "u-boot";
|
||||
reg = <0x10000 0x40000>;
|
||||
};
|
||||
partition@50000 {
|
||||
label = "linux";
|
||||
reg = <0x50000 0x2c0000>;
|
||||
};
|
||||
partition@310000 {
|
||||
label = "rootfs";
|
||||
reg = <0x310000 0x4f0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@d0100000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi1: spi@a5000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi2: spi@a6000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ehci@e1800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ohci@e1900000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ohci@e2100000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
apb {
|
||||
gpio0: gpio@fc980000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@d0180000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@a7000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
rtc@fc900000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@d0000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@a3000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@a4000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wdt@fc880000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
95
arch/arm/boot/dts/spear320.dtsi
Normal file
95
arch/arm/boot/dts/spear320.dtsi
Normal file
@ -0,0 +1,95 @@
|
||||
/*
|
||||
* DTS file for SPEAr320 SoC
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "spear3xx.dtsi"
|
||||
|
||||
/ {
|
||||
ahb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x40000000 0x40000000 0x80000000
|
||||
0xd0000000 0xd0000000 0x30000000>;
|
||||
|
||||
pinmux@b3000000 {
|
||||
compatible = "st,spear320-pinmux";
|
||||
reg = <0xb3000000 0x1000>;
|
||||
};
|
||||
|
||||
clcd@90000000 {
|
||||
compatible = "arm,clcd-pl110", "arm,primecell";
|
||||
reg = <0x90000000 0x1000>;
|
||||
interrupts = <33>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fsmc: flash@4c000000 {
|
||||
compatible = "st,spear600-fsmc-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x4c000000 0x1000 /* FSMC Register */
|
||||
0x50000000 0x0010>; /* NAND Base */
|
||||
reg-names = "fsmc_regs", "nand_data";
|
||||
st,ale-off = <0x20000>;
|
||||
st,cle-off = <0x10000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@70000000 {
|
||||
compatible = "st,sdhci-spear";
|
||||
reg = <0x70000000 0x100>;
|
||||
interrupts = <29>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@a5000000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0xa5000000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@a6000000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0xa6000000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
apb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0xa0000000 0xa0000000 0x10000000
|
||||
0xd0000000 0xd0000000 0x30000000>;
|
||||
|
||||
i2c1: i2c@a7000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xa7000000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@a3000000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xa3000000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@a4000000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xa4000000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
150
arch/arm/boot/dts/spear3xx.dtsi
Normal file
150
arch/arm/boot/dts/spear3xx.dtsi
Normal file
@ -0,0 +1,150 @@
|
||||
/*
|
||||
* DTS file for all SPEAr3xx SoCs
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&vic>;
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,arm926ejs";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0xd0000000 0xd0000000 0x30000000>;
|
||||
|
||||
vic: interrupt-controller@f1100000 {
|
||||
compatible = "arm,pl190-vic";
|
||||
interrupt-controller;
|
||||
reg = <0xf1100000 0x1000>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
dma@fc400000 {
|
||||
compatible = "arm,pl080", "arm,primecell";
|
||||
reg = <0xfc400000 0x1000>;
|
||||
interrupt-parent = <&vic>;
|
||||
interrupts = <8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac: eth@e0800000 {
|
||||
compatible = "st,spear600-gmac";
|
||||
reg = <0xe0800000 0x8000>;
|
||||
interrupts = <23 22>;
|
||||
interrupt-names = "macirq", "eth_wake_irq";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
smi: flash@fc000000 {
|
||||
compatible = "st,spear600-smi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xfc000000 0x1000>;
|
||||
interrupts = <9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@d0100000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0xd0100000 0x1000>;
|
||||
interrupts = <20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci@e1800000 {
|
||||
compatible = "st,spear600-ehci", "usb-ehci";
|
||||
reg = <0xe1800000 0x1000>;
|
||||
interrupts = <26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci@e1900000 {
|
||||
compatible = "st,spear600-ohci", "usb-ohci";
|
||||
reg = <0xe1900000 0x1000>;
|
||||
interrupts = <25>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci@e2100000 {
|
||||
compatible = "st,spear600-ohci", "usb-ohci";
|
||||
reg = <0xe2100000 0x1000>;
|
||||
interrupts = <27>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
apb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0xd0000000 0xd0000000 0x30000000>;
|
||||
|
||||
gpio0: gpio@fc980000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0xfc980000 0x1000>;
|
||||
interrupts = <11>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@d0180000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xd0180000 0x1000>;
|
||||
interrupts = <21>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@fc900000 {
|
||||
compatible = "st,spear-rtc";
|
||||
reg = <0xfc900000 0x1000>;
|
||||
interrupts = <10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@d0000000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xd0000000 0x1000>;
|
||||
interrupts = <19>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt@fc880000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0xfc880000 0x1000>;
|
||||
interrupts = <12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@f0000000 {
|
||||
compatible = "st,spear-timer";
|
||||
reg = <0xf0000000 0x400>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -24,11 +24,44 @@
|
||||
};
|
||||
|
||||
ahb {
|
||||
dma@fc400000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gmac: ethernet@e0800000 {
|
||||
phy-mode = "gmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
smi: flash@fc000000 {
|
||||
status = "okay";
|
||||
clock-rate=<50000000>;
|
||||
|
||||
flash@f8000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xf8000000 0x800000>;
|
||||
st,smi-fast-mode;
|
||||
|
||||
partition@0 {
|
||||
label = "xloader";
|
||||
reg = <0x0 0x10000>;
|
||||
};
|
||||
partition@10000 {
|
||||
label = "u-boot";
|
||||
reg = <0x10000 0x40000>;
|
||||
};
|
||||
partition@50000 {
|
||||
label = "linux";
|
||||
reg = <0x50000 0x2c0000>;
|
||||
};
|
||||
partition@310000 {
|
||||
label = "rootfs";
|
||||
reg = <0x310000 0x4f0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
apb {
|
||||
serial@d0000000 {
|
||||
status = "okay";
|
||||
|
||||
@ -45,6 +45,14 @@
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
dma@fc400000 {
|
||||
compatible = "arm,pl080", "arm,primecell";
|
||||
reg = <0xfc400000 0x1000>;
|
||||
interrupt-parent = <&vic1>;
|
||||
interrupts = <10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac: ethernet@e0800000 {
|
||||
compatible = "st,spear600-gmac";
|
||||
reg = <0xe0800000 0x8000>;
|
||||
@ -169,6 +177,12 @@
|
||||
interrupts = <28>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@f0000000 {
|
||||
compatible = "st,spear-timer";
|
||||
reg = <0xf0000000 0x400>;
|
||||
interrupts = <16>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -2,33 +2,70 @@ CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_KALLSYMS_EXTRA_PASS=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_PLAT_SPEAR=y
|
||||
CONFIG_BOARD_SPEAR300_EVB=y
|
||||
CONFIG_BOARD_SPEAR310_EVB=y
|
||||
CONFIG_BOARD_SPEAR320_EVB=y
|
||||
CONFIG_MACH_SPEAR300=y
|
||||
CONFIG_MACH_SPEAR310=y
|
||||
CONFIG_MACH_SPEAR320=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_FSMC=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=16384
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_CIRRUS is not set
|
||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SMSC is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
# CONFIG_WLAN is not set
|
||||
CONFIG_INPUT_FF_MEMLESS=y
|
||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
CONFIG_KEYBOARD_SPEAR=y
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_RAW_DRIVER=y
|
||||
CONFIG_MAX_RAW_DEVS=8192
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_PL022=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_PL061=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_ARM_SP805_WATCHDOG=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_ARMCLCD=y
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_USB=y
|
||||
# CONFIG_USB_DEVICE_CLASS is not set
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SPEAR=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_AMBA_PL08X=y
|
||||
CONFIG_DMATEST=m
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_SECURITY=y
|
||||
@ -39,8 +76,7 @@ CONFIG_MSDOS_FS=m
|
||||
CONFIG_VFAT_FS=m
|
||||
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NLS_DEFAULT="utf8"
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=m
|
||||
@ -48,6 +84,4 @@ CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DEBUG_SPINLOCK=y
|
||||
CONFIG_DEBUG_SPINLOCK_SLEEP=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_CRC32 is not set
|
||||
|
||||
@ -2,29 +2,60 @@ CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_KALLSYMS_EXTRA_PASS=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_PLAT_SPEAR=y
|
||||
CONFIG_ARCH_SPEAR6XX=y
|
||||
CONFIG_BOARD_SPEAR600_EVB=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_FSMC=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=16384
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_CIRRUS is not set
|
||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SMSC is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
# CONFIG_WLAN is not set
|
||||
CONFIG_INPUT_FF_MEMLESS=y
|
||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_RAW_DRIVER=y
|
||||
CONFIG_MAX_RAW_DEVS=8192
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_PL022=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_PL061=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_ARM_SP805_WATCHDOG=y
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_AMBA_PL08X=y
|
||||
CONFIG_DMATEST=m
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_SECURITY=y
|
||||
@ -35,8 +66,7 @@ CONFIG_MSDOS_FS=m
|
||||
CONFIG_VFAT_FS=m
|
||||
CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NLS_DEFAULT="utf8"
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=m
|
||||
@ -44,6 +74,4 @@ CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DEBUG_SPINLOCK=y
|
||||
CONFIG_DEBUG_SPINLOCK_SLEEP=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_CRC32 is not set
|
||||
|
||||
@ -850,6 +850,8 @@ config SOC_IMX6Q
|
||||
select HAVE_IMX_MMDC
|
||||
select HAVE_IMX_SRC
|
||||
select HAVE_SMP
|
||||
select PINCTRL
|
||||
select PINCTRL_IMX6Q
|
||||
select USE_OF
|
||||
|
||||
help
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/common.h>
|
||||
@ -81,6 +82,8 @@ static void __init imx51_dt_init(void)
|
||||
|
||||
of_irq_init(imx51_irq_match);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
|
||||
if (node) {
|
||||
of_id = of_match_node(imx51_iomuxc_of_match, node);
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/common.h>
|
||||
@ -88,6 +89,8 @@ static void __init imx53_dt_init(void)
|
||||
|
||||
of_irq_init(imx53_irq_match);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
|
||||
if (node) {
|
||||
of_id = of_match_node(imx53_iomuxc_of_match, node);
|
||||
|
||||
@ -19,6 +19,7 @@
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/micrel_phy.h>
|
||||
#include <asm/smp_twd.h>
|
||||
@ -77,6 +78,12 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev)
|
||||
|
||||
static void __init imx6q_init_machine(void)
|
||||
{
|
||||
/*
|
||||
* This should be removed when all imx6q boards have pinctrl
|
||||
* states for devices defined in device tree.
|
||||
*/
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
|
||||
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
|
||||
ksz9021rn_phy_fixup);
|
||||
|
||||
@ -18,6 +18,7 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
@ -58,4 +59,5 @@ void __init imx1_soc_init(void)
|
||||
MX1_GPIO_INT_PORTC, 0);
|
||||
mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
|
||||
MX1_GPIO_INT_PORTD, 0);
|
||||
pinctrl_provide_dummies();
|
||||
}
|
||||
|
||||
@ -20,6 +20,7 @@
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/devices-common.h>
|
||||
@ -88,6 +89,7 @@ void __init imx21_soc_init(void)
|
||||
mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
|
||||
mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
imx_add_imx_dma();
|
||||
platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
|
||||
ARRAY_SIZE(imx21_audmux_res));
|
||||
|
||||
@ -19,6 +19,7 @@
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/mach/map.h>
|
||||
@ -95,6 +96,7 @@ void __init imx25_soc_init(void)
|
||||
mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
|
||||
mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
/* i.mx25 has the i.mx35 type sdma */
|
||||
imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
|
||||
/* i.mx25 has the i.mx31 type audmux */
|
||||
|
||||
@ -20,6 +20,7 @@
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/devices-common.h>
|
||||
@ -89,6 +90,7 @@ void __init imx27_soc_init(void)
|
||||
mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
|
||||
mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
imx_add_imx_dma();
|
||||
/* imx27 has the imx21 type audmux */
|
||||
platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
|
||||
|
||||
@ -19,6 +19,7 @@
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/system_misc.h>
|
||||
@ -273,6 +274,7 @@ void __init imx35_soc_init(void)
|
||||
mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
|
||||
mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
if (to_version == 1) {
|
||||
strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
|
||||
strlen(imx35_sdma_pdata.fw_name));
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/system_misc.h>
|
||||
#include <asm/mach/map.h>
|
||||
@ -224,6 +225,7 @@ void __init imx53_soc_init(void)
|
||||
mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
|
||||
mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
/* i.mx53 has the i.mx35 type sdma */
|
||||
imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
|
||||
|
||||
|
||||
@ -9,11 +9,13 @@ config SOC_IMX23
|
||||
bool
|
||||
select CPU_ARM926T
|
||||
select HAVE_PWM
|
||||
select PINCTRL_IMX23
|
||||
|
||||
config SOC_IMX28
|
||||
bool
|
||||
select CPU_ARM926T
|
||||
select HAVE_PWM
|
||||
select PINCTRL_IMX28
|
||||
|
||||
comment "MXS platforms:"
|
||||
|
||||
|
||||
@ -17,11 +17,13 @@ extern void mxs_timer_init(int);
|
||||
extern void mxs_restart(char, const char *);
|
||||
extern int mxs_saif_clkmux_select(unsigned int clkmux);
|
||||
|
||||
extern void mx23_soc_init(void);
|
||||
extern int mx23_register_gpios(void);
|
||||
extern int mx23_clocks_init(void);
|
||||
extern void mx23_map_io(void);
|
||||
extern void mx23_init_irq(void);
|
||||
|
||||
extern void mx28_soc_init(void);
|
||||
extern int mx28_register_gpios(void);
|
||||
extern int mx28_clocks_init(void);
|
||||
extern void mx28_map_io(void);
|
||||
|
||||
@ -207,6 +207,8 @@ static int apx4devkit_phy_fixup(struct phy_device *phy)
|
||||
|
||||
static void __init apx4devkit_init(void)
|
||||
{
|
||||
mx28_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(apx4devkit_pads,
|
||||
ARRAY_SIZE(apx4devkit_pads));
|
||||
|
||||
|
||||
@ -319,6 +319,8 @@ static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
|
||||
|
||||
static void __init m28evk_init(void)
|
||||
{
|
||||
mx28_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
|
||||
|
||||
mx28_add_duart();
|
||||
|
||||
@ -141,6 +141,8 @@ static void __init mx23evk_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
mx23_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
|
||||
|
||||
mx23_add_duart();
|
||||
|
||||
@ -413,6 +413,8 @@ static void __init mx28evk_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
mx28_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
|
||||
|
||||
mx28_add_duart();
|
||||
|
||||
@ -85,6 +85,8 @@ static void __init stmp378x_dvb_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
mx23_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
|
||||
ARRAY_SIZE(stmp378x_dvb_pads));
|
||||
|
||||
|
||||
@ -146,6 +146,8 @@ static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = {
|
||||
|
||||
static void __init tx28_stk5v3_init(void)
|
||||
{
|
||||
mx28_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
|
||||
ARRAY_SIZE(tx28_stk5v3_pads));
|
||||
|
||||
|
||||
@ -13,6 +13,7 @@
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
@ -61,3 +62,13 @@ void __init mx28_init_irq(void)
|
||||
{
|
||||
icoll_init_irq();
|
||||
}
|
||||
|
||||
void __init mx23_soc_init(void)
|
||||
{
|
||||
pinctrl_provide_dummies();
|
||||
}
|
||||
|
||||
void __init mx28_soc_init(void)
|
||||
{
|
||||
pinctrl_provide_dummies();
|
||||
}
|
||||
|
||||
@ -5,39 +5,22 @@
|
||||
if ARCH_SPEAR3XX
|
||||
|
||||
menu "SPEAr3xx Implementations"
|
||||
config BOARD_SPEAR300_EVB
|
||||
bool "SPEAr300 Evaluation Board"
|
||||
select MACH_SPEAR300
|
||||
help
|
||||
Supports ST SPEAr300 Evaluation Board
|
||||
|
||||
config BOARD_SPEAR310_EVB
|
||||
bool "SPEAr310 Evaluation Board"
|
||||
select MACH_SPEAR310
|
||||
help
|
||||
Supports ST SPEAr310 Evaluation Board
|
||||
|
||||
config BOARD_SPEAR320_EVB
|
||||
bool "SPEAr320 Evaluation Board"
|
||||
select MACH_SPEAR320
|
||||
help
|
||||
Supports ST SPEAr320 Evaluation Board
|
||||
|
||||
endmenu
|
||||
|
||||
config MACH_SPEAR300
|
||||
bool "SPEAr300"
|
||||
bool "SPEAr300 Machine support with Device Tree"
|
||||
select PINCTRL_SPEAR300
|
||||
help
|
||||
Supports ST SPEAr300 Machine
|
||||
Supports ST SPEAr300 machine configured via the device-tree
|
||||
|
||||
config MACH_SPEAR310
|
||||
bool "SPEAr310"
|
||||
bool "SPEAr310 Machine support with Device Tree"
|
||||
select PINCTRL_SPEAR310
|
||||
help
|
||||
Supports ST SPEAr310 Machine
|
||||
Supports ST SPEAr310 machine configured via the device-tree
|
||||
|
||||
config MACH_SPEAR320
|
||||
bool "SPEAr320"
|
||||
bool "SPEAr320 Machine support with Device Tree"
|
||||
select PINCTRL_SPEAR320
|
||||
help
|
||||
Supports ST SPEAr320 Machine
|
||||
|
||||
Supports ST SPEAr320 machine configured via the device-tree
|
||||
endmenu
|
||||
endif #ARCH_SPEAR3XX
|
||||
|
||||
@ -3,24 +3,13 @@
|
||||
#
|
||||
|
||||
# common files
|
||||
obj-y += spear3xx.o
|
||||
obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
|
||||
|
||||
# spear300 specific files
|
||||
obj-$(CONFIG_MACH_SPEAR300) += spear300.o
|
||||
|
||||
# spear300 boards files
|
||||
obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
|
||||
|
||||
|
||||
# spear310 specific files
|
||||
obj-$(CONFIG_MACH_SPEAR310) += spear310.o
|
||||
|
||||
# spear310 boards files
|
||||
obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
|
||||
|
||||
|
||||
# spear320 specific files
|
||||
obj-$(CONFIG_MACH_SPEAR320) += spear320.o
|
||||
|
||||
# spear320 boards files
|
||||
obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
|
||||
|
||||
@ -1,3 +1,7 @@
|
||||
zreladdr-y += 0x00008000
|
||||
params_phys-y := 0x00000100
|
||||
initrd_phys-y := 0x00800000
|
||||
|
||||
dtb-$(CONFIG_MACH_SPEAR300) += spear300-evb.dtb
|
||||
dtb-$(CONFIG_MACH_SPEAR310) += spear310-evb.dtb
|
||||
dtb-$(CONFIG_MACH_SPEAR320) += spear320-evb.dtb
|
||||
|
||||
@ -14,188 +14,24 @@
|
||||
#ifndef __MACH_GENERIC_H
|
||||
#define __MACH_GENERIC_H
|
||||
|
||||
#include <linux/amba/pl08x.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/amba/bus.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <plat/padmux.h>
|
||||
|
||||
/* spear3xx declarations */
|
||||
/*
|
||||
* Each GPT has 2 timer channels
|
||||
* Following GPT channels will be used as clock source and clockevent
|
||||
*/
|
||||
#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
|
||||
#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1
|
||||
#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
|
||||
|
||||
/* Add spear3xx family device structure declarations here */
|
||||
extern struct amba_device spear3xx_gpio_device;
|
||||
extern struct amba_device spear3xx_uart_device;
|
||||
extern struct sys_timer spear3xx_timer;
|
||||
extern struct pl022_ssp_controller pl022_plat_data;
|
||||
extern struct pl08x_platform_data pl080_plat_data;
|
||||
|
||||
/* Add spear3xx family function declarations here */
|
||||
void __init spear_setup_timer(void);
|
||||
void __init spear_setup_of_timer(void);
|
||||
void __init spear3xx_clk_init(void);
|
||||
void __init spear3xx_map_io(void);
|
||||
void __init spear3xx_init_irq(void);
|
||||
void __init spear3xx_init(void);
|
||||
void __init spear3xx_dt_init_irq(void);
|
||||
|
||||
void spear_restart(char, const char *);
|
||||
|
||||
/* pad mux declarations */
|
||||
#define PMX_FIRDA_MASK (1 << 14)
|
||||
#define PMX_I2C_MASK (1 << 13)
|
||||
#define PMX_SSP_CS_MASK (1 << 12)
|
||||
#define PMX_SSP_MASK (1 << 11)
|
||||
#define PMX_MII_MASK (1 << 10)
|
||||
#define PMX_GPIO_PIN0_MASK (1 << 9)
|
||||
#define PMX_GPIO_PIN1_MASK (1 << 8)
|
||||
#define PMX_GPIO_PIN2_MASK (1 << 7)
|
||||
#define PMX_GPIO_PIN3_MASK (1 << 6)
|
||||
#define PMX_GPIO_PIN4_MASK (1 << 5)
|
||||
#define PMX_GPIO_PIN5_MASK (1 << 4)
|
||||
#define PMX_UART0_MODEM_MASK (1 << 3)
|
||||
#define PMX_UART0_MASK (1 << 2)
|
||||
#define PMX_TIMER_3_4_MASK (1 << 1)
|
||||
#define PMX_TIMER_1_2_MASK (1 << 0)
|
||||
|
||||
/* pad mux devices */
|
||||
extern struct pmx_dev spear3xx_pmx_firda;
|
||||
extern struct pmx_dev spear3xx_pmx_i2c;
|
||||
extern struct pmx_dev spear3xx_pmx_ssp_cs;
|
||||
extern struct pmx_dev spear3xx_pmx_ssp;
|
||||
extern struct pmx_dev spear3xx_pmx_mii;
|
||||
extern struct pmx_dev spear3xx_pmx_gpio_pin0;
|
||||
extern struct pmx_dev spear3xx_pmx_gpio_pin1;
|
||||
extern struct pmx_dev spear3xx_pmx_gpio_pin2;
|
||||
extern struct pmx_dev spear3xx_pmx_gpio_pin3;
|
||||
extern struct pmx_dev spear3xx_pmx_gpio_pin4;
|
||||
extern struct pmx_dev spear3xx_pmx_gpio_pin5;
|
||||
extern struct pmx_dev spear3xx_pmx_uart0_modem;
|
||||
extern struct pmx_dev spear3xx_pmx_uart0;
|
||||
extern struct pmx_dev spear3xx_pmx_timer_3_4;
|
||||
extern struct pmx_dev spear3xx_pmx_timer_1_2;
|
||||
|
||||
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
|
||||
/* padmux plgpio devices */
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_28;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_29;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_30;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_31;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_32;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_33;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
|
||||
extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
|
||||
#endif
|
||||
|
||||
/* spear300 declarations */
|
||||
#ifdef CONFIG_MACH_SPEAR300
|
||||
/* Add spear300 machine device structure declarations here */
|
||||
extern struct amba_device spear300_gpio1_device;
|
||||
|
||||
/* pad mux modes */
|
||||
extern struct pmx_mode spear300_nand_mode;
|
||||
extern struct pmx_mode spear300_nor_mode;
|
||||
extern struct pmx_mode spear300_photo_frame_mode;
|
||||
extern struct pmx_mode spear300_lend_ip_phone_mode;
|
||||
extern struct pmx_mode spear300_hend_ip_phone_mode;
|
||||
extern struct pmx_mode spear300_lend_wifi_phone_mode;
|
||||
extern struct pmx_mode spear300_hend_wifi_phone_mode;
|
||||
extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
|
||||
extern struct pmx_mode spear300_ata_pabx_i2s_mode;
|
||||
extern struct pmx_mode spear300_caml_lcdw_mode;
|
||||
extern struct pmx_mode spear300_camu_lcd_mode;
|
||||
extern struct pmx_mode spear300_camu_wlcd_mode;
|
||||
extern struct pmx_mode spear300_caml_lcd_mode;
|
||||
|
||||
/* pad mux devices */
|
||||
extern struct pmx_dev spear300_pmx_fsmc_2_chips;
|
||||
extern struct pmx_dev spear300_pmx_fsmc_4_chips;
|
||||
extern struct pmx_dev spear300_pmx_keyboard;
|
||||
extern struct pmx_dev spear300_pmx_clcd;
|
||||
extern struct pmx_dev spear300_pmx_telecom_gpio;
|
||||
extern struct pmx_dev spear300_pmx_telecom_tdm;
|
||||
extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
|
||||
extern struct pmx_dev spear300_pmx_telecom_camera;
|
||||
extern struct pmx_dev spear300_pmx_telecom_dac;
|
||||
extern struct pmx_dev spear300_pmx_telecom_i2s;
|
||||
extern struct pmx_dev spear300_pmx_telecom_boot_pins;
|
||||
extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
|
||||
extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
|
||||
extern struct pmx_dev spear300_pmx_gpio1;
|
||||
|
||||
/* Add spear300 machine function declarations here */
|
||||
void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
|
||||
u8 pmx_dev_count);
|
||||
|
||||
#endif /* CONFIG_MACH_SPEAR300 */
|
||||
|
||||
/* spear310 declarations */
|
||||
#ifdef CONFIG_MACH_SPEAR310
|
||||
/* Add spear310 machine device structure declarations here */
|
||||
|
||||
/* pad mux devices */
|
||||
extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
|
||||
extern struct pmx_dev spear310_pmx_emi_cs_2_3;
|
||||
extern struct pmx_dev spear310_pmx_uart1;
|
||||
extern struct pmx_dev spear310_pmx_uart2;
|
||||
extern struct pmx_dev spear310_pmx_uart3_4_5;
|
||||
extern struct pmx_dev spear310_pmx_fsmc;
|
||||
extern struct pmx_dev spear310_pmx_rs485_0_1;
|
||||
extern struct pmx_dev spear310_pmx_tdm0;
|
||||
|
||||
/* Add spear310 machine function declarations here */
|
||||
void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
|
||||
u8 pmx_dev_count);
|
||||
#endif /* CONFIG_MACH_SPEAR310 */
|
||||
|
||||
/* spear320 declarations */
|
||||
#ifdef CONFIG_MACH_SPEAR320
|
||||
/* Add spear320 machine device structure declarations here */
|
||||
|
||||
/* pad mux modes */
|
||||
extern struct pmx_mode spear320_auto_net_smii_mode;
|
||||
extern struct pmx_mode spear320_auto_net_mii_mode;
|
||||
extern struct pmx_mode spear320_auto_exp_mode;
|
||||
extern struct pmx_mode spear320_small_printers_mode;
|
||||
|
||||
/* pad mux devices */
|
||||
extern struct pmx_dev spear320_pmx_clcd;
|
||||
extern struct pmx_dev spear320_pmx_emi;
|
||||
extern struct pmx_dev spear320_pmx_fsmc;
|
||||
extern struct pmx_dev spear320_pmx_spp;
|
||||
extern struct pmx_dev spear320_pmx_sdhci;
|
||||
extern struct pmx_dev spear320_pmx_i2s;
|
||||
extern struct pmx_dev spear320_pmx_uart1;
|
||||
extern struct pmx_dev spear320_pmx_uart1_modem;
|
||||
extern struct pmx_dev spear320_pmx_uart2;
|
||||
extern struct pmx_dev spear320_pmx_touchscreen;
|
||||
extern struct pmx_dev spear320_pmx_can;
|
||||
extern struct pmx_dev spear320_pmx_sdhci_led;
|
||||
extern struct pmx_dev spear320_pmx_pwm0;
|
||||
extern struct pmx_dev spear320_pmx_pwm1;
|
||||
extern struct pmx_dev spear320_pmx_pwm2;
|
||||
extern struct pmx_dev spear320_pmx_pwm3;
|
||||
extern struct pmx_dev spear320_pmx_ssp1;
|
||||
extern struct pmx_dev spear320_pmx_ssp2;
|
||||
extern struct pmx_dev spear320_pmx_mii1;
|
||||
extern struct pmx_dev spear320_pmx_smii0;
|
||||
extern struct pmx_dev spear320_pmx_smii1;
|
||||
extern struct pmx_dev spear320_pmx_i2c1;
|
||||
|
||||
/* Add spear320 machine function declarations here */
|
||||
void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
|
||||
u8 pmx_dev_count);
|
||||
|
||||
#endif /* CONFIG_MACH_SPEAR320 */
|
||||
|
||||
#endif /* __MACH_GENERIC_H */
|
||||
|
||||
@ -1,23 +1 @@
|
||||
/*
|
||||
* arch/arm/mach-spear3xx/include/mach/hardware.h
|
||||
*
|
||||
* Hardware definitions for SPEAr3xx machine family
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_HARDWARE_H
|
||||
#define __MACH_HARDWARE_H
|
||||
|
||||
#include <plat/hardware.h>
|
||||
#include <mach/spear.h>
|
||||
|
||||
/* Vitual to physical translation of statically mapped space */
|
||||
#define IO_ADDRESS(x) (x | 0xF0000000)
|
||||
|
||||
#endif /* __MACH_HARDWARE_H */
|
||||
/* empty */
|
||||
|
||||
@ -14,141 +14,14 @@
|
||||
#ifndef __MACH_IRQS_H
|
||||
#define __MACH_IRQS_H
|
||||
|
||||
/* SPEAr3xx IRQ definitions */
|
||||
#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0
|
||||
/* FIXME: probe all these from DT */
|
||||
#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
|
||||
#define SPEAR3XX_IRQ_CPU_GPT1_1 2
|
||||
#define SPEAR3XX_IRQ_CPU_GPT1_2 3
|
||||
#define SPEAR3XX_IRQ_BASIC_GPT1_1 4
|
||||
#define SPEAR3XX_IRQ_BASIC_GPT1_2 5
|
||||
#define SPEAR3XX_IRQ_BASIC_GPT2_1 6
|
||||
#define SPEAR3XX_IRQ_BASIC_GPT2_2 7
|
||||
#define SPEAR3XX_IRQ_BASIC_DMA 8
|
||||
#define SPEAR3XX_IRQ_BASIC_SMI 9
|
||||
#define SPEAR3XX_IRQ_BASIC_RTC 10
|
||||
#define SPEAR3XX_IRQ_BASIC_GPIO 11
|
||||
#define SPEAR3XX_IRQ_BASIC_WDT 12
|
||||
#define SPEAR3XX_IRQ_DDR_CONTROLLER 13
|
||||
#define SPEAR3XX_IRQ_SYS_ERROR 14
|
||||
#define SPEAR3XX_IRQ_WAKEUP_RCV 15
|
||||
#define SPEAR3XX_IRQ_JPEG 16
|
||||
#define SPEAR3XX_IRQ_IRDA 17
|
||||
#define SPEAR3XX_IRQ_ADC 18
|
||||
#define SPEAR3XX_IRQ_UART 19
|
||||
#define SPEAR3XX_IRQ_SSP 20
|
||||
#define SPEAR3XX_IRQ_I2C 21
|
||||
#define SPEAR3XX_IRQ_MAC_1 22
|
||||
#define SPEAR3XX_IRQ_MAC_2 23
|
||||
#define SPEAR3XX_IRQ_USB_DEV 24
|
||||
#define SPEAR3XX_IRQ_USB_H_OHCI_0 25
|
||||
#define SPEAR3XX_IRQ_USB_H_EHCI_0 26
|
||||
#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0
|
||||
#define SPEAR3XX_IRQ_USB_H_OHCI_1 27
|
||||
#define SPEAR3XX_IRQ_GEN_RAS_1 28
|
||||
#define SPEAR3XX_IRQ_GEN_RAS_2 29
|
||||
#define SPEAR3XX_IRQ_GEN_RAS_3 30
|
||||
#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31
|
||||
#define SPEAR3XX_IRQ_VIC_END 32
|
||||
|
||||
#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
|
||||
|
||||
/* SPEAr300 Virtual irq definitions */
|
||||
/* IRQs sharing IRQ_GEN_RAS_1 */
|
||||
#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
|
||||
#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
|
||||
#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
|
||||
#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
|
||||
#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
|
||||
#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
|
||||
#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
|
||||
#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
|
||||
#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
|
||||
|
||||
/* IRQs sharing IRQ_GEN_RAS_3 */
|
||||
#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
|
||||
|
||||
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
|
||||
#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
|
||||
|
||||
/* SPEAr310 Virtual irq definitions */
|
||||
/* IRQs sharing IRQ_GEN_RAS_1 */
|
||||
#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
|
||||
#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
|
||||
#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
|
||||
#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
|
||||
#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
|
||||
#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
|
||||
#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
|
||||
#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
|
||||
|
||||
/* IRQs sharing IRQ_GEN_RAS_2 */
|
||||
#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
|
||||
#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
|
||||
#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
|
||||
#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
|
||||
#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
|
||||
|
||||
/* IRQs sharing IRQ_GEN_RAS_3 */
|
||||
#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
|
||||
#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
|
||||
|
||||
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
|
||||
#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
|
||||
#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
|
||||
#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
|
||||
|
||||
/* SPEAr320 Virtual irq definitions */
|
||||
/* IRQs sharing IRQ_GEN_RAS_1 */
|
||||
#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
|
||||
#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
|
||||
#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
|
||||
|
||||
/* IRQs sharing IRQ_GEN_RAS_2 */
|
||||
#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
|
||||
|
||||
/* IRQs sharing IRQ_GEN_RAS_3 */
|
||||
#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
|
||||
#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
|
||||
#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
|
||||
|
||||
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
|
||||
#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
|
||||
#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
|
||||
#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
|
||||
#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
|
||||
#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
|
||||
#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
|
||||
#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
|
||||
#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
|
||||
#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
|
||||
#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
|
||||
#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
|
||||
|
||||
/*
|
||||
* GPIO pins virtual irqs
|
||||
* Use the lowest number for the GPIO virtual IRQs base on which subarchs
|
||||
* we have compiled in
|
||||
*/
|
||||
#if defined(CONFIG_MACH_SPEAR310)
|
||||
#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18)
|
||||
#elif defined(CONFIG_MACH_SPEAR320)
|
||||
#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17)
|
||||
#else
|
||||
#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9)
|
||||
#endif
|
||||
|
||||
#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
|
||||
#define SPEAR3XX_PLGPIO_COUNT 102
|
||||
|
||||
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
|
||||
#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
|
||||
#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \
|
||||
SPEAR3XX_PLGPIO_COUNT)
|
||||
#else
|
||||
#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8)
|
||||
#endif
|
||||
|
||||
#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END
|
||||
#define NR_IRQS SPEAR3XX_VIRQ_END
|
||||
#define NR_IRQS 160
|
||||
|
||||
#endif /* __MACH_IRQS_H */
|
||||
|
||||
@ -14,9 +14,9 @@
|
||||
#ifndef __MACH_MISC_REGS_H
|
||||
#define __MACH_MISC_REGS_H
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/spear.h>
|
||||
|
||||
#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
|
||||
#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
|
||||
|
||||
#endif /* __MACH_MISC_REGS_H */
|
||||
|
||||
@ -15,60 +15,26 @@
|
||||
#define __MACH_SPEAR3XX_H
|
||||
|
||||
#include <asm/memory.h>
|
||||
#include <mach/spear300.h>
|
||||
#include <mach/spear310.h>
|
||||
#include <mach/spear320.h>
|
||||
|
||||
#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000)
|
||||
|
||||
#define SPEAR3XX_ICM9_BASE UL(0xC0000000)
|
||||
|
||||
/* ICM1 - Low speed connection */
|
||||
#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
|
||||
#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000)
|
||||
#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
|
||||
#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
|
||||
#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
|
||||
#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
|
||||
#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
|
||||
#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
|
||||
#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000)
|
||||
#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000)
|
||||
#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000)
|
||||
|
||||
/* ICM2 - Application Subsystem */
|
||||
#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000)
|
||||
#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000)
|
||||
|
||||
/* ICM4 - High Speed Connection */
|
||||
#define SPEAR3XX_ICM4_BASE UL(0xE0000000)
|
||||
#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000)
|
||||
#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
|
||||
#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
|
||||
#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
|
||||
#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000)
|
||||
#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
|
||||
#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
|
||||
#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000)
|
||||
|
||||
/* ML1 - Multi Layer CPU Subsystem */
|
||||
#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
|
||||
#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000)
|
||||
#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000)
|
||||
#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
|
||||
#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
|
||||
|
||||
/* ICM3 - Basic Subsystem */
|
||||
#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
|
||||
#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
|
||||
#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
|
||||
#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
|
||||
#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
|
||||
#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
|
||||
#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000)
|
||||
#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
|
||||
#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
|
||||
#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
|
||||
#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
|
||||
#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
|
||||
#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
|
||||
#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
|
||||
#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
|
||||
#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
|
||||
|
||||
/* Debug uart for linux, will be used for debug and uncompress messages */
|
||||
#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
|
||||
|
||||
@ -1,54 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-spear3xx/include/mach/spear300.h
|
||||
*
|
||||
* SPEAr300 Machine specific definition
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_MACH_SPEAR300
|
||||
|
||||
#ifndef __MACH_SPEAR300_H
|
||||
#define __MACH_SPEAR300_H
|
||||
|
||||
/* Base address of various IPs */
|
||||
#define SPEAR300_TELECOM_BASE UL(0x50000000)
|
||||
|
||||
/* Interrupt registers offsets and masks */
|
||||
#define SPEAR300_INT_ENB_MASK_REG 0x54
|
||||
#define SPEAR300_INT_STS_MASK_REG 0x58
|
||||
#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
|
||||
#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
|
||||
#define SPEAR300_I2S_IRQ_MASK (1 << 2)
|
||||
#define SPEAR300_TDM_IRQ_MASK (1 << 3)
|
||||
#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
|
||||
#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
|
||||
#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
|
||||
#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
|
||||
#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
|
||||
|
||||
#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
|
||||
|
||||
#define SPEAR300_CLCD_BASE UL(0x60000000)
|
||||
#define SPEAR300_SDHCI_BASE UL(0x70000000)
|
||||
#define SPEAR300_NAND_0_BASE UL(0x80000000)
|
||||
#define SPEAR300_NAND_1_BASE UL(0x84000000)
|
||||
#define SPEAR300_NAND_2_BASE UL(0x88000000)
|
||||
#define SPEAR300_NAND_3_BASE UL(0x8c000000)
|
||||
#define SPEAR300_NOR_0_BASE UL(0x90000000)
|
||||
#define SPEAR300_NOR_1_BASE UL(0x91000000)
|
||||
#define SPEAR300_NOR_2_BASE UL(0x92000000)
|
||||
#define SPEAR300_NOR_3_BASE UL(0x93000000)
|
||||
#define SPEAR300_FSMC_BASE UL(0x94000000)
|
||||
#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
|
||||
#define SPEAR300_KEYBOARD_BASE UL(0xA0000000)
|
||||
#define SPEAR300_GPIO_BASE UL(0xA9000000)
|
||||
|
||||
#endif /* __MACH_SPEAR300_H */
|
||||
|
||||
#endif /* CONFIG_MACH_SPEAR300 */
|
||||
@ -1,58 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-spear3xx/include/mach/spear310.h
|
||||
*
|
||||
* SPEAr310 Machine specific definition
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_MACH_SPEAR310
|
||||
|
||||
#ifndef __MACH_SPEAR310_H
|
||||
#define __MACH_SPEAR310_H
|
||||
|
||||
#define SPEAR310_NAND_BASE UL(0x40000000)
|
||||
#define SPEAR310_FSMC_BASE UL(0x44000000)
|
||||
#define SPEAR310_UART1_BASE UL(0xB2000000)
|
||||
#define SPEAR310_UART2_BASE UL(0xB2080000)
|
||||
#define SPEAR310_UART3_BASE UL(0xB2100000)
|
||||
#define SPEAR310_UART4_BASE UL(0xB2180000)
|
||||
#define SPEAR310_UART5_BASE UL(0xB2200000)
|
||||
#define SPEAR310_HDLC_BASE UL(0xB2800000)
|
||||
#define SPEAR310_RS485_0_BASE UL(0xB3000000)
|
||||
#define SPEAR310_RS485_1_BASE UL(0xB3800000)
|
||||
#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
|
||||
|
||||
/* Interrupt registers offsets and masks */
|
||||
#define SPEAR310_INT_STS_MASK_REG 0x04
|
||||
#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
|
||||
#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
|
||||
#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
|
||||
#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
|
||||
#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
|
||||
#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
|
||||
#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
|
||||
#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
|
||||
#define SPEAR310_UART1_IRQ_MASK (1 << 8)
|
||||
#define SPEAR310_UART2_IRQ_MASK (1 << 9)
|
||||
#define SPEAR310_UART3_IRQ_MASK (1 << 10)
|
||||
#define SPEAR310_UART4_IRQ_MASK (1 << 11)
|
||||
#define SPEAR310_UART5_IRQ_MASK (1 << 12)
|
||||
#define SPEAR310_EMI_IRQ_MASK (1 << 13)
|
||||
#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
|
||||
#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
|
||||
#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
|
||||
|
||||
#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
|
||||
#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
|
||||
#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
|
||||
#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
|
||||
|
||||
#endif /* __MACH_SPEAR310_H */
|
||||
|
||||
#endif /* CONFIG_MACH_SPEAR310 */
|
||||
@ -1,67 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-spear3xx/include/mach/spear320.h
|
||||
*
|
||||
* SPEAr320 Machine specific definition
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_MACH_SPEAR320
|
||||
|
||||
#ifndef __MACH_SPEAR320_H
|
||||
#define __MACH_SPEAR320_H
|
||||
|
||||
#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
|
||||
#define SPEAR320_FSMC_BASE UL(0x4C000000)
|
||||
#define SPEAR320_NAND_BASE UL(0x50000000)
|
||||
#define SPEAR320_I2S_BASE UL(0x60000000)
|
||||
#define SPEAR320_SDHCI_BASE UL(0x70000000)
|
||||
#define SPEAR320_CLCD_BASE UL(0x90000000)
|
||||
#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
|
||||
#define SPEAR320_CAN0_BASE UL(0xA1000000)
|
||||
#define SPEAR320_CAN1_BASE UL(0xA2000000)
|
||||
#define SPEAR320_UART1_BASE UL(0xA3000000)
|
||||
#define SPEAR320_UART2_BASE UL(0xA4000000)
|
||||
#define SPEAR320_SSP0_BASE UL(0xA5000000)
|
||||
#define SPEAR320_SSP1_BASE UL(0xA6000000)
|
||||
#define SPEAR320_I2C_BASE UL(0xA7000000)
|
||||
#define SPEAR320_PWM_BASE UL(0xA8000000)
|
||||
#define SPEAR320_SMII0_BASE UL(0xAA000000)
|
||||
#define SPEAR320_SMII1_BASE UL(0xAB000000)
|
||||
#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
|
||||
|
||||
/* Interrupt registers offsets and masks */
|
||||
#define SPEAR320_INT_STS_MASK_REG 0x04
|
||||
#define SPEAR320_INT_CLR_MASK_REG 0x04
|
||||
#define SPEAR320_INT_ENB_MASK_REG 0x08
|
||||
#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
|
||||
#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
|
||||
#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
|
||||
#define SPEAR320_EMI_IRQ_MASK (1 << 7)
|
||||
#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
|
||||
#define SPEAR320_SPP_IRQ_MASK (1 << 9)
|
||||
#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
|
||||
#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
|
||||
#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
|
||||
#define SPEAR320_UART1_IRQ_MASK (1 << 13)
|
||||
#define SPEAR320_UART2_IRQ_MASK (1 << 14)
|
||||
#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
|
||||
#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
|
||||
#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
|
||||
#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
|
||||
#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
|
||||
#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
|
||||
#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
|
||||
|
||||
#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
|
||||
#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
|
||||
#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
|
||||
|
||||
#endif /* __MACH_SPEAR320_H */
|
||||
|
||||
#endif /* CONFIG_MACH_SPEAR320 */
|
||||
@ -3,372 +3,62 @@
|
||||
*
|
||||
* SPEAr300 machine source file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
* Copyright (C) 2009-2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/amba/pl061.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <asm/irq.h>
|
||||
#define pr_fmt(fmt) "SPEAr300: " fmt
|
||||
|
||||
#include <linux/amba/pl08x.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <plat/shirq.h>
|
||||
#include <mach/generic.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/spear.h>
|
||||
|
||||
/* pad multiplexing support */
|
||||
/* muxing registers */
|
||||
#define PAD_MUX_CONFIG_REG 0x00
|
||||
#define MODE_CONFIG_REG 0x04
|
||||
/* Base address of various IPs */
|
||||
#define SPEAR300_TELECOM_BASE UL(0x50000000)
|
||||
|
||||
/* modes */
|
||||
#define NAND_MODE (1 << 0)
|
||||
#define NOR_MODE (1 << 1)
|
||||
#define PHOTO_FRAME_MODE (1 << 2)
|
||||
#define LEND_IP_PHONE_MODE (1 << 3)
|
||||
#define HEND_IP_PHONE_MODE (1 << 4)
|
||||
#define LEND_WIFI_PHONE_MODE (1 << 5)
|
||||
#define HEND_WIFI_PHONE_MODE (1 << 6)
|
||||
#define ATA_PABX_WI2S_MODE (1 << 7)
|
||||
#define ATA_PABX_I2S_MODE (1 << 8)
|
||||
#define CAML_LCDW_MODE (1 << 9)
|
||||
#define CAMU_LCD_MODE (1 << 10)
|
||||
#define CAMU_WLCD_MODE (1 << 11)
|
||||
#define CAML_LCD_MODE (1 << 12)
|
||||
#define ALL_MODES 0x1FFF
|
||||
/* Interrupt registers offsets and masks */
|
||||
#define SPEAR300_INT_ENB_MASK_REG 0x54
|
||||
#define SPEAR300_INT_STS_MASK_REG 0x58
|
||||
#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
|
||||
#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
|
||||
#define SPEAR300_I2S_IRQ_MASK (1 << 2)
|
||||
#define SPEAR300_TDM_IRQ_MASK (1 << 3)
|
||||
#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
|
||||
#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
|
||||
#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
|
||||
#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
|
||||
#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
|
||||
|
||||
struct pmx_mode spear300_nand_mode = {
|
||||
.id = NAND_MODE,
|
||||
.name = "nand mode",
|
||||
.mask = 0x00,
|
||||
};
|
||||
#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
|
||||
|
||||
struct pmx_mode spear300_nor_mode = {
|
||||
.id = NOR_MODE,
|
||||
.name = "nor mode",
|
||||
.mask = 0x01,
|
||||
};
|
||||
#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
|
||||
|
||||
struct pmx_mode spear300_photo_frame_mode = {
|
||||
.id = PHOTO_FRAME_MODE,
|
||||
.name = "photo frame mode",
|
||||
.mask = 0x02,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_lend_ip_phone_mode = {
|
||||
.id = LEND_IP_PHONE_MODE,
|
||||
.name = "lend ip phone mode",
|
||||
.mask = 0x03,
|
||||
};
|
||||
/* SPEAr300 Virtual irq definitions */
|
||||
/* IRQs sharing IRQ_GEN_RAS_1 */
|
||||
#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
|
||||
#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
|
||||
#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
|
||||
#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
|
||||
#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
|
||||
#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
|
||||
#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
|
||||
#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
|
||||
#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
|
||||
|
||||
struct pmx_mode spear300_hend_ip_phone_mode = {
|
||||
.id = HEND_IP_PHONE_MODE,
|
||||
.name = "hend ip phone mode",
|
||||
.mask = 0x04,
|
||||
};
|
||||
/* IRQs sharing IRQ_GEN_RAS_3 */
|
||||
#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
|
||||
|
||||
struct pmx_mode spear300_lend_wifi_phone_mode = {
|
||||
.id = LEND_WIFI_PHONE_MODE,
|
||||
.name = "lend wifi phone mode",
|
||||
.mask = 0x05,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_hend_wifi_phone_mode = {
|
||||
.id = HEND_WIFI_PHONE_MODE,
|
||||
.name = "hend wifi phone mode",
|
||||
.mask = 0x06,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_ata_pabx_wi2s_mode = {
|
||||
.id = ATA_PABX_WI2S_MODE,
|
||||
.name = "ata pabx wi2s mode",
|
||||
.mask = 0x07,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_ata_pabx_i2s_mode = {
|
||||
.id = ATA_PABX_I2S_MODE,
|
||||
.name = "ata pabx i2s mode",
|
||||
.mask = 0x08,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_caml_lcdw_mode = {
|
||||
.id = CAML_LCDW_MODE,
|
||||
.name = "caml lcdw mode",
|
||||
.mask = 0x0C,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_camu_lcd_mode = {
|
||||
.id = CAMU_LCD_MODE,
|
||||
.name = "camu lcd mode",
|
||||
.mask = 0x0D,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_camu_wlcd_mode = {
|
||||
.id = CAMU_WLCD_MODE,
|
||||
.name = "camu wlcd mode",
|
||||
.mask = 0x0E,
|
||||
};
|
||||
|
||||
struct pmx_mode spear300_caml_lcd_mode = {
|
||||
.id = CAML_LCD_MODE,
|
||||
.name = "caml lcd mode",
|
||||
.mask = 0x0F,
|
||||
};
|
||||
|
||||
/* devices */
|
||||
static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
|
||||
{
|
||||
.ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
|
||||
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
|
||||
.mask = PMX_FIRDA_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_fsmc_2_chips = {
|
||||
.name = "fsmc_2_chips",
|
||||
.modes = pmx_fsmc_2_chips_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
|
||||
{
|
||||
.ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
|
||||
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
|
||||
.mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_fsmc_4_chips = {
|
||||
.name = "fsmc_4_chips",
|
||||
.modes = pmx_fsmc_4_chips_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_keyboard_modes[] = {
|
||||
{
|
||||
.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
|
||||
LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
|
||||
CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
|
||||
CAML_LCD_MODE,
|
||||
.mask = 0x0,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_keyboard = {
|
||||
.name = "keyboard",
|
||||
.modes = pmx_keyboard_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_keyboard_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_clcd_modes[] = {
|
||||
{
|
||||
.ids = PHOTO_FRAME_MODE,
|
||||
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
|
||||
}, {
|
||||
.ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
|
||||
CAMU_LCD_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_clcd = {
|
||||
.name = "clcd",
|
||||
.modes = pmx_clcd_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_clcd_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
|
||||
{
|
||||
.ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
}, {
|
||||
.ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
|
||||
.mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
|
||||
}, {
|
||||
.ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
|
||||
.mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
|
||||
}, {
|
||||
.ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
|
||||
.mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
|
||||
}, {
|
||||
.ids = ATA_PABX_WI2S_MODE,
|
||||
.mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
|
||||
| PMX_UART0_MODEM_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_gpio = {
|
||||
.name = "telecom_gpio",
|
||||
.modes = pmx_telecom_gpio_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
|
||||
{
|
||||
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
|
||||
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
|
||||
| HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
|
||||
| ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
|
||||
| CAMU_WLCD_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_tdm = {
|
||||
.name = "telecom_tdm",
|
||||
.modes = pmx_telecom_tdm_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
|
||||
{
|
||||
.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
|
||||
LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
|
||||
| ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
|
||||
CAML_LCDW_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
|
||||
.name = "telecom_spi_cs_i2c_clk",
|
||||
.modes = pmx_telecom_spi_cs_i2c_clk_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
|
||||
{
|
||||
.ids = CAML_LCDW_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
}, {
|
||||
.ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
|
||||
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_camera = {
|
||||
.name = "telecom_camera",
|
||||
.modes = pmx_telecom_camera_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
|
||||
{
|
||||
.ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
|
||||
| CAMU_WLCD_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_TIMER_1_2_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_dac = {
|
||||
.name = "telecom_dac",
|
||||
.modes = pmx_telecom_dac_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
|
||||
{
|
||||
.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
|
||||
| LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
|
||||
ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
|
||||
| CAMU_WLCD_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_UART0_MODEM_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_i2s = {
|
||||
.name = "telecom_i2s",
|
||||
.modes = pmx_telecom_i2s_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
|
||||
{
|
||||
.ids = NAND_MODE | NOR_MODE,
|
||||
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
|
||||
PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_boot_pins = {
|
||||
.name = "telecom_boot_pins",
|
||||
.modes = pmx_telecom_boot_pins_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
|
||||
{
|
||||
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
|
||||
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
|
||||
HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
|
||||
CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
|
||||
ATA_PABX_I2S_MODE,
|
||||
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
|
||||
PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
|
||||
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
|
||||
.name = "telecom_sdhci_4bit",
|
||||
.modes = pmx_telecom_sdhci_4bit_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
|
||||
{
|
||||
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
|
||||
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
|
||||
HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
|
||||
CAMU_WLCD_MODE | CAML_LCD_MODE,
|
||||
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
|
||||
PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
|
||||
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
|
||||
.name = "telecom_sdhci_8bit",
|
||||
.modes = pmx_telecom_sdhci_8bit_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_gpio1_modes[] = {
|
||||
{
|
||||
.ids = PHOTO_FRAME_MODE,
|
||||
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
|
||||
PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear300_pmx_gpio1 = {
|
||||
.name = "arm gpio1",
|
||||
.modes = pmx_gpio1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_gpio1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
/* pmx driver structure */
|
||||
static struct pmx_driver pmx_driver = {
|
||||
.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
|
||||
.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
|
||||
};
|
||||
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
|
||||
#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
|
||||
|
||||
/* spear3xx shared irq */
|
||||
static struct shirq_dev_config shirq_ras1_config[] = {
|
||||
@ -423,45 +113,238 @@ static struct spear_shirq shirq_ras1 = {
|
||||
},
|
||||
};
|
||||
|
||||
/* Add spear300 specific devices here */
|
||||
/* arm gpio1 device registration */
|
||||
static struct pl061_platform_data gpio1_plat_data = {
|
||||
.gpio_base = 8,
|
||||
.irq_base = SPEAR300_GPIO1_INT_BASE,
|
||||
/* DMAC platform data's slave info */
|
||||
struct pl08x_channel_data spear300_dma_info[] = {
|
||||
{
|
||||
.bus_id = "uart0_rx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart0_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp0_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp0_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "irda",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "adc",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "to_jpeg",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "from_jpeg",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras0_rx",
|
||||
.min_signal = 0,
|
||||
.max_signal = 0,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras0_tx",
|
||||
.min_signal = 1,
|
||||
.max_signal = 1,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras1_rx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras1_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras2_rx",
|
||||
.min_signal = 4,
|
||||
.max_signal = 4,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras2_tx",
|
||||
.min_signal = 5,
|
||||
.max_signal = 5,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras3_rx",
|
||||
.min_signal = 6,
|
||||
.max_signal = 6,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras3_tx",
|
||||
.min_signal = 7,
|
||||
.max_signal = 7,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras4_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras4_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras5_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras5_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras6_rx",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras6_tx",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras7_rx",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras7_tx",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
},
|
||||
};
|
||||
|
||||
AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE,
|
||||
{SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data);
|
||||
/* Add SPEAr300 auxdata to pass platform data */
|
||||
static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
|
||||
&pl022_plat_data),
|
||||
OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
|
||||
&pl080_plat_data),
|
||||
{}
|
||||
};
|
||||
|
||||
/* spear300 routines */
|
||||
void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
|
||||
u8 pmx_dev_count)
|
||||
static void __init spear300_dt_init(void)
|
||||
{
|
||||
int ret = 0;
|
||||
int ret;
|
||||
|
||||
/* call spear3xx family common init function */
|
||||
spear3xx_init();
|
||||
pl080_plat_data.slave_channels = spear300_dma_info;
|
||||
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
spear300_auxdata_lookup, NULL);
|
||||
|
||||
/* shared irq registration */
|
||||
shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
|
||||
if (shirq_ras1.regs.base) {
|
||||
ret = spear_shirq_register(&shirq_ras1);
|
||||
if (ret)
|
||||
printk(KERN_ERR "Error registering Shared IRQ\n");
|
||||
}
|
||||
|
||||
/* pmx initialization */
|
||||
pmx_driver.mode = pmx_mode;
|
||||
pmx_driver.devs = pmx_devs;
|
||||
pmx_driver.devs_count = pmx_dev_count;
|
||||
|
||||
pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
|
||||
if (pmx_driver.base) {
|
||||
ret = pmx_register(&pmx_driver);
|
||||
if (ret)
|
||||
printk(KERN_ERR "padmux: registration failed. err no"
|
||||
": %d\n", ret);
|
||||
/* Free Mapping, device selection already done */
|
||||
iounmap(pmx_driver.base);
|
||||
pr_err("Error registering Shared IRQ\n");
|
||||
}
|
||||
}
|
||||
|
||||
static const char * const spear300_dt_board_compat[] = {
|
||||
"st,spear300",
|
||||
"st,spear300-evb",
|
||||
NULL,
|
||||
};
|
||||
|
||||
static void __init spear300_map_io(void)
|
||||
{
|
||||
spear3xx_map_io();
|
||||
}
|
||||
|
||||
DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
|
||||
.map_io = spear300_map_io,
|
||||
.init_irq = spear3xx_dt_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &spear3xx_timer,
|
||||
.init_machine = spear300_dt_init,
|
||||
.restart = spear_restart,
|
||||
.dt_compat = spear300_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
||||
@ -1,75 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-spear3xx/spear300_evb.c
|
||||
*
|
||||
* SPEAr300 evaluation board source file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <mach/generic.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
/* padmux devices to enable */
|
||||
static struct pmx_dev *pmx_devs[] = {
|
||||
/* spear3xx specific devices */
|
||||
&spear3xx_pmx_i2c,
|
||||
&spear3xx_pmx_ssp_cs,
|
||||
&spear3xx_pmx_ssp,
|
||||
&spear3xx_pmx_mii,
|
||||
&spear3xx_pmx_uart0,
|
||||
|
||||
/* spear300 specific devices */
|
||||
&spear300_pmx_fsmc_2_chips,
|
||||
&spear300_pmx_clcd,
|
||||
&spear300_pmx_telecom_sdhci_4bit,
|
||||
&spear300_pmx_gpio1,
|
||||
};
|
||||
|
||||
static struct amba_device *amba_devs[] __initdata = {
|
||||
/* spear3xx specific devices */
|
||||
&spear3xx_gpio_device,
|
||||
&spear3xx_uart_device,
|
||||
|
||||
/* spear300 specific devices */
|
||||
&spear300_gpio1_device,
|
||||
};
|
||||
|
||||
static struct platform_device *plat_devs[] __initdata = {
|
||||
/* spear3xx specific devices */
|
||||
|
||||
/* spear300 specific devices */
|
||||
};
|
||||
|
||||
static void __init spear300_evb_init(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
/* call spear300 machine init function */
|
||||
spear300_init(&spear300_photo_frame_mode, pmx_devs,
|
||||
ARRAY_SIZE(pmx_devs));
|
||||
|
||||
/* Add Platform Devices */
|
||||
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
|
||||
|
||||
/* Add Amba Devices */
|
||||
for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
|
||||
amba_device_register(amba_devs[i], &iomem_resource);
|
||||
}
|
||||
|
||||
MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = spear3xx_map_io,
|
||||
.init_irq = spear3xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &spear3xx_timer,
|
||||
.init_machine = spear300_evb_init,
|
||||
.restart = spear_restart,
|
||||
MACHINE_END
|
||||
@ -3,141 +3,84 @@
|
||||
*
|
||||
* SPEAr310 machine source file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
* Copyright (C) 2009-2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/ptrace.h>
|
||||
#include <asm/irq.h>
|
||||
#define pr_fmt(fmt) "SPEAr310: " fmt
|
||||
|
||||
#include <linux/amba/pl08x.h>
|
||||
#include <linux/amba/serial.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <plat/shirq.h>
|
||||
#include <mach/generic.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/spear.h>
|
||||
|
||||
/* pad multiplexing support */
|
||||
/* muxing registers */
|
||||
#define PAD_MUX_CONFIG_REG 0x08
|
||||
#define SPEAR310_UART1_BASE UL(0xB2000000)
|
||||
#define SPEAR310_UART2_BASE UL(0xB2080000)
|
||||
#define SPEAR310_UART3_BASE UL(0xB2100000)
|
||||
#define SPEAR310_UART4_BASE UL(0xB2180000)
|
||||
#define SPEAR310_UART5_BASE UL(0xB2200000)
|
||||
#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
|
||||
|
||||
/* devices */
|
||||
static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
/* Interrupt registers offsets and masks */
|
||||
#define SPEAR310_INT_STS_MASK_REG 0x04
|
||||
#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
|
||||
#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
|
||||
#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
|
||||
#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
|
||||
#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
|
||||
#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
|
||||
#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
|
||||
#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
|
||||
#define SPEAR310_UART1_IRQ_MASK (1 << 8)
|
||||
#define SPEAR310_UART2_IRQ_MASK (1 << 9)
|
||||
#define SPEAR310_UART3_IRQ_MASK (1 << 10)
|
||||
#define SPEAR310_UART4_IRQ_MASK (1 << 11)
|
||||
#define SPEAR310_UART5_IRQ_MASK (1 << 12)
|
||||
#define SPEAR310_EMI_IRQ_MASK (1 << 13)
|
||||
#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
|
||||
#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
|
||||
#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
|
||||
|
||||
struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
|
||||
.name = "emi_cs_0_1_4_5",
|
||||
.modes = pmx_emi_cs_0_1_4_5_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
|
||||
#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
|
||||
#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
|
||||
#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
|
||||
|
||||
static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_TIMER_1_2_MASK,
|
||||
},
|
||||
};
|
||||
/* SPEAr310 Virtual irq definitions */
|
||||
/* IRQs sharing IRQ_GEN_RAS_1 */
|
||||
#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
|
||||
#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
|
||||
#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
|
||||
#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
|
||||
#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
|
||||
#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
|
||||
#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
|
||||
#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
|
||||
|
||||
struct pmx_dev spear310_pmx_emi_cs_2_3 = {
|
||||
.name = "emi_cs_2_3",
|
||||
.modes = pmx_emi_cs_2_3_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
/* IRQs sharing IRQ_GEN_RAS_2 */
|
||||
#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
|
||||
#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
|
||||
#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
|
||||
#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
|
||||
#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
|
||||
|
||||
static struct pmx_dev_mode pmx_uart1_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_FIRDA_MASK,
|
||||
},
|
||||
};
|
||||
/* IRQs sharing IRQ_GEN_RAS_3 */
|
||||
#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
|
||||
#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
|
||||
|
||||
struct pmx_dev spear310_pmx_uart1 = {
|
||||
.name = "uart1",
|
||||
.modes = pmx_uart1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
|
||||
#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
|
||||
#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
|
||||
#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
|
||||
|
||||
static struct pmx_dev_mode pmx_uart2_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_TIMER_1_2_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear310_pmx_uart2 = {
|
||||
.name = "uart2",
|
||||
.modes = pmx_uart2_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart2_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_UART0_MODEM_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear310_pmx_uart3_4_5 = {
|
||||
.name = "uart3_4_5",
|
||||
.modes = pmx_uart3_4_5_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_fsmc_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_SSP_CS_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear310_pmx_fsmc = {
|
||||
.name = "fsmc",
|
||||
.modes = pmx_fsmc_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear310_pmx_rs485_0_1 = {
|
||||
.name = "rs485_0_1",
|
||||
.modes = pmx_rs485_0_1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_tdm0_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear310_pmx_tdm0 = {
|
||||
.name = "tdm0",
|
||||
.modes = pmx_tdm0_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_tdm0_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
/* pmx driver structure */
|
||||
static struct pmx_driver pmx_driver = {
|
||||
.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
|
||||
};
|
||||
|
||||
/* spear3xx shared irq */
|
||||
static struct shirq_dev_config shirq_ras1_config[] = {
|
||||
@ -255,17 +198,247 @@ static struct spear_shirq shirq_intrcomm_ras = {
|
||||
},
|
||||
};
|
||||
|
||||
/* Add spear310 specific devices here */
|
||||
/* DMAC platform data's slave info */
|
||||
struct pl08x_channel_data spear310_dma_info[] = {
|
||||
{
|
||||
.bus_id = "uart0_rx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart0_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp0_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp0_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "irda",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "adc",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "to_jpeg",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "from_jpeg",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart1_rx",
|
||||
.min_signal = 0,
|
||||
.max_signal = 0,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart1_tx",
|
||||
.min_signal = 1,
|
||||
.max_signal = 1,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart2_rx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart2_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart3_rx",
|
||||
.min_signal = 4,
|
||||
.max_signal = 4,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart3_tx",
|
||||
.min_signal = 5,
|
||||
.max_signal = 5,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart4_rx",
|
||||
.min_signal = 6,
|
||||
.max_signal = 6,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart4_tx",
|
||||
.min_signal = 7,
|
||||
.max_signal = 7,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart5_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart5_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras5_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras5_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras6_rx",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras6_tx",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras7_rx",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras7_tx",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
},
|
||||
};
|
||||
|
||||
/* spear310 routines */
|
||||
void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
|
||||
u8 pmx_dev_count)
|
||||
/* uart devices plat data */
|
||||
static struct amba_pl011_data spear310_uart_data[] = {
|
||||
{
|
||||
.dma_filter = pl08x_filter_id,
|
||||
.dma_tx_param = "uart1_tx",
|
||||
.dma_rx_param = "uart1_rx",
|
||||
}, {
|
||||
.dma_filter = pl08x_filter_id,
|
||||
.dma_tx_param = "uart2_tx",
|
||||
.dma_rx_param = "uart2_rx",
|
||||
}, {
|
||||
.dma_filter = pl08x_filter_id,
|
||||
.dma_tx_param = "uart3_tx",
|
||||
.dma_rx_param = "uart3_rx",
|
||||
}, {
|
||||
.dma_filter = pl08x_filter_id,
|
||||
.dma_tx_param = "uart4_tx",
|
||||
.dma_rx_param = "uart4_rx",
|
||||
}, {
|
||||
.dma_filter = pl08x_filter_id,
|
||||
.dma_tx_param = "uart5_tx",
|
||||
.dma_rx_param = "uart5_rx",
|
||||
},
|
||||
};
|
||||
|
||||
/* Add SPEAr310 auxdata to pass platform data */
|
||||
static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
|
||||
&pl022_plat_data),
|
||||
OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
|
||||
&pl080_plat_data),
|
||||
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
|
||||
&spear310_uart_data[0]),
|
||||
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
|
||||
&spear310_uart_data[1]),
|
||||
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
|
||||
&spear310_uart_data[2]),
|
||||
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
|
||||
&spear310_uart_data[3]),
|
||||
OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
|
||||
&spear310_uart_data[4]),
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init spear310_dt_init(void)
|
||||
{
|
||||
void __iomem *base;
|
||||
int ret = 0;
|
||||
int ret;
|
||||
|
||||
/* call spear3xx family common init function */
|
||||
spear3xx_init();
|
||||
pl080_plat_data.slave_channels = spear310_dma_info;
|
||||
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
spear310_auxdata_lookup, NULL);
|
||||
|
||||
/* shared irq registration */
|
||||
base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
|
||||
@ -274,35 +447,45 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
|
||||
shirq_ras1.regs.base = base;
|
||||
ret = spear_shirq_register(&shirq_ras1);
|
||||
if (ret)
|
||||
printk(KERN_ERR "Error registering Shared IRQ 1\n");
|
||||
pr_err("Error registering Shared IRQ 1\n");
|
||||
|
||||
/* shirq 2 */
|
||||
shirq_ras2.regs.base = base;
|
||||
ret = spear_shirq_register(&shirq_ras2);
|
||||
if (ret)
|
||||
printk(KERN_ERR "Error registering Shared IRQ 2\n");
|
||||
pr_err("Error registering Shared IRQ 2\n");
|
||||
|
||||
/* shirq 3 */
|
||||
shirq_ras3.regs.base = base;
|
||||
ret = spear_shirq_register(&shirq_ras3);
|
||||
if (ret)
|
||||
printk(KERN_ERR "Error registering Shared IRQ 3\n");
|
||||
pr_err("Error registering Shared IRQ 3\n");
|
||||
|
||||
/* shirq 4 */
|
||||
shirq_intrcomm_ras.regs.base = base;
|
||||
ret = spear_shirq_register(&shirq_intrcomm_ras);
|
||||
if (ret)
|
||||
printk(KERN_ERR "Error registering Shared IRQ 4\n");
|
||||
pr_err("Error registering Shared IRQ 4\n");
|
||||
}
|
||||
|
||||
/* pmx initialization */
|
||||
pmx_driver.base = base;
|
||||
pmx_driver.mode = pmx_mode;
|
||||
pmx_driver.devs = pmx_devs;
|
||||
pmx_driver.devs_count = pmx_dev_count;
|
||||
|
||||
ret = pmx_register(&pmx_driver);
|
||||
if (ret)
|
||||
printk(KERN_ERR "padmux: registration failed. err no: %d\n",
|
||||
ret);
|
||||
}
|
||||
|
||||
static const char * const spear310_dt_board_compat[] = {
|
||||
"st,spear310",
|
||||
"st,spear310-evb",
|
||||
NULL,
|
||||
};
|
||||
|
||||
static void __init spear310_map_io(void)
|
||||
{
|
||||
spear3xx_map_io();
|
||||
}
|
||||
|
||||
DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
|
||||
.map_io = spear310_map_io,
|
||||
.init_irq = spear3xx_dt_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &spear3xx_timer,
|
||||
.init_machine = spear310_dt_init,
|
||||
.restart = spear_restart,
|
||||
.dt_compat = spear310_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
||||
@ -1,81 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-spear3xx/spear310_evb.c
|
||||
*
|
||||
* SPEAr310 evaluation board source file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <mach/generic.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
/* padmux devices to enable */
|
||||
static struct pmx_dev *pmx_devs[] = {
|
||||
/* spear3xx specific devices */
|
||||
&spear3xx_pmx_i2c,
|
||||
&spear3xx_pmx_ssp,
|
||||
&spear3xx_pmx_gpio_pin0,
|
||||
&spear3xx_pmx_gpio_pin1,
|
||||
&spear3xx_pmx_gpio_pin2,
|
||||
&spear3xx_pmx_gpio_pin3,
|
||||
&spear3xx_pmx_gpio_pin4,
|
||||
&spear3xx_pmx_gpio_pin5,
|
||||
&spear3xx_pmx_uart0,
|
||||
|
||||
/* spear310 specific devices */
|
||||
&spear310_pmx_emi_cs_0_1_4_5,
|
||||
&spear310_pmx_emi_cs_2_3,
|
||||
&spear310_pmx_uart1,
|
||||
&spear310_pmx_uart2,
|
||||
&spear310_pmx_uart3_4_5,
|
||||
&spear310_pmx_fsmc,
|
||||
&spear310_pmx_rs485_0_1,
|
||||
&spear310_pmx_tdm0,
|
||||
};
|
||||
|
||||
static struct amba_device *amba_devs[] __initdata = {
|
||||
/* spear3xx specific devices */
|
||||
&spear3xx_gpio_device,
|
||||
&spear3xx_uart_device,
|
||||
|
||||
/* spear310 specific devices */
|
||||
};
|
||||
|
||||
static struct platform_device *plat_devs[] __initdata = {
|
||||
/* spear3xx specific devices */
|
||||
|
||||
/* spear310 specific devices */
|
||||
};
|
||||
|
||||
static void __init spear310_evb_init(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
/* call spear310 machine init function */
|
||||
spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
|
||||
|
||||
/* Add Platform Devices */
|
||||
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
|
||||
|
||||
/* Add Amba Devices */
|
||||
for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
|
||||
amba_device_register(amba_devs[i], &iomem_resource);
|
||||
}
|
||||
|
||||
MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = spear3xx_map_io,
|
||||
.init_irq = spear3xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &spear3xx_timer,
|
||||
.init_machine = spear310_evb_init,
|
||||
.restart = spear_restart,
|
||||
MACHINE_END
|
||||
@ -3,387 +3,84 @@
|
||||
*
|
||||
* SPEAr320 machine source file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
* Copyright (C) 2009-2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/ptrace.h>
|
||||
#include <asm/irq.h>
|
||||
#define pr_fmt(fmt) "SPEAr320: " fmt
|
||||
|
||||
#include <linux/amba/pl022.h>
|
||||
#include <linux/amba/pl08x.h>
|
||||
#include <linux/amba/serial.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <plat/shirq.h>
|
||||
#include <mach/generic.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/spear.h>
|
||||
|
||||
/* pad multiplexing support */
|
||||
/* muxing registers */
|
||||
#define PAD_MUX_CONFIG_REG 0x0C
|
||||
#define MODE_CONFIG_REG 0x10
|
||||
#define SPEAR320_UART1_BASE UL(0xA3000000)
|
||||
#define SPEAR320_UART2_BASE UL(0xA4000000)
|
||||
#define SPEAR320_SSP0_BASE UL(0xA5000000)
|
||||
#define SPEAR320_SSP1_BASE UL(0xA6000000)
|
||||
|
||||
/* modes */
|
||||
#define AUTO_NET_SMII_MODE (1 << 0)
|
||||
#define AUTO_NET_MII_MODE (1 << 1)
|
||||
#define AUTO_EXP_MODE (1 << 2)
|
||||
#define SMALL_PRINTERS_MODE (1 << 3)
|
||||
#define ALL_MODES 0xF
|
||||
/* Interrupt registers offsets and masks */
|
||||
#define SPEAR320_INT_STS_MASK_REG 0x04
|
||||
#define SPEAR320_INT_CLR_MASK_REG 0x04
|
||||
#define SPEAR320_INT_ENB_MASK_REG 0x08
|
||||
#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
|
||||
#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
|
||||
#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
|
||||
#define SPEAR320_EMI_IRQ_MASK (1 << 7)
|
||||
#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
|
||||
#define SPEAR320_SPP_IRQ_MASK (1 << 9)
|
||||
#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
|
||||
#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
|
||||
#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
|
||||
#define SPEAR320_UART1_IRQ_MASK (1 << 13)
|
||||
#define SPEAR320_UART2_IRQ_MASK (1 << 14)
|
||||
#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
|
||||
#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
|
||||
#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
|
||||
#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
|
||||
#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
|
||||
#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
|
||||
#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
|
||||
|
||||
struct pmx_mode spear320_auto_net_smii_mode = {
|
||||
.id = AUTO_NET_SMII_MODE,
|
||||
.name = "Automation Networking SMII Mode",
|
||||
.mask = 0x00,
|
||||
};
|
||||
#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
|
||||
#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
|
||||
#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
|
||||
|
||||
struct pmx_mode spear320_auto_net_mii_mode = {
|
||||
.id = AUTO_NET_MII_MODE,
|
||||
.name = "Automation Networking MII Mode",
|
||||
.mask = 0x01,
|
||||
};
|
||||
/* SPEAr320 Virtual irq definitions */
|
||||
/* IRQs sharing IRQ_GEN_RAS_1 */
|
||||
#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
|
||||
#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
|
||||
#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
|
||||
|
||||
struct pmx_mode spear320_auto_exp_mode = {
|
||||
.id = AUTO_EXP_MODE,
|
||||
.name = "Automation Expanded Mode",
|
||||
.mask = 0x02,
|
||||
};
|
||||
/* IRQs sharing IRQ_GEN_RAS_2 */
|
||||
#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
|
||||
|
||||
struct pmx_mode spear320_small_printers_mode = {
|
||||
.id = SMALL_PRINTERS_MODE,
|
||||
.name = "Small Printers Mode",
|
||||
.mask = 0x03,
|
||||
};
|
||||
/* IRQs sharing IRQ_GEN_RAS_3 */
|
||||
#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
|
||||
#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
|
||||
#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
|
||||
|
||||
/* devices */
|
||||
static struct pmx_dev_mode pmx_clcd_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE,
|
||||
.mask = 0x0,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_clcd = {
|
||||
.name = "clcd",
|
||||
.modes = pmx_clcd_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_clcd_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_emi_modes[] = {
|
||||
{
|
||||
.ids = AUTO_EXP_MODE,
|
||||
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_emi = {
|
||||
.name = "emi",
|
||||
.modes = pmx_emi_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_emi_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_fsmc_modes[] = {
|
||||
{
|
||||
.ids = ALL_MODES,
|
||||
.mask = 0x0,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_fsmc = {
|
||||
.name = "fsmc",
|
||||
.modes = pmx_fsmc_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_spp_modes[] = {
|
||||
{
|
||||
.ids = SMALL_PRINTERS_MODE,
|
||||
.mask = 0x0,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_spp = {
|
||||
.name = "spp",
|
||||
.modes = pmx_spp_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_spp_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_sdhci_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
|
||||
SMALL_PRINTERS_MODE,
|
||||
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_sdhci = {
|
||||
.name = "sdhci",
|
||||
.modes = pmx_sdhci_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_sdhci_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_i2s_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
|
||||
.mask = PMX_UART0_MODEM_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_i2s = {
|
||||
.name = "i2s",
|
||||
.modes = pmx_i2s_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_i2s_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_uart1_modes[] = {
|
||||
{
|
||||
.ids = ALL_MODES,
|
||||
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_uart1 = {
|
||||
.name = "uart1",
|
||||
.modes = pmx_uart1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
|
||||
{
|
||||
.ids = AUTO_EXP_MODE,
|
||||
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
|
||||
PMX_SSP_CS_MASK,
|
||||
}, {
|
||||
.ids = SMALL_PRINTERS_MODE,
|
||||
.mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
|
||||
PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_uart1_modem = {
|
||||
.name = "uart1_modem",
|
||||
.modes = pmx_uart1_modem_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_uart2_modes[] = {
|
||||
{
|
||||
.ids = ALL_MODES,
|
||||
.mask = PMX_FIRDA_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_uart2 = {
|
||||
.name = "uart2",
|
||||
.modes = pmx_uart2_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart2_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_touchscreen_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE,
|
||||
.mask = PMX_SSP_CS_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_touchscreen = {
|
||||
.name = "touchscreen",
|
||||
.modes = pmx_touchscreen_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_can_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
|
||||
.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
|
||||
PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_can = {
|
||||
.name = "can",
|
||||
.modes = pmx_can_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_can_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
|
||||
.mask = PMX_SSP_CS_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_sdhci_led = {
|
||||
.name = "sdhci_led",
|
||||
.modes = pmx_sdhci_led_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_pwm0_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
|
||||
.mask = PMX_UART0_MODEM_MASK,
|
||||
}, {
|
||||
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_pwm0 = {
|
||||
.name = "pwm0",
|
||||
.modes = pmx_pwm0_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_pwm0_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_pwm1_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
|
||||
.mask = PMX_UART0_MODEM_MASK,
|
||||
}, {
|
||||
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_pwm1 = {
|
||||
.name = "pwm1",
|
||||
.modes = pmx_pwm1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_pwm1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_pwm2_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
|
||||
.mask = PMX_SSP_CS_MASK,
|
||||
}, {
|
||||
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_pwm2 = {
|
||||
.name = "pwm2",
|
||||
.modes = pmx_pwm2_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_pwm2_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_pwm3_modes[] = {
|
||||
{
|
||||
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_pwm3 = {
|
||||
.name = "pwm3",
|
||||
.modes = pmx_pwm3_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_pwm3_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_ssp1_modes[] = {
|
||||
{
|
||||
.ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_ssp1 = {
|
||||
.name = "ssp1",
|
||||
.modes = pmx_ssp1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_ssp1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_ssp2_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_ssp2 = {
|
||||
.name = "ssp2",
|
||||
.modes = pmx_ssp2_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_ssp2_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_mii1_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_MII_MODE,
|
||||
.mask = 0x0,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_mii1 = {
|
||||
.name = "mii1",
|
||||
.modes = pmx_mii1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_mii1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_smii0_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_smii0 = {
|
||||
.name = "smii0",
|
||||
.modes = pmx_smii0_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_smii0_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_smii1_modes[] = {
|
||||
{
|
||||
.ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_smii1 = {
|
||||
.name = "smii1",
|
||||
.modes = pmx_smii1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_smii1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_i2c1_modes[] = {
|
||||
{
|
||||
.ids = AUTO_EXP_MODE,
|
||||
.mask = 0x0,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear320_pmx_i2c1 = {
|
||||
.name = "i2c1",
|
||||
.modes = pmx_i2c1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_i2c1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
/* pmx driver structure */
|
||||
static struct pmx_driver pmx_driver = {
|
||||
.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
|
||||
.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
|
||||
};
|
||||
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
|
||||
#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
|
||||
#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
|
||||
#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
|
||||
#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
|
||||
#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
|
||||
#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
|
||||
#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
|
||||
#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
|
||||
#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
|
||||
#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
|
||||
#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
|
||||
|
||||
/* spear3xx shared irq */
|
||||
static struct shirq_dev_config shirq_ras1_config[] = {
|
||||
@ -509,17 +206,250 @@ static struct spear_shirq shirq_intrcomm_ras = {
|
||||
},
|
||||
};
|
||||
|
||||
/* Add spear320 specific devices here */
|
||||
/* DMAC platform data's slave info */
|
||||
struct pl08x_channel_data spear320_dma_info[] = {
|
||||
{
|
||||
.bus_id = "uart0_rx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart0_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp0_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp0_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c0_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c0_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "irda",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "adc",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "to_jpeg",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "from_jpeg",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp1_rx",
|
||||
.min_signal = 0,
|
||||
.max_signal = 0,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ssp1_tx",
|
||||
.min_signal = 1,
|
||||
.max_signal = 1,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ssp2_rx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ssp2_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "uart1_rx",
|
||||
.min_signal = 4,
|
||||
.max_signal = 4,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "uart1_tx",
|
||||
.min_signal = 5,
|
||||
.max_signal = 5,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "uart2_rx",
|
||||
.min_signal = 6,
|
||||
.max_signal = 6,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "uart2_tx",
|
||||
.min_signal = 7,
|
||||
.max_signal = 7,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2c1_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2c1_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2c2_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2c2_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2s_rx",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "i2s_tx",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "rs485_rx",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "rs485_tx",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
},
|
||||
};
|
||||
|
||||
/* spear320 routines */
|
||||
void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
|
||||
u8 pmx_dev_count)
|
||||
static struct pl022_ssp_controller spear320_ssp_data[] = {
|
||||
{
|
||||
.bus_id = 1,
|
||||
.enable_dma = 1,
|
||||
.dma_filter = pl08x_filter_id,
|
||||
.dma_tx_param = "ssp1_tx",
|
||||
.dma_rx_param = "ssp1_rx",
|
||||
.num_chipselect = 2,
|
||||
}, {
|
||||
.bus_id = 2,
|
||||
.enable_dma = 1,
|
||||
.dma_filter = pl08x_filter_id,
|
||||
.dma_tx_param = "ssp2_tx",
|
||||
.dma_rx_param = "ssp2_rx",
|
||||
.num_chipselect = 2,
|
||||
}
|
||||
};
|
||||
|
||||
static struct amba_pl011_data spear320_uart_data[] = {
|
||||
{
|
||||
.dma_filter = pl08x_filter_id,
|
||||
.dma_tx_param = "uart1_tx",
|
||||
.dma_rx_param = "uart1_rx",
|
||||
}, {
|
||||
.dma_filter = pl08x_filter_id,
|
||||
.dma_tx_param = "uart2_tx",
|
||||
.dma_rx_param = "uart2_rx",
|
||||
},
|
||||
};
|
||||
|
||||
/* Add SPEAr310 auxdata to pass platform data */
|
||||
static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
|
||||
&pl022_plat_data),
|
||||
OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
|
||||
&pl080_plat_data),
|
||||
OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
|
||||
&spear320_ssp_data[0]),
|
||||
OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
|
||||
&spear320_ssp_data[1]),
|
||||
OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
|
||||
&spear320_uart_data[0]),
|
||||
OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
|
||||
&spear320_uart_data[1]),
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init spear320_dt_init(void)
|
||||
{
|
||||
void __iomem *base;
|
||||
int ret = 0;
|
||||
int ret;
|
||||
|
||||
/* call spear3xx family common init function */
|
||||
spear3xx_init();
|
||||
pl080_plat_data.slave_channels = spear320_dma_info;
|
||||
pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
spear320_auxdata_lookup, NULL);
|
||||
|
||||
/* shared irq registration */
|
||||
base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
|
||||
@ -528,29 +458,49 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
|
||||
shirq_ras1.regs.base = base;
|
||||
ret = spear_shirq_register(&shirq_ras1);
|
||||
if (ret)
|
||||
printk(KERN_ERR "Error registering Shared IRQ 1\n");
|
||||
pr_err("Error registering Shared IRQ 1\n");
|
||||
|
||||
/* shirq 3 */
|
||||
shirq_ras3.regs.base = base;
|
||||
ret = spear_shirq_register(&shirq_ras3);
|
||||
if (ret)
|
||||
printk(KERN_ERR "Error registering Shared IRQ 3\n");
|
||||
pr_err("Error registering Shared IRQ 3\n");
|
||||
|
||||
/* shirq 4 */
|
||||
shirq_intrcomm_ras.regs.base = base;
|
||||
ret = spear_shirq_register(&shirq_intrcomm_ras);
|
||||
if (ret)
|
||||
printk(KERN_ERR "Error registering Shared IRQ 4\n");
|
||||
pr_err("Error registering Shared IRQ 4\n");
|
||||
}
|
||||
|
||||
/* pmx initialization */
|
||||
pmx_driver.base = base;
|
||||
pmx_driver.mode = pmx_mode;
|
||||
pmx_driver.devs = pmx_devs;
|
||||
pmx_driver.devs_count = pmx_dev_count;
|
||||
|
||||
ret = pmx_register(&pmx_driver);
|
||||
if (ret)
|
||||
printk(KERN_ERR "padmux: registration failed. err no: %d\n",
|
||||
ret);
|
||||
}
|
||||
|
||||
static const char * const spear320_dt_board_compat[] = {
|
||||
"st,spear320",
|
||||
"st,spear320-evb",
|
||||
NULL,
|
||||
};
|
||||
|
||||
struct map_desc spear320_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = VA_SPEAR320_SOC_CONFIG_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
};
|
||||
|
||||
static void __init spear320_map_io(void)
|
||||
{
|
||||
iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
|
||||
spear3xx_map_io();
|
||||
}
|
||||
|
||||
DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
|
||||
.map_io = spear320_map_io,
|
||||
.init_irq = spear3xx_dt_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &spear3xx_timer,
|
||||
.init_machine = spear320_dt_init,
|
||||
.restart = spear_restart,
|
||||
.dt_compat = spear320_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
||||
@ -1,79 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-spear3xx/spear320_evb.c
|
||||
*
|
||||
* SPEAr320 evaluation board source file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <mach/generic.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
/* padmux devices to enable */
|
||||
static struct pmx_dev *pmx_devs[] = {
|
||||
/* spear3xx specific devices */
|
||||
&spear3xx_pmx_i2c,
|
||||
&spear3xx_pmx_ssp,
|
||||
&spear3xx_pmx_mii,
|
||||
&spear3xx_pmx_uart0,
|
||||
|
||||
/* spear320 specific devices */
|
||||
&spear320_pmx_fsmc,
|
||||
&spear320_pmx_sdhci,
|
||||
&spear320_pmx_i2s,
|
||||
&spear320_pmx_uart1,
|
||||
&spear320_pmx_uart2,
|
||||
&spear320_pmx_can,
|
||||
&spear320_pmx_pwm0,
|
||||
&spear320_pmx_pwm1,
|
||||
&spear320_pmx_pwm2,
|
||||
&spear320_pmx_mii1,
|
||||
};
|
||||
|
||||
static struct amba_device *amba_devs[] __initdata = {
|
||||
/* spear3xx specific devices */
|
||||
&spear3xx_gpio_device,
|
||||
&spear3xx_uart_device,
|
||||
|
||||
/* spear320 specific devices */
|
||||
};
|
||||
|
||||
static struct platform_device *plat_devs[] __initdata = {
|
||||
/* spear3xx specific devices */
|
||||
|
||||
/* spear320 specific devices */
|
||||
};
|
||||
|
||||
static void __init spear320_evb_init(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
/* call spear320 machine init function */
|
||||
spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
|
||||
ARRAY_SIZE(pmx_devs));
|
||||
|
||||
/* Add Platform Devices */
|
||||
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
|
||||
|
||||
/* Add Amba Devices */
|
||||
for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
|
||||
amba_device_register(amba_devs[i], &iomem_resource);
|
||||
}
|
||||
|
||||
MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = spear3xx_map_io,
|
||||
.init_irq = spear3xx_init_irq,
|
||||
.handle_irq = vic_handle_irq,
|
||||
.timer = &spear3xx_timer,
|
||||
.init_machine = spear320_evb_init,
|
||||
.restart = spear_restart,
|
||||
MACHINE_END
|
||||
@ -3,71 +3,78 @@
|
||||
*
|
||||
* SPEAr3XX machines common source file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
* Copyright (C) 2009-2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/amba/pl061.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <mach/generic.h>
|
||||
#include <mach/hardware.h>
|
||||
#define pr_fmt(fmt) "SPEAr3xx: " fmt
|
||||
|
||||
/* Add spear3xx machines common devices here */
|
||||
/* gpio device registration */
|
||||
static struct pl061_platform_data gpio_plat_data = {
|
||||
.gpio_base = 0,
|
||||
.irq_base = SPEAR3XX_GPIO_INT_BASE,
|
||||
#include <linux/amba/pl022.h>
|
||||
#include <linux/amba/pl08x.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/hardware/pl080.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <plat/pl080.h>
|
||||
#include <mach/generic.h>
|
||||
#include <mach/spear.h>
|
||||
|
||||
/* ssp device registration */
|
||||
struct pl022_ssp_controller pl022_plat_data = {
|
||||
.bus_id = 0,
|
||||
.enable_dma = 1,
|
||||
.dma_filter = pl08x_filter_id,
|
||||
.dma_tx_param = "ssp0_tx",
|
||||
.dma_rx_param = "ssp0_rx",
|
||||
/*
|
||||
* This is number of spi devices that can be connected to spi. There are
|
||||
* two type of chipselects on which slave devices can work. One is chip
|
||||
* select provided by spi masters other is controlled through external
|
||||
* gpio's. We can't use chipselect provided from spi master (because as
|
||||
* soon as FIFO becomes empty, CS is disabled and transfer ends). So
|
||||
* this number now depends on number of gpios available for spi. each
|
||||
* slave on each master requires a separate gpio pin.
|
||||
*/
|
||||
.num_chipselect = 2,
|
||||
};
|
||||
|
||||
AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
|
||||
{SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
|
||||
/* dmac device registration */
|
||||
struct pl08x_platform_data pl080_plat_data = {
|
||||
.memcpy_channel = {
|
||||
.bus_id = "memcpy",
|
||||
.cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
|
||||
PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
|
||||
PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
|
||||
PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
|
||||
PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
|
||||
PL080_CONTROL_PROT_SYS),
|
||||
},
|
||||
.lli_buses = PL08X_AHB1,
|
||||
.mem_buses = PL08X_AHB1,
|
||||
.get_signal = pl080_get_signal,
|
||||
.put_signal = pl080_put_signal,
|
||||
};
|
||||
|
||||
/* uart device registration */
|
||||
AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
|
||||
{SPEAR3XX_IRQ_UART}, NULL);
|
||||
|
||||
/* Do spear3xx familiy common initialization part here */
|
||||
void __init spear3xx_init(void)
|
||||
{
|
||||
/* nothing to do for now */
|
||||
}
|
||||
|
||||
/* This will initialize vic */
|
||||
void __init spear3xx_init_irq(void)
|
||||
{
|
||||
vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
|
||||
}
|
||||
|
||||
/* Following will create static virtual/physical mappings */
|
||||
/*
|
||||
* Following will create 16MB static virtual/physical mappings
|
||||
* PHYSICAL VIRTUAL
|
||||
* 0xD0000000 0xFD000000
|
||||
* 0xFC000000 0xFC000000
|
||||
*/
|
||||
struct map_desc spear3xx_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = VA_SPEAR3XX_ICM1_UART_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
|
||||
.length = SZ_4K,
|
||||
.virtual = VA_SPEAR3XX_ICM1_2_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = VA_SPEAR3XX_ML1_VIC_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
|
||||
.length = SZ_4K,
|
||||
.virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
};
|
||||
@ -76,436 +83,8 @@ struct map_desc spear3xx_io_desc[] __initdata = {
|
||||
void __init spear3xx_map_io(void)
|
||||
{
|
||||
iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
|
||||
|
||||
/* This will initialize clock framework */
|
||||
spear3xx_clk_init();
|
||||
}
|
||||
|
||||
/* pad multiplexing support */
|
||||
/* devices */
|
||||
static struct pmx_dev_mode pmx_firda_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_FIRDA_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_firda = {
|
||||
.name = "firda",
|
||||
.modes = pmx_firda_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_firda_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_i2c_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_I2C_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_i2c = {
|
||||
.name = "i2c",
|
||||
.modes = pmx_i2c_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_i2c_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_SSP_CS_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_ssp_cs = {
|
||||
.name = "ssp_chip_selects",
|
||||
.modes = pmx_ssp_cs_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_ssp_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_SSP_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_ssp = {
|
||||
.name = "ssp",
|
||||
.modes = pmx_ssp_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_ssp_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_mii_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_mii = {
|
||||
.name = "mii",
|
||||
.modes = pmx_mii_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_mii_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_GPIO_PIN0_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_gpio_pin0 = {
|
||||
.name = "gpio_pin0",
|
||||
.modes = pmx_gpio_pin0_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_GPIO_PIN1_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_gpio_pin1 = {
|
||||
.name = "gpio_pin1",
|
||||
.modes = pmx_gpio_pin1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_GPIO_PIN2_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_gpio_pin2 = {
|
||||
.name = "gpio_pin2",
|
||||
.modes = pmx_gpio_pin2_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_GPIO_PIN3_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_gpio_pin3 = {
|
||||
.name = "gpio_pin3",
|
||||
.modes = pmx_gpio_pin3_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_GPIO_PIN4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_gpio_pin4 = {
|
||||
.name = "gpio_pin4",
|
||||
.modes = pmx_gpio_pin4_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_GPIO_PIN5_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_gpio_pin5 = {
|
||||
.name = "gpio_pin5",
|
||||
.modes = pmx_gpio_pin5_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_UART0_MODEM_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_uart0_modem = {
|
||||
.name = "uart0_modem",
|
||||
.modes = pmx_uart0_modem_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_uart0_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_UART0_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_uart0 = {
|
||||
.name = "uart0",
|
||||
.modes = pmx_uart0_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_uart0_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_timer_3_4 = {
|
||||
.name = "timer_3_4",
|
||||
.modes = pmx_timer_3_4_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
|
||||
{
|
||||
.ids = 0xffffffff,
|
||||
.mask = PMX_TIMER_1_2_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_timer_1_2 = {
|
||||
.name = "timer_1_2",
|
||||
.modes = pmx_timer_1_2_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
|
||||
.enb_on_reset = 0,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
|
||||
/* plgpios devices */
|
||||
static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_FIRDA_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
|
||||
.name = "plgpio 0 and 1",
|
||||
.modes = pmx_plgpio_0_1_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_UART0_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
|
||||
.name = "plgpio 2 and 3",
|
||||
.modes = pmx_plgpio_2_3_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_I2C_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
|
||||
.name = "plgpio 4 and 5",
|
||||
.modes = pmx_plgpio_4_5_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_SSP_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
|
||||
.name = "plgpio 6 to 9",
|
||||
.modes = pmx_plgpio_6_9_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_MII_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
|
||||
.name = "plgpio 10 to 27",
|
||||
.modes = pmx_plgpio_10_27_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_GPIO_PIN0_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_28 = {
|
||||
.name = "plgpio 28",
|
||||
.modes = pmx_plgpio_28_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_GPIO_PIN1_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_29 = {
|
||||
.name = "plgpio 29",
|
||||
.modes = pmx_plgpio_29_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_GPIO_PIN2_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_30 = {
|
||||
.name = "plgpio 30",
|
||||
.modes = pmx_plgpio_30_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_GPIO_PIN3_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_31 = {
|
||||
.name = "plgpio 31",
|
||||
.modes = pmx_plgpio_31_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_GPIO_PIN4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_32 = {
|
||||
.name = "plgpio 32",
|
||||
.modes = pmx_plgpio_32_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_GPIO_PIN5_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_33 = {
|
||||
.name = "plgpio 33",
|
||||
.modes = pmx_plgpio_33_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_SSP_CS_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
|
||||
.name = "plgpio 34 to 36",
|
||||
.modes = pmx_plgpio_34_36_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_UART0_MODEM_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
|
||||
.name = "plgpio 37 to 42",
|
||||
.modes = pmx_plgpio_37_42_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_TIMER_1_2_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
|
||||
.name = "plgpio 43, 44, 47 and 48",
|
||||
.modes = pmx_plgpio_43_44_47_48_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
|
||||
static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
|
||||
{
|
||||
.ids = 0x00,
|
||||
.mask = PMX_TIMER_3_4_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
|
||||
.name = "plgpio 45, 46, 49 and 50",
|
||||
.modes = pmx_plgpio_45_46_49_50_modes,
|
||||
.mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
|
||||
.enb_on_reset = 1,
|
||||
};
|
||||
#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
|
||||
|
||||
static void __init spear3xx_timer_init(void)
|
||||
{
|
||||
char pclk_name[] = "pll3_48m_clk";
|
||||
@ -532,9 +111,19 @@ static void __init spear3xx_timer_init(void)
|
||||
clk_put(gpt_clk);
|
||||
clk_put(pclk);
|
||||
|
||||
spear_setup_timer();
|
||||
spear_setup_of_timer();
|
||||
}
|
||||
|
||||
struct sys_timer spear3xx_timer = {
|
||||
.init = spear3xx_timer_init,
|
||||
};
|
||||
|
||||
static const struct of_device_id vic_of_match[] __initconst = {
|
||||
{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
|
||||
{ /* Sentinel */ }
|
||||
};
|
||||
|
||||
void __init spear3xx_dt_init_irq(void)
|
||||
{
|
||||
of_irq_init(vic_of_match);
|
||||
}
|
||||
|
||||
@ -1,3 +1,5 @@
|
||||
zreladdr-y += 0x00008000
|
||||
params_phys-y := 0x00000100
|
||||
initrd_phys-y := 0x00800000
|
||||
|
||||
dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb
|
||||
|
||||
@ -15,34 +15,9 @@
|
||||
#define __MACH_GENERIC_H
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/amba/bus.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
/*
|
||||
* Each GPT has 2 timer channels
|
||||
* Following GPT channels will be used as clock source and clockevent
|
||||
*/
|
||||
#define SPEAR_GPT0_BASE SPEAR6XX_CPU_TMR_BASE
|
||||
#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1
|
||||
#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2
|
||||
|
||||
/* Add spear6xx family device structure declarations here */
|
||||
extern struct amba_device gpio_device[];
|
||||
extern struct amba_device uart_device[];
|
||||
extern struct sys_timer spear6xx_timer;
|
||||
|
||||
/* Add spear6xx family function declarations here */
|
||||
void __init spear_setup_timer(void);
|
||||
void __init spear6xx_map_io(void);
|
||||
void __init spear6xx_init_irq(void);
|
||||
void __init spear6xx_init(void);
|
||||
void __init spear600_init(void);
|
||||
void __init spear_setup_of_timer(void);
|
||||
void spear_restart(char, const char *);
|
||||
void __init spear6xx_clk_init(void);
|
||||
|
||||
void spear_restart(char, const char *);
|
||||
|
||||
/* Add spear600 machine device structure declarations here */
|
||||
|
||||
#endif /* __MACH_GENERIC_H */
|
||||
|
||||
@ -1,23 +1 @@
|
||||
/*
|
||||
* arch/arm/mach-spear6xx/include/mach/hardware.h
|
||||
*
|
||||
* Hardware definitions for SPEAr6xx machine family
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Rajeev Kumar<rajeev-dlh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_HARDWARE_H
|
||||
#define __MACH_HARDWARE_H
|
||||
|
||||
#include <plat/hardware.h>
|
||||
#include <mach/spear.h>
|
||||
|
||||
/* Vitual to physical translation of statically mapped space */
|
||||
#define IO_ADDRESS(x) (x | 0xF0000000)
|
||||
|
||||
#endif /* __MACH_HARDWARE_H */
|
||||
/* empty */
|
||||
|
||||
@ -16,82 +16,10 @@
|
||||
|
||||
/* IRQ definitions */
|
||||
/* VIC 1 */
|
||||
#define IRQ_INTRCOMM_SW_IRQ 0
|
||||
#define IRQ_INTRCOMM_CPU_1 1
|
||||
#define IRQ_INTRCOMM_CPU_2 2
|
||||
#define IRQ_INTRCOMM_RAS2A11_1 3
|
||||
#define IRQ_INTRCOMM_RAS2A11_2 4
|
||||
#define IRQ_INTRCOMM_RAS2A12_1 5
|
||||
#define IRQ_INTRCOMM_RAS2A12_2 6
|
||||
#define IRQ_GEN_RAS_0 7
|
||||
#define IRQ_GEN_RAS_1 8
|
||||
#define IRQ_GEN_RAS_2 9
|
||||
#define IRQ_GEN_RAS_3 10
|
||||
#define IRQ_GEN_RAS_4 11
|
||||
#define IRQ_GEN_RAS_5 12
|
||||
#define IRQ_GEN_RAS_6 13
|
||||
#define IRQ_GEN_RAS_7 14
|
||||
#define IRQ_GEN_RAS_8 15
|
||||
#define IRQ_CPU_GPT1_1 16
|
||||
#define IRQ_CPU_GPT1_2 17
|
||||
#define IRQ_LOCAL_GPIO 18
|
||||
#define IRQ_PLL_UNLOCK 19
|
||||
#define IRQ_JPEG 20
|
||||
#define IRQ_FSMC 21
|
||||
#define IRQ_IRDA 22
|
||||
#define IRQ_RESERVED 23
|
||||
#define IRQ_UART_0 24
|
||||
#define IRQ_UART_1 25
|
||||
#define IRQ_SSP_1 26
|
||||
#define IRQ_SSP_2 27
|
||||
#define IRQ_I2C 28
|
||||
#define IRQ_GEN_RAS_9 29
|
||||
#define IRQ_GEN_RAS_10 30
|
||||
#define IRQ_GEN_RAS_11 31
|
||||
|
||||
/* VIC 2 */
|
||||
#define IRQ_APPL_GPT1_1 32
|
||||
#define IRQ_APPL_GPT1_2 33
|
||||
#define IRQ_APPL_GPT2_1 34
|
||||
#define IRQ_APPL_GPT2_2 35
|
||||
#define IRQ_APPL_GPIO 36
|
||||
#define IRQ_APPL_SSP 37
|
||||
#define IRQ_APPL_ADC 38
|
||||
#define IRQ_APPL_RESERVED 39
|
||||
#define IRQ_AHB_EXP_MASTER 40
|
||||
#define IRQ_DDR_CONTROLLER 41
|
||||
#define IRQ_BASIC_DMA 42
|
||||
#define IRQ_BASIC_RESERVED1 43
|
||||
#define IRQ_BASIC_SMI 44
|
||||
#define IRQ_BASIC_CLCD 45
|
||||
#define IRQ_EXP_AHB_1 46
|
||||
#define IRQ_EXP_AHB_2 47
|
||||
#define IRQ_BASIC_GPT1_1 48
|
||||
#define IRQ_BASIC_GPT1_2 49
|
||||
#define IRQ_BASIC_RTC 50
|
||||
#define IRQ_BASIC_GPIO 51
|
||||
#define IRQ_BASIC_WDT 52
|
||||
#define IRQ_BASIC_RESERVED 53
|
||||
#define IRQ_AHB_EXP_SLAVE 54
|
||||
#define IRQ_GMAC_1 55
|
||||
#define IRQ_GMAC_2 56
|
||||
#define IRQ_USB_DEV 57
|
||||
#define IRQ_USB_H_OHCI_0 58
|
||||
#define IRQ_USB_H_EHCI_0 59
|
||||
#define IRQ_USB_H_OHCI_1 60
|
||||
#define IRQ_USB_H_EHCI_1 61
|
||||
#define IRQ_EXP_AHB_3 62
|
||||
#define IRQ_EXP_AHB_4 63
|
||||
|
||||
#define IRQ_VIC_END 64
|
||||
|
||||
/* GPIO pins virtual irqs */
|
||||
#define SPEAR_GPIO_INT_BASE IRQ_VIC_END
|
||||
#define SPEAR_GPIO0_INT_BASE SPEAR_GPIO_INT_BASE
|
||||
#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8)
|
||||
#define SPEAR_GPIO2_INT_BASE (SPEAR_GPIO1_INT_BASE + 8)
|
||||
#define SPEAR_GPIO_INT_END (SPEAR_GPIO2_INT_BASE + 8)
|
||||
#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END)
|
||||
#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
|
||||
#define VIRTUAL_IRQS 24
|
||||
#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
|
||||
|
||||
#endif /* __MACH_IRQS_H */
|
||||
|
||||
@ -14,9 +14,9 @@
|
||||
#ifndef __MACH_MISC_REGS_H
|
||||
#define __MACH_MISC_REGS_H
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/spear.h>
|
||||
|
||||
#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
|
||||
#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
|
||||
|
||||
#endif /* __MACH_MISC_REGS_H */
|
||||
|
||||
@ -15,69 +15,25 @@
|
||||
#define __MACH_SPEAR6XX_H
|
||||
|
||||
#include <asm/memory.h>
|
||||
#include <mach/spear600.h>
|
||||
|
||||
#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000)
|
||||
/* ICM1 - Low speed connection */
|
||||
#define SPEAR6XX_ICM1_BASE UL(0xD0000000)
|
||||
|
||||
#define VA_SPEAR6XX_ICM1_BASE UL(0xFD000000)
|
||||
#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000)
|
||||
#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
|
||||
|
||||
#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000)
|
||||
#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000)
|
||||
#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000)
|
||||
#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000)
|
||||
#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000)
|
||||
#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000)
|
||||
#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000)
|
||||
#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000)
|
||||
#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000)
|
||||
|
||||
/* ICM2 - Application Subsystem */
|
||||
#define SPEAR6XX_ICM2_BASE UL(0xD8000000)
|
||||
#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000)
|
||||
#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000)
|
||||
#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000)
|
||||
#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000)
|
||||
#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000)
|
||||
#define VA_SPEAR6XX_ICM1_UART0_BASE (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
|
||||
|
||||
/* ML-1, 2 - Multi Layer CPU Subsystem */
|
||||
#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
|
||||
#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000)
|
||||
#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000)
|
||||
#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000)
|
||||
#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
|
||||
#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000)
|
||||
#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
|
||||
#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
|
||||
|
||||
/* ICM3 - Basic Subsystem */
|
||||
#define SPEAR6XX_ICM3_BASE UL(0xF8000000)
|
||||
#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000)
|
||||
#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
|
||||
#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000)
|
||||
#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
|
||||
#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000)
|
||||
#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
|
||||
#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000)
|
||||
#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000)
|
||||
#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000)
|
||||
#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000)
|
||||
#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
|
||||
#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
|
||||
#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
|
||||
#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
|
||||
#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
|
||||
|
||||
/* ICM4 - High Speed Connection */
|
||||
#define SPEAR6XX_ICM4_BASE UL(0xE0000000)
|
||||
#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000)
|
||||
#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
|
||||
#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
|
||||
#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
|
||||
#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000)
|
||||
#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
|
||||
#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000)
|
||||
#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
|
||||
#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000)
|
||||
#define VA_SPEAR6XX_ICM3_MISC_REG_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
|
||||
|
||||
/* Debug uart for linux, will be used for debug and uncompress messages */
|
||||
#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE
|
||||
|
||||
@ -1,21 +0,0 @@
|
||||
/*
|
||||
* arch/arm/mach-spear66xx/include/mach/spear600.h
|
||||
*
|
||||
* SPEAr600 Machine specific definition
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_MACH_SPEAR600
|
||||
|
||||
#ifndef __MACH_SPEAR600_H
|
||||
#define __MACH_SPEAR600_H
|
||||
|
||||
#endif /* __MACH_SPEAR600_H */
|
||||
|
||||
#endif /* CONFIG_MACH_SPEAR600 */
|
||||
@ -13,41 +13,404 @@
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/amba/pl08x.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/hardware/pl080.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <plat/pl080.h>
|
||||
#include <mach/generic.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/spear.h>
|
||||
|
||||
/* Following will create static virtual/physical mappings */
|
||||
static struct map_desc spear6xx_io_desc[] __initdata = {
|
||||
/* dmac device registration */
|
||||
static struct pl08x_channel_data spear600_dma_info[] = {
|
||||
{
|
||||
.virtual = VA_SPEAR6XX_ICM1_UART0_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE),
|
||||
.length = SZ_4K,
|
||||
.bus_id = "ssp1_rx",
|
||||
.min_signal = 0,
|
||||
.max_signal = 0,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp1_tx",
|
||||
.min_signal = 1,
|
||||
.max_signal = 1,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart0_rx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart0_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart1_rx",
|
||||
.min_signal = 4,
|
||||
.max_signal = 4,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "uart1_tx",
|
||||
.min_signal = 5,
|
||||
.max_signal = 5,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp2_rx",
|
||||
.min_signal = 6,
|
||||
.max_signal = 6,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ssp2_tx",
|
||||
.min_signal = 7,
|
||||
.max_signal = 7,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ssp0_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ssp0_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "i2c_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "irda",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "adc",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "to_jpeg",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "from_jpeg",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 0,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras0_rx",
|
||||
.min_signal = 0,
|
||||
.max_signal = 0,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras0_tx",
|
||||
.min_signal = 1,
|
||||
.max_signal = 1,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras1_rx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras1_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras2_rx",
|
||||
.min_signal = 4,
|
||||
.max_signal = 4,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras2_tx",
|
||||
.min_signal = 5,
|
||||
.max_signal = 5,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras3_rx",
|
||||
.min_signal = 6,
|
||||
.max_signal = 6,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras3_tx",
|
||||
.min_signal = 7,
|
||||
.max_signal = 7,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras4_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras4_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras5_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras5_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras6_rx",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras6_tx",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras7_rx",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ras7_tx",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 1,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
}, {
|
||||
.bus_id = "ext0_rx",
|
||||
.min_signal = 0,
|
||||
.max_signal = 0,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext0_tx",
|
||||
.min_signal = 1,
|
||||
.max_signal = 1,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext1_rx",
|
||||
.min_signal = 2,
|
||||
.max_signal = 2,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext1_tx",
|
||||
.min_signal = 3,
|
||||
.max_signal = 3,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext2_rx",
|
||||
.min_signal = 4,
|
||||
.max_signal = 4,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext2_tx",
|
||||
.min_signal = 5,
|
||||
.max_signal = 5,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext3_rx",
|
||||
.min_signal = 6,
|
||||
.max_signal = 6,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext3_tx",
|
||||
.min_signal = 7,
|
||||
.max_signal = 7,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext4_rx",
|
||||
.min_signal = 8,
|
||||
.max_signal = 8,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext4_tx",
|
||||
.min_signal = 9,
|
||||
.max_signal = 9,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext5_rx",
|
||||
.min_signal = 10,
|
||||
.max_signal = 10,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext5_tx",
|
||||
.min_signal = 11,
|
||||
.max_signal = 11,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext6_rx",
|
||||
.min_signal = 12,
|
||||
.max_signal = 12,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext6_tx",
|
||||
.min_signal = 13,
|
||||
.max_signal = 13,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext7_rx",
|
||||
.min_signal = 14,
|
||||
.max_signal = 14,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
}, {
|
||||
.bus_id = "ext7_tx",
|
||||
.min_signal = 15,
|
||||
.max_signal = 15,
|
||||
.muxval = 2,
|
||||
.cctl = 0,
|
||||
.periph_buses = PL08X_AHB2,
|
||||
},
|
||||
};
|
||||
|
||||
struct pl08x_platform_data pl080_plat_data = {
|
||||
.memcpy_channel = {
|
||||
.bus_id = "memcpy",
|
||||
.cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
|
||||
PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
|
||||
PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
|
||||
PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
|
||||
PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
|
||||
PL080_CONTROL_PROT_SYS),
|
||||
},
|
||||
.lli_buses = PL08X_AHB1,
|
||||
.mem_buses = PL08X_AHB1,
|
||||
.get_signal = pl080_get_signal,
|
||||
.put_signal = pl080_put_signal,
|
||||
.slave_channels = spear600_dma_info,
|
||||
.num_slave_channels = ARRAY_SIZE(spear600_dma_info),
|
||||
};
|
||||
|
||||
/*
|
||||
* Following will create 16MB static virtual/physical mappings
|
||||
* PHYSICAL VIRTUAL
|
||||
* 0xF0000000 0xF0000000
|
||||
* 0xF1000000 0xF1000000
|
||||
* 0xD0000000 0xFD000000
|
||||
* 0xFC000000 0xFC000000
|
||||
*/
|
||||
struct map_desc spear6xx_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = VA_SPEAR6XX_ML_CPU_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
|
||||
.length = 2 * SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = VA_SPEAR6XX_ICM1_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE),
|
||||
.length = SZ_4K,
|
||||
.virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
|
||||
.pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
};
|
||||
@ -84,16 +447,24 @@ static void __init spear6xx_timer_init(void)
|
||||
clk_put(gpt_clk);
|
||||
clk_put(pclk);
|
||||
|
||||
spear_setup_timer();
|
||||
spear_setup_of_timer();
|
||||
}
|
||||
|
||||
struct sys_timer spear6xx_timer = {
|
||||
.init = spear6xx_timer_init,
|
||||
};
|
||||
|
||||
/* Add auxdata to pass platform data */
|
||||
struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
|
||||
&pl080_plat_data),
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init spear600_dt_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
spear6xx_auxdata_lookup, NULL);
|
||||
}
|
||||
|
||||
static const char *spear600_dt_board_compat[] = {
|
||||
|
||||
@ -9,9 +9,11 @@ choice
|
||||
default ARCH_SPEAR3XX
|
||||
|
||||
config ARCH_SPEAR3XX
|
||||
bool "SPEAr3XX"
|
||||
bool "ST SPEAr3xx with Device Tree"
|
||||
select ARM_VIC
|
||||
select CPU_ARM926T
|
||||
select USE_OF
|
||||
select PINCTRL
|
||||
help
|
||||
Supports for ARM's SPEAR3XX family
|
||||
|
||||
|
||||
@ -3,6 +3,6 @@
|
||||
#
|
||||
|
||||
# Common support
|
||||
obj-y := restart.o time.o
|
||||
obj-y := restart.o time.o pl080.o
|
||||
|
||||
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o
|
||||
obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
*/
|
||||
|
||||
#include <linux/amba/serial.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/spear.h>
|
||||
|
||||
.macro addruart, rp, rv, tmp
|
||||
mov \rp, #SPEAR_DBG_UART_BASE @ Physical base
|
||||
|
||||
@ -1,17 +0,0 @@
|
||||
/*
|
||||
* arch/arm/plat-spear/include/plat/hardware.h
|
||||
*
|
||||
* Hardware definitions for SPEAr
|
||||
*
|
||||
* Copyright (C) 2010 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_HARDWARE_H
|
||||
#define __PLAT_HARDWARE_H
|
||||
|
||||
#endif /* __PLAT_HARDWARE_H */
|
||||
@ -1,92 +0,0 @@
|
||||
/*
|
||||
* arch/arm/plat-spear/include/plat/padmux.h
|
||||
*
|
||||
* SPEAr platform specific gpio pads muxing file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_PADMUX_H
|
||||
#define __PLAT_PADMUX_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/*
|
||||
* struct pmx_reg: configuration structure for mode reg and mux reg
|
||||
*
|
||||
* offset: offset of mode reg
|
||||
* mask: mask of mode reg
|
||||
*/
|
||||
struct pmx_reg {
|
||||
u32 offset;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct pmx_dev_mode: configuration structure every group of modes of a device
|
||||
*
|
||||
* ids: all modes for this configuration
|
||||
* mask: mask for supported mode
|
||||
*/
|
||||
struct pmx_dev_mode {
|
||||
u32 ids;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct pmx_mode: mode definition structure
|
||||
*
|
||||
* name: mode name
|
||||
* mask: mode mask
|
||||
*/
|
||||
struct pmx_mode {
|
||||
char *name;
|
||||
u32 id;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct pmx_dev: device definition structure
|
||||
*
|
||||
* name: device name
|
||||
* modes: device configuration array for different modes supported
|
||||
* mode_count: size of modes array
|
||||
* is_active: is peripheral active/enabled
|
||||
* enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
|
||||
*/
|
||||
struct pmx_dev {
|
||||
char *name;
|
||||
struct pmx_dev_mode *modes;
|
||||
u8 mode_count;
|
||||
bool is_active;
|
||||
bool enb_on_reset;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct pmx_driver: driver definition structure
|
||||
*
|
||||
* mode: mode to be set
|
||||
* devs: array of pointer to pmx devices
|
||||
* devs_count: ARRAY_SIZE of devs
|
||||
* base: base address of soc config registers
|
||||
* mode_reg: structure of mode config register
|
||||
* mux_reg: structure of device mux config register
|
||||
*/
|
||||
struct pmx_driver {
|
||||
struct pmx_mode *mode;
|
||||
struct pmx_dev **devs;
|
||||
u8 devs_count;
|
||||
u32 *base;
|
||||
struct pmx_reg mode_reg;
|
||||
struct pmx_reg mux_reg;
|
||||
};
|
||||
|
||||
/* pmx functions */
|
||||
int pmx_register(struct pmx_driver *driver);
|
||||
|
||||
#endif /* __PLAT_PADMUX_H */
|
||||
21
arch/arm/plat-spear/include/plat/pl080.h
Normal file
21
arch/arm/plat-spear/include/plat/pl080.h
Normal file
@ -0,0 +1,21 @@
|
||||
/*
|
||||
* arch/arm/plat-spear/include/plat/pl080.h
|
||||
*
|
||||
* DMAC pl080 definitions for SPEAr platform
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_PL080_H
|
||||
#define __PLAT_PL080_H
|
||||
|
||||
struct pl08x_dma_chan;
|
||||
int pl080_get_signal(struct pl08x_dma_chan *ch);
|
||||
void pl080_put_signal(struct pl08x_dma_chan *ch);
|
||||
|
||||
#endif /* __PLAT_PL080_H */
|
||||
@ -13,7 +13,7 @@
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/amba/serial.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/spear.h>
|
||||
|
||||
#ifndef __PLAT_UNCOMPRESS_H
|
||||
#define __PLAT_UNCOMPRESS_H
|
||||
|
||||
@ -1,164 +0,0 @@
|
||||
/*
|
||||
* arch/arm/plat-spear/include/plat/padmux.c
|
||||
*
|
||||
* SPEAr platform specific gpio pads muxing source file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include <plat/padmux.h>
|
||||
|
||||
/*
|
||||
* struct pmx: pmx definition structure
|
||||
*
|
||||
* base: base address of configuration registers
|
||||
* mode_reg: mode configurations
|
||||
* mux_reg: muxing configurations
|
||||
* active_mode: pointer to current active mode
|
||||
*/
|
||||
struct pmx {
|
||||
u32 base;
|
||||
struct pmx_reg mode_reg;
|
||||
struct pmx_reg mux_reg;
|
||||
struct pmx_mode *active_mode;
|
||||
};
|
||||
|
||||
static struct pmx *pmx;
|
||||
|
||||
/**
|
||||
* pmx_mode_set - Enables an multiplexing mode
|
||||
* @mode - pointer to pmx mode
|
||||
*
|
||||
* It will set mode of operation in hardware.
|
||||
* Returns -ve on Err otherwise 0
|
||||
*/
|
||||
static int pmx_mode_set(struct pmx_mode *mode)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (!mode->name)
|
||||
return -EFAULT;
|
||||
|
||||
pmx->active_mode = mode;
|
||||
|
||||
val = readl(pmx->base + pmx->mode_reg.offset);
|
||||
val &= ~pmx->mode_reg.mask;
|
||||
val |= mode->mask & pmx->mode_reg.mask;
|
||||
writel(val, pmx->base + pmx->mode_reg.offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* pmx_devs_enable - Enables list of devices
|
||||
* @devs - pointer to pmx device array
|
||||
* @count - number of devices to enable
|
||||
*
|
||||
* It will enable pads for all required peripherals once and only once.
|
||||
* If peripheral is not supported by current mode then request is rejected.
|
||||
* Conflicts between peripherals are not handled and peripherals will be
|
||||
* enabled in the order they are present in pmx_dev array.
|
||||
* In case of conflicts last peripheral enabled will be present.
|
||||
* Returns -ve on Err otherwise 0
|
||||
*/
|
||||
static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
|
||||
{
|
||||
u32 val, i, mask;
|
||||
|
||||
if (!count)
|
||||
return -EINVAL;
|
||||
|
||||
val = readl(pmx->base + pmx->mux_reg.offset);
|
||||
for (i = 0; i < count; i++) {
|
||||
u8 j = 0;
|
||||
|
||||
if (!devs[i]->name || !devs[i]->modes) {
|
||||
printk(KERN_ERR "padmux: dev name or modes is null\n");
|
||||
continue;
|
||||
}
|
||||
/* check if peripheral exists in active mode */
|
||||
if (pmx->active_mode) {
|
||||
bool found = false;
|
||||
for (j = 0; j < devs[i]->mode_count; j++) {
|
||||
if (devs[i]->modes[j].ids &
|
||||
pmx->active_mode->id) {
|
||||
found = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (found == false) {
|
||||
printk(KERN_ERR "%s device not available in %s"\
|
||||
"mode\n", devs[i]->name,
|
||||
pmx->active_mode->name);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
/* enable peripheral */
|
||||
mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
|
||||
if (devs[i]->enb_on_reset)
|
||||
val &= ~mask;
|
||||
else
|
||||
val |= mask;
|
||||
|
||||
devs[i]->is_active = true;
|
||||
}
|
||||
writel(val, pmx->base + pmx->mux_reg.offset);
|
||||
kfree(pmx);
|
||||
|
||||
/* this will ensure that multiplexing can't be changed now */
|
||||
pmx = (struct pmx *)-1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* pmx_register - registers a platform requesting pad mux feature
|
||||
* @driver - pointer to driver structure containing driver specific parameters
|
||||
*
|
||||
* Also this must be called only once. This will allocate memory for pmx
|
||||
* structure, will call pmx_mode_set, will call pmx_devs_enable.
|
||||
* Returns -ve on Err otherwise 0
|
||||
*/
|
||||
int pmx_register(struct pmx_driver *driver)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (pmx)
|
||||
return -EPERM;
|
||||
if (!driver->base || !driver->devs)
|
||||
return -EFAULT;
|
||||
|
||||
pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
|
||||
if (!pmx)
|
||||
return -ENOMEM;
|
||||
|
||||
pmx->base = (u32)driver->base;
|
||||
pmx->mode_reg.offset = driver->mode_reg.offset;
|
||||
pmx->mode_reg.mask = driver->mode_reg.mask;
|
||||
pmx->mux_reg.offset = driver->mux_reg.offset;
|
||||
pmx->mux_reg.mask = driver->mux_reg.mask;
|
||||
|
||||
/* choose mode to enable */
|
||||
if (driver->mode) {
|
||||
ret = pmx_mode_set(driver->mode);
|
||||
if (ret)
|
||||
goto pmx_fail;
|
||||
}
|
||||
ret = pmx_devs_enable(driver->devs, driver->devs_count);
|
||||
if (ret)
|
||||
goto pmx_fail;
|
||||
|
||||
return 0;
|
||||
|
||||
pmx_fail:
|
||||
return ret;
|
||||
}
|
||||
80
arch/arm/plat-spear/pl080.c
Normal file
80
arch/arm/plat-spear/pl080.c
Normal file
@ -0,0 +1,80 @@
|
||||
/*
|
||||
* arch/arm/plat-spear/pl080.c
|
||||
*
|
||||
* DMAC pl080 definitions for SPEAr platform
|
||||
*
|
||||
* Copyright (C) 2012 ST Microelectronics
|
||||
* Viresh Kumar <viresh.kumar@st.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/amba/pl08x.h>
|
||||
#include <linux/amba/bus.h>
|
||||
#include <linux/bug.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/spinlock_types.h>
|
||||
#include <mach/spear.h>
|
||||
#include <mach/misc_regs.h>
|
||||
|
||||
static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
|
||||
|
||||
struct {
|
||||
unsigned char busy;
|
||||
unsigned char val;
|
||||
} signals[16] = {{0, 0}, };
|
||||
|
||||
int pl080_get_signal(struct pl08x_dma_chan *ch)
|
||||
{
|
||||
const struct pl08x_channel_data *cd = ch->cd;
|
||||
unsigned int signal = cd->min_signal, val;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&lock, flags);
|
||||
|
||||
/* Return if signal is already acquired by somebody else */
|
||||
if (signals[signal].busy &&
|
||||
(signals[signal].val != cd->muxval)) {
|
||||
spin_unlock_irqrestore(&lock, flags);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* If acquiring for the first time, configure it */
|
||||
if (!signals[signal].busy) {
|
||||
val = readl(DMA_CHN_CFG);
|
||||
|
||||
/*
|
||||
* Each request line has two bits in DMA_CHN_CFG register. To
|
||||
* goto the bits of current request line, do left shift of
|
||||
* value by 2 * signal number.
|
||||
*/
|
||||
val &= ~(0x3 << (signal * 2));
|
||||
val |= cd->muxval << (signal * 2);
|
||||
writel(val, DMA_CHN_CFG);
|
||||
}
|
||||
|
||||
signals[signal].busy++;
|
||||
signals[signal].val = cd->muxval;
|
||||
spin_unlock_irqrestore(&lock, flags);
|
||||
|
||||
return signal;
|
||||
}
|
||||
|
||||
void pl080_put_signal(struct pl08x_dma_chan *ch)
|
||||
{
|
||||
const struct pl08x_channel_data *cd = ch->cd;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&lock, flags);
|
||||
|
||||
/* if signal is not used */
|
||||
if (!signals[cd->min_signal].busy)
|
||||
BUG();
|
||||
|
||||
signals[cd->min_signal].busy--;
|
||||
|
||||
spin_unlock_irqrestore(&lock, flags);
|
||||
}
|
||||
@ -13,7 +13,7 @@
|
||||
#include <linux/io.h>
|
||||
#include <asm/system_misc.h>
|
||||
#include <asm/hardware/sp810.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/spear.h>
|
||||
#include <mach/generic.h>
|
||||
|
||||
void spear_restart(char mode, const char *cmd)
|
||||
|
||||
@ -15,14 +15,15 @@
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/time.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/generic.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
/*
|
||||
* We would use TIMER0 and TIMER1 as clockevent and clocksource.
|
||||
@ -175,7 +176,7 @@ static struct irqaction spear_timer_irq = {
|
||||
.handler = spear_timer_interrupt
|
||||
};
|
||||
|
||||
static void __init spear_clockevent_init(void)
|
||||
static void __init spear_clockevent_init(int irq)
|
||||
{
|
||||
u32 tick_rate;
|
||||
|
||||
@ -195,22 +196,35 @@ static void __init spear_clockevent_init(void)
|
||||
|
||||
clockevents_register_device(&clkevt);
|
||||
|
||||
setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq);
|
||||
setup_irq(irq, &spear_timer_irq);
|
||||
}
|
||||
|
||||
void __init spear_setup_timer(void)
|
||||
{
|
||||
int ret;
|
||||
const static struct of_device_id timer_of_match[] __initconst = {
|
||||
{ .compatible = "st,spear-timer", },
|
||||
{ },
|
||||
};
|
||||
|
||||
if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) {
|
||||
pr_err("%s:cannot get IO addr\n", __func__);
|
||||
void __init spear_setup_of_timer(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
int irq, ret;
|
||||
|
||||
np = of_find_matching_node(NULL, timer_of_match);
|
||||
if (!np) {
|
||||
pr_err("%s: No timer passed via DT\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K);
|
||||
irq = irq_of_parse_and_map(np, 0);
|
||||
if (!irq) {
|
||||
pr_err("%s: No irq passed for timer via DT\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
gpt_base = of_iomap(np, 0);
|
||||
if (!gpt_base) {
|
||||
pr_err("%s:ioremap failed for gpt\n", __func__);
|
||||
goto err_mem;
|
||||
pr_err("%s: of iomap failed\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
gpt_clk = clk_get_sys("gpt0", NULL);
|
||||
@ -225,7 +239,7 @@ void __init spear_setup_timer(void)
|
||||
goto err_prepare_enable_clk;
|
||||
}
|
||||
|
||||
spear_clockevent_init();
|
||||
spear_clockevent_init(irq);
|
||||
spear_clocksource_init();
|
||||
|
||||
return;
|
||||
@ -234,6 +248,4 @@ err_prepare_enable_clk:
|
||||
clk_put(gpt_clk);
|
||||
err_iomap:
|
||||
iounmap(gpt_base);
|
||||
err_mem:
|
||||
release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
|
||||
}
|
||||
|
||||
@ -51,6 +51,7 @@
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_i2c.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/hardware.h>
|
||||
@ -470,6 +471,7 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
|
||||
struct imx_i2c_struct *i2c_imx;
|
||||
struct resource *res;
|
||||
struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
|
||||
struct pinctrl *pinctrl;
|
||||
void __iomem *base;
|
||||
resource_size_t res_size;
|
||||
int irq, bitrate;
|
||||
@ -520,6 +522,12 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
|
||||
i2c_imx->base = base;
|
||||
i2c_imx->res = res;
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
if (IS_ERR(pinctrl)) {
|
||||
ret = PTR_ERR(pinctrl);
|
||||
goto fail3;
|
||||
}
|
||||
|
||||
/* Get I2C clock */
|
||||
i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk");
|
||||
if (IS_ERR(i2c_imx->clk)) {
|
||||
|
||||
@ -26,6 +26,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
|
||||
@ -325,10 +326,15 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev)
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mxs_i2c_dev *i2c;
|
||||
struct i2c_adapter *adap;
|
||||
struct pinctrl *pinctrl;
|
||||
struct resource *res;
|
||||
resource_size_t res_size;
|
||||
int err, irq;
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(dev);
|
||||
if (IS_ERR(pinctrl))
|
||||
return PTR_ERR(pinctrl);
|
||||
|
||||
i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
|
||||
if (!i2c)
|
||||
return -ENOMEM;
|
||||
|
||||
@ -39,6 +39,7 @@
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/fsl/mxs-dma.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <mach/mxs.h>
|
||||
#include <mach/common.h>
|
||||
@ -682,6 +683,7 @@ static int mxs_mmc_probe(struct platform_device *pdev)
|
||||
struct mmc_host *mmc;
|
||||
struct resource *iores, *dmares, *r;
|
||||
struct mxs_mmc_platform_data *pdata;
|
||||
struct pinctrl *pinctrl;
|
||||
int ret = 0, irq_err, irq_dma;
|
||||
dma_cap_mask_t mask;
|
||||
|
||||
@ -719,6 +721,12 @@ static int mxs_mmc_probe(struct platform_device *pdev)
|
||||
host->irq = irq_err;
|
||||
host->sdio_irq_en = 0;
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
if (IS_ERR(pinctrl)) {
|
||||
ret = PTR_ERR(pinctrl);
|
||||
goto out_iounmap;
|
||||
}
|
||||
|
||||
host->clk = clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(host->clk)) {
|
||||
ret = PTR_ERR(host->clk);
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <mach/esdhc.h>
|
||||
#include "sdhci-pltfm.h"
|
||||
#include "sdhci-esdhc.h"
|
||||
@ -68,6 +69,7 @@ struct pltfm_imx_data {
|
||||
int flags;
|
||||
u32 scratchpad;
|
||||
enum imx_esdhc_type devtype;
|
||||
struct pinctrl *pinctrl;
|
||||
struct esdhc_platform_data boarddata;
|
||||
struct clk *clk_ipg;
|
||||
struct clk *clk_ahb;
|
||||
@ -484,6 +486,12 @@ static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev)
|
||||
clk_prepare_enable(imx_data->clk_ipg);
|
||||
clk_prepare_enable(imx_data->clk_ahb);
|
||||
|
||||
imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
if (IS_ERR(imx_data->pinctrl)) {
|
||||
err = PTR_ERR(imx_data->pinctrl);
|
||||
goto pin_err;
|
||||
}
|
||||
|
||||
host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
|
||||
|
||||
if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
|
||||
@ -575,6 +583,7 @@ no_card_detect_irq:
|
||||
gpio_free(boarddata->wp_gpio);
|
||||
no_card_detect_pin:
|
||||
no_board_data:
|
||||
pin_err:
|
||||
clk_disable_unprepare(imx_data->clk_per);
|
||||
clk_disable_unprepare(imx_data->clk_ipg);
|
||||
clk_disable_unprepare(imx_data->clk_ahb);
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/mtd/gpmi-nand.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include "gpmi-nand.h"
|
||||
|
||||
/* add our owner bbt descriptor */
|
||||
@ -476,6 +477,7 @@ acquire_err:
|
||||
static int __devinit acquire_resources(struct gpmi_nand_data *this)
|
||||
{
|
||||
struct resources *res = &this->resources;
|
||||
struct pinctrl *pinctrl;
|
||||
int ret;
|
||||
|
||||
ret = acquire_register_block(this, GPMI_NAND_GPMI_REGS_ADDR_RES_NAME);
|
||||
@ -494,6 +496,12 @@ static int __devinit acquire_resources(struct gpmi_nand_data *this)
|
||||
if (ret)
|
||||
goto exit_dma_channels;
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
if (IS_ERR(pinctrl)) {
|
||||
ret = PTR_ERR(pinctrl);
|
||||
goto exit_pin;
|
||||
}
|
||||
|
||||
res->clock = clk_get(&this->pdev->dev, NULL);
|
||||
if (IS_ERR(res->clock)) {
|
||||
pr_err("can not get the clock\n");
|
||||
@ -503,6 +511,7 @@ static int __devinit acquire_resources(struct gpmi_nand_data *this)
|
||||
return 0;
|
||||
|
||||
exit_clock:
|
||||
exit_pin:
|
||||
release_dma_channels(this);
|
||||
exit_dma_channels:
|
||||
release_bch_irq(this);
|
||||
|
||||
@ -35,6 +35,7 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#define DRV_NAME "flexcan"
|
||||
|
||||
@ -927,11 +928,16 @@ static int __devinit flexcan_probe(struct platform_device *pdev)
|
||||
struct flexcan_priv *priv;
|
||||
struct resource *mem;
|
||||
struct clk *clk = NULL;
|
||||
struct pinctrl *pinctrl;
|
||||
void __iomem *base;
|
||||
resource_size_t mem_size;
|
||||
int err, irq;
|
||||
u32 clock_freq = 0;
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
if (IS_ERR(pinctrl))
|
||||
return PTR_ERR(pinctrl);
|
||||
|
||||
if (pdev->dev.of_node) {
|
||||
const u32 *clock_freq_p;
|
||||
|
||||
|
||||
@ -48,6 +48,7 @@
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <linux/of_net.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
@ -1543,6 +1544,7 @@ fec_probe(struct platform_device *pdev)
|
||||
struct resource *r;
|
||||
const struct of_device_id *of_id;
|
||||
static int dev_id;
|
||||
struct pinctrl *pinctrl;
|
||||
|
||||
of_id = of_match_device(fec_dt_ids, &pdev->dev);
|
||||
if (of_id)
|
||||
@ -1610,6 +1612,12 @@ fec_probe(struct platform_device *pdev)
|
||||
}
|
||||
}
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
||||
if (IS_ERR(pinctrl)) {
|
||||
ret = PTR_ERR(pinctrl);
|
||||
goto failed_pin;
|
||||
}
|
||||
|
||||
fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
|
||||
if (IS_ERR(fep->clk_ipg)) {
|
||||
ret = PTR_ERR(fep->clk_ipg);
|
||||
@ -1648,6 +1656,7 @@ failed_mii_init:
|
||||
failed_init:
|
||||
clk_disable_unprepare(fep->clk_ahb);
|
||||
clk_disable_unprepare(fep->clk_ipg);
|
||||
failed_pin:
|
||||
failed_clk:
|
||||
for (i = 0; i < FEC_IRQ_NUM; i++) {
|
||||
irq = platform_get_irq(pdev, i);
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
@ -1260,3 +1260,44 @@ int of_alias_get_id(struct device_node *np, const char *stem)
|
||||
return id;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_alias_get_id);
|
||||
|
||||
const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur,
|
||||
u32 *pu)
|
||||
{
|
||||
const void *curv = cur;
|
||||
|
||||
if (!prop)
|
||||
return NULL;
|
||||
|
||||
if (!cur) {
|
||||
curv = prop->value;
|
||||
goto out_val;
|
||||
}
|
||||
|
||||
curv += sizeof(*cur);
|
||||
if (curv >= prop->value + prop->length)
|
||||
return NULL;
|
||||
|
||||
out_val:
|
||||
*pu = be32_to_cpup(curv);
|
||||
return curv;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_prop_next_u32);
|
||||
|
||||
const char *of_prop_next_string(struct property *prop, const char *cur)
|
||||
{
|
||||
const void *curv = cur;
|
||||
|
||||
if (!prop)
|
||||
return NULL;
|
||||
|
||||
if (!cur)
|
||||
return prop->value;
|
||||
|
||||
curv += strlen(cur) + 1;
|
||||
if (curv >= prop->value + prop->length)
|
||||
return NULL;
|
||||
|
||||
return curv;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_prop_next_string);
|
||||
|
||||
@ -4,7 +4,6 @@
|
||||
|
||||
config PINCTRL
|
||||
bool
|
||||
depends on EXPERIMENTAL
|
||||
|
||||
if PINCTRL
|
||||
|
||||
@ -27,6 +26,19 @@ config DEBUG_PINCTRL
|
||||
help
|
||||
Say Y here to add some extra checks and diagnostics to PINCTRL calls.
|
||||
|
||||
config PINCTRL_IMX
|
||||
bool
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
|
||||
config PINCTRL_IMX6Q
|
||||
bool "IMX6Q pinctrl driver"
|
||||
depends on OF
|
||||
depends on SOC_IMX6Q
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx6q pinctrl driver
|
||||
|
||||
config PINCTRL_PXA3xx
|
||||
bool
|
||||
select PINMUX
|
||||
@ -37,6 +49,21 @@ config PINCTRL_MMP2
|
||||
select PINCTRL_PXA3xx
|
||||
select PINCONF
|
||||
|
||||
config PINCTRL_MXS
|
||||
bool
|
||||
|
||||
config PINCTRL_IMX23
|
||||
bool
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select PINCTRL_MXS
|
||||
|
||||
config PINCTRL_IMX28
|
||||
bool
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select PINCTRL_MXS
|
||||
|
||||
config PINCTRL_PXA168
|
||||
bool "PXA168 pin controller driver"
|
||||
depends on ARCH_MMP
|
||||
@ -84,6 +111,8 @@ config PINCTRL_COH901
|
||||
COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
|
||||
ports of 8 GPIO pins each.
|
||||
|
||||
source "drivers/pinctrl/spear/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
||||
|
||||
@ -5,9 +5,17 @@ ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG
|
||||
obj-$(CONFIG_PINCTRL) += core.o
|
||||
obj-$(CONFIG_PINMUX) += pinmux.o
|
||||
obj-$(CONFIG_PINCONF) += pinconf.o
|
||||
ifeq ($(CONFIG_OF),y)
|
||||
obj-$(CONFIG_PINCTRL) += devicetree.o
|
||||
endif
|
||||
obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
|
||||
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
|
||||
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
|
||||
obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o
|
||||
obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
|
||||
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
|
||||
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
|
||||
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
|
||||
obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
|
||||
obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
|
||||
obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o
|
||||
@ -16,3 +24,5 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
|
||||
obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
|
||||
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
|
||||
obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
|
||||
|
||||
obj-$(CONFIG_PLAT_SPEAR) += spear/
|
||||
|
||||
@ -23,9 +23,11 @@
|
||||
#include <linux/sysfs.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include "core.h"
|
||||
#include "devicetree.h"
|
||||
#include "pinmux.h"
|
||||
#include "pinconf.h"
|
||||
|
||||
@ -41,11 +43,13 @@ struct pinctrl_maps {
|
||||
unsigned num_maps;
|
||||
};
|
||||
|
||||
static bool pinctrl_dummy_state;
|
||||
|
||||
/* Mutex taken by all entry points */
|
||||
DEFINE_MUTEX(pinctrl_mutex);
|
||||
|
||||
/* Global list of pin control devices (struct pinctrl_dev) */
|
||||
static LIST_HEAD(pinctrldev_list);
|
||||
LIST_HEAD(pinctrldev_list);
|
||||
|
||||
/* List of pin controller handles (struct pinctrl) */
|
||||
static LIST_HEAD(pinctrl_list);
|
||||
@ -59,6 +63,19 @@ static LIST_HEAD(pinctrl_maps);
|
||||
_i_ < _maps_node_->num_maps; \
|
||||
i++, _map_ = &_maps_node_->maps[_i_])
|
||||
|
||||
/**
|
||||
* pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
|
||||
*
|
||||
* Usually this function is called by platforms without pinctrl driver support
|
||||
* but run with some shared drivers using pinctrl APIs.
|
||||
* After calling this function, the pinctrl core will return successfully
|
||||
* with creating a dummy state for the driver to keep going smoothly.
|
||||
*/
|
||||
void pinctrl_provide_dummies(void)
|
||||
{
|
||||
pinctrl_dummy_state = true;
|
||||
}
|
||||
|
||||
const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
/* We're not allowed to register devices without name */
|
||||
@ -123,6 +140,25 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/**
|
||||
* pin_get_name_from_id() - look up a pin name from a pin id
|
||||
* @pctldev: the pin control device to lookup the pin on
|
||||
* @name: the name of the pin to look up
|
||||
*/
|
||||
const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin)
|
||||
{
|
||||
const struct pin_desc *desc;
|
||||
|
||||
desc = pin_desc_get(pctldev, pin);
|
||||
if (desc == NULL) {
|
||||
dev_err(pctldev->dev, "failed to get pin(%d) name\n",
|
||||
pin);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return desc->name;
|
||||
}
|
||||
|
||||
/**
|
||||
* pin_is_valid() - check if pin exists on controller
|
||||
* @pctldev: the pin control device to check the pin on
|
||||
@ -255,7 +291,8 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
|
||||
*
|
||||
* Find the pin controller handling a certain GPIO pin from the pinspace of
|
||||
* the GPIO subsystem, return the device and the matching GPIO range. Returns
|
||||
* negative if the GPIO range could not be found in any device.
|
||||
* -EPROBE_DEFER if the GPIO range could not be found in any device since it
|
||||
* may still have not been registered.
|
||||
*/
|
||||
static int pinctrl_get_device_gpio_range(unsigned gpio,
|
||||
struct pinctrl_dev **outdev,
|
||||
@ -275,7 +312,7 @@ static int pinctrl_get_device_gpio_range(unsigned gpio,
|
||||
}
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -318,9 +355,10 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
|
||||
const char *pin_group)
|
||||
{
|
||||
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
|
||||
unsigned ngroups = pctlops->get_groups_count(pctldev);
|
||||
unsigned group_selector = 0;
|
||||
|
||||
while (pctlops->list_groups(pctldev, group_selector) >= 0) {
|
||||
while (group_selector < ngroups) {
|
||||
const char *gname = pctlops->get_group_name(pctldev,
|
||||
group_selector);
|
||||
if (!strcmp(gname, pin_group)) {
|
||||
@ -360,7 +398,7 @@ int pinctrl_request_gpio(unsigned gpio)
|
||||
ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
|
||||
if (ret) {
|
||||
mutex_unlock(&pinctrl_mutex);
|
||||
return -EINVAL;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Convert to the pin controllers number space */
|
||||
@ -516,11 +554,14 @@ static int add_setting(struct pinctrl *p, struct pinctrl_map const *map)
|
||||
|
||||
setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
|
||||
if (setting->pctldev == NULL) {
|
||||
dev_err(p->dev, "unknown pinctrl device %s in map entry",
|
||||
dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe",
|
||||
map->ctrl_dev_name);
|
||||
kfree(setting);
|
||||
/* Eventually, this should trigger deferred probe */
|
||||
return -ENODEV;
|
||||
/*
|
||||
* OK let us guess that the driver is not there yet, and
|
||||
* let's defer obtaining this pinctrl handle to later...
|
||||
*/
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
|
||||
switch (map->type) {
|
||||
@ -579,6 +620,13 @@ static struct pinctrl *create_pinctrl(struct device *dev)
|
||||
}
|
||||
p->dev = dev;
|
||||
INIT_LIST_HEAD(&p->states);
|
||||
INIT_LIST_HEAD(&p->dt_maps);
|
||||
|
||||
ret = pinctrl_dt_to_map(p);
|
||||
if (ret < 0) {
|
||||
kfree(p);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
devname = dev_name(dev);
|
||||
|
||||
@ -662,6 +710,8 @@ static void pinctrl_put_locked(struct pinctrl *p, bool inlist)
|
||||
kfree(state);
|
||||
}
|
||||
|
||||
pinctrl_dt_free_maps(p);
|
||||
|
||||
if (inlist)
|
||||
list_del(&p->node);
|
||||
kfree(p);
|
||||
@ -685,8 +735,18 @@ static struct pinctrl_state *pinctrl_lookup_state_locked(struct pinctrl *p,
|
||||
struct pinctrl_state *state;
|
||||
|
||||
state = find_state(p, name);
|
||||
if (!state)
|
||||
return ERR_PTR(-ENODEV);
|
||||
if (!state) {
|
||||
if (pinctrl_dummy_state) {
|
||||
/* create dummy state */
|
||||
dev_dbg(p->dev, "using pinctrl dummy state (%s)\n",
|
||||
name);
|
||||
state = create_state(p, name);
|
||||
if (IS_ERR(state))
|
||||
return state;
|
||||
} else {
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
}
|
||||
|
||||
return state;
|
||||
}
|
||||
@ -787,15 +847,63 @@ int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pinctrl_select_state);
|
||||
|
||||
static void devm_pinctrl_release(struct device *dev, void *res)
|
||||
{
|
||||
pinctrl_put(*(struct pinctrl **)res);
|
||||
}
|
||||
|
||||
/**
|
||||
* pinctrl_register_mappings() - register a set of pin controller mappings
|
||||
* @maps: the pincontrol mappings table to register. This should probably be
|
||||
* marked with __initdata so it can be discarded after boot. This
|
||||
* function will perform a shallow copy for the mapping entries.
|
||||
* @num_maps: the number of maps in the mapping table
|
||||
* struct devm_pinctrl_get() - Resource managed pinctrl_get()
|
||||
* @dev: the device to obtain the handle for
|
||||
*
|
||||
* If there is a need to explicitly destroy the returned struct pinctrl,
|
||||
* devm_pinctrl_put() should be used, rather than plain pinctrl_put().
|
||||
*/
|
||||
int pinctrl_register_mappings(struct pinctrl_map const *maps,
|
||||
unsigned num_maps)
|
||||
struct pinctrl *devm_pinctrl_get(struct device *dev)
|
||||
{
|
||||
struct pinctrl **ptr, *p;
|
||||
|
||||
ptr = devres_alloc(devm_pinctrl_release, sizeof(*ptr), GFP_KERNEL);
|
||||
if (!ptr)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
p = pinctrl_get(dev);
|
||||
if (!IS_ERR(p)) {
|
||||
*ptr = p;
|
||||
devres_add(dev, ptr);
|
||||
} else {
|
||||
devres_free(ptr);
|
||||
}
|
||||
|
||||
return p;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(devm_pinctrl_get);
|
||||
|
||||
static int devm_pinctrl_match(struct device *dev, void *res, void *data)
|
||||
{
|
||||
struct pinctrl **p = res;
|
||||
|
||||
return *p == data;
|
||||
}
|
||||
|
||||
/**
|
||||
* devm_pinctrl_put() - Resource managed pinctrl_put()
|
||||
* @p: the pinctrl handle to release
|
||||
*
|
||||
* Deallocate a struct pinctrl obtained via devm_pinctrl_get(). Normally
|
||||
* this function will not need to be called and the resource management
|
||||
* code will ensure that the resource is freed.
|
||||
*/
|
||||
void devm_pinctrl_put(struct pinctrl *p)
|
||||
{
|
||||
WARN_ON(devres_destroy(p->dev, devm_pinctrl_release,
|
||||
devm_pinctrl_match, p));
|
||||
pinctrl_put(p);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(devm_pinctrl_put);
|
||||
|
||||
int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
|
||||
bool dup, bool locked)
|
||||
{
|
||||
int i, ret;
|
||||
struct pinctrl_maps *maps_node;
|
||||
@ -829,13 +937,13 @@ int pinctrl_register_mappings(struct pinctrl_map const *maps,
|
||||
case PIN_MAP_TYPE_MUX_GROUP:
|
||||
ret = pinmux_validate_map(&maps[i], i);
|
||||
if (ret < 0)
|
||||
return 0;
|
||||
return ret;
|
||||
break;
|
||||
case PIN_MAP_TYPE_CONFIGS_PIN:
|
||||
case PIN_MAP_TYPE_CONFIGS_GROUP:
|
||||
ret = pinconf_validate_map(&maps[i], i);
|
||||
if (ret < 0)
|
||||
return 0;
|
||||
return ret;
|
||||
break;
|
||||
default:
|
||||
pr_err("failed to register map %s (%d): invalid type given\n",
|
||||
@ -851,20 +959,52 @@ int pinctrl_register_mappings(struct pinctrl_map const *maps,
|
||||
}
|
||||
|
||||
maps_node->num_maps = num_maps;
|
||||
maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps, GFP_KERNEL);
|
||||
if (!maps_node->maps) {
|
||||
pr_err("failed to duplicate mapping table\n");
|
||||
kfree(maps_node);
|
||||
return -ENOMEM;
|
||||
if (dup) {
|
||||
maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps,
|
||||
GFP_KERNEL);
|
||||
if (!maps_node->maps) {
|
||||
pr_err("failed to duplicate mapping table\n");
|
||||
kfree(maps_node);
|
||||
return -ENOMEM;
|
||||
}
|
||||
} else {
|
||||
maps_node->maps = maps;
|
||||
}
|
||||
|
||||
mutex_lock(&pinctrl_mutex);
|
||||
if (!locked)
|
||||
mutex_lock(&pinctrl_mutex);
|
||||
list_add_tail(&maps_node->node, &pinctrl_maps);
|
||||
mutex_unlock(&pinctrl_mutex);
|
||||
if (!locked)
|
||||
mutex_unlock(&pinctrl_mutex);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* pinctrl_register_mappings() - register a set of pin controller mappings
|
||||
* @maps: the pincontrol mappings table to register. This should probably be
|
||||
* marked with __initdata so it can be discarded after boot. This
|
||||
* function will perform a shallow copy for the mapping entries.
|
||||
* @num_maps: the number of maps in the mapping table
|
||||
*/
|
||||
int pinctrl_register_mappings(struct pinctrl_map const *maps,
|
||||
unsigned num_maps)
|
||||
{
|
||||
return pinctrl_register_map(maps, num_maps, true, false);
|
||||
}
|
||||
|
||||
void pinctrl_unregister_map(struct pinctrl_map const *map)
|
||||
{
|
||||
struct pinctrl_maps *maps_node;
|
||||
|
||||
list_for_each_entry(maps_node, &pinctrl_maps, node) {
|
||||
if (maps_node->maps == map) {
|
||||
list_del(&maps_node->node);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
||||
static int pinctrl_pins_show(struct seq_file *s, void *what)
|
||||
@ -906,15 +1046,17 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
|
||||
{
|
||||
struct pinctrl_dev *pctldev = s->private;
|
||||
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
|
||||
unsigned selector = 0;
|
||||
unsigned ngroups, selector = 0;
|
||||
|
||||
ngroups = ops->get_groups_count(pctldev);
|
||||
mutex_lock(&pinctrl_mutex);
|
||||
|
||||
seq_puts(s, "registered pin groups:\n");
|
||||
while (ops->list_groups(pctldev, selector) >= 0) {
|
||||
while (selector < ngroups) {
|
||||
const unsigned *pins;
|
||||
unsigned num_pins;
|
||||
const char *gname = ops->get_group_name(pctldev, selector);
|
||||
const char *pname;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
@ -924,10 +1066,14 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
|
||||
seq_printf(s, "%s [ERROR GETTING PINS]\n",
|
||||
gname);
|
||||
else {
|
||||
seq_printf(s, "group: %s, pins = [ ", gname);
|
||||
for (i = 0; i < num_pins; i++)
|
||||
seq_printf(s, "%d ", pins[i]);
|
||||
seq_puts(s, "]\n");
|
||||
seq_printf(s, "group: %s\n", gname);
|
||||
for (i = 0; i < num_pins; i++) {
|
||||
pname = pin_get_name(pctldev, pins[i]);
|
||||
if (WARN_ON(!pname))
|
||||
return -EINVAL;
|
||||
seq_printf(s, "pin %d (%s)\n", pins[i], pname);
|
||||
}
|
||||
seq_puts(s, "\n");
|
||||
}
|
||||
selector++;
|
||||
}
|
||||
@ -1226,11 +1372,14 @@ static int pinctrl_check_ops(struct pinctrl_dev *pctldev)
|
||||
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
|
||||
|
||||
if (!ops ||
|
||||
!ops->list_groups ||
|
||||
!ops->get_groups_count ||
|
||||
!ops->get_group_name ||
|
||||
!ops->get_group_pins)
|
||||
return -EINVAL;
|
||||
|
||||
if (ops->dt_node_to_map && !ops->dt_free_map)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1268,37 +1417,29 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
|
||||
/* check core ops for sanity */
|
||||
ret = pinctrl_check_ops(pctldev);
|
||||
if (ret) {
|
||||
pr_err("%s pinctrl ops lacks necessary functions\n",
|
||||
pctldesc->name);
|
||||
dev_err(dev, "pinctrl ops lacks necessary functions\n");
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
/* If we're implementing pinmuxing, check the ops for sanity */
|
||||
if (pctldesc->pmxops) {
|
||||
ret = pinmux_check_ops(pctldev);
|
||||
if (ret) {
|
||||
pr_err("%s pinmux ops lacks necessary functions\n",
|
||||
pctldesc->name);
|
||||
if (ret)
|
||||
goto out_err;
|
||||
}
|
||||
}
|
||||
|
||||
/* If we're implementing pinconfig, check the ops for sanity */
|
||||
if (pctldesc->confops) {
|
||||
ret = pinconf_check_ops(pctldev);
|
||||
if (ret) {
|
||||
pr_err("%s pin config ops lacks necessary functions\n",
|
||||
pctldesc->name);
|
||||
if (ret)
|
||||
goto out_err;
|
||||
}
|
||||
}
|
||||
|
||||
/* Register all the pins */
|
||||
pr_debug("try to register %d pins on %s...\n",
|
||||
pctldesc->npins, pctldesc->name);
|
||||
dev_dbg(dev, "try to register %d pins ...\n", pctldesc->npins);
|
||||
ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins);
|
||||
if (ret) {
|
||||
pr_err("error during pin registration\n");
|
||||
dev_err(dev, "error during pin registration\n");
|
||||
pinctrl_free_pindescs(pctldev, pctldesc->pins,
|
||||
pctldesc->npins);
|
||||
goto out_err;
|
||||
@ -1313,8 +1454,15 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
|
||||
struct pinctrl_state *s =
|
||||
pinctrl_lookup_state_locked(pctldev->p,
|
||||
PINCTRL_STATE_DEFAULT);
|
||||
if (!IS_ERR(s))
|
||||
pinctrl_select_state_locked(pctldev->p, s);
|
||||
if (IS_ERR(s)) {
|
||||
dev_dbg(dev, "failed to lookup the default state\n");
|
||||
} else {
|
||||
ret = pinctrl_select_state_locked(pctldev->p, s);
|
||||
if (ret) {
|
||||
dev_err(dev,
|
||||
"failed to select default state\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
mutex_unlock(&pinctrl_mutex);
|
||||
|
||||
@ -52,12 +52,15 @@ struct pinctrl_dev {
|
||||
* @dev: the device using this pin control handle
|
||||
* @states: a list of states for this device
|
||||
* @state: the current state
|
||||
* @dt_maps: the mapping table chunks dynamically parsed from device tree for
|
||||
* this device, if any
|
||||
*/
|
||||
struct pinctrl {
|
||||
struct list_head node;
|
||||
struct device *dev;
|
||||
struct list_head states;
|
||||
struct pinctrl_state *state;
|
||||
struct list_head dt_maps;
|
||||
};
|
||||
|
||||
/**
|
||||
@ -100,7 +103,8 @@ struct pinctrl_setting_configs {
|
||||
* struct pinctrl_setting - an individual mux or config setting
|
||||
* @node: list node for struct pinctrl_settings's @settings field
|
||||
* @type: the type of setting
|
||||
* @pctldev: pin control device handling to be programmed
|
||||
* @pctldev: pin control device handling to be programmed. Not used for
|
||||
* PIN_MAP_TYPE_DUMMY_STATE.
|
||||
* @data: Data specific to the setting type
|
||||
*/
|
||||
struct pinctrl_setting {
|
||||
@ -144,6 +148,7 @@ struct pin_desc {
|
||||
|
||||
struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
|
||||
int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
|
||||
const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
|
||||
int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
|
||||
const char *pin_group);
|
||||
|
||||
@ -153,4 +158,9 @@ static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev,
|
||||
return radix_tree_lookup(&pctldev->pin_desc_tree, pin);
|
||||
}
|
||||
|
||||
int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
|
||||
bool dup, bool locked);
|
||||
void pinctrl_unregister_map(struct pinctrl_map const *map);
|
||||
|
||||
extern struct mutex pinctrl_mutex;
|
||||
extern struct list_head pinctrldev_list;
|
||||
|
||||
249
drivers/pinctrl/devicetree.c
Normal file
249
drivers/pinctrl/devicetree.c
Normal file
@ -0,0 +1,249 @@
|
||||
/*
|
||||
* Device tree integration for the pin control subsystem
|
||||
*
|
||||
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "devicetree.h"
|
||||
|
||||
/**
|
||||
* struct pinctrl_dt_map - mapping table chunk parsed from device tree
|
||||
* @node: list node for struct pinctrl's @dt_maps field
|
||||
* @pctldev: the pin controller that allocated this struct, and will free it
|
||||
* @maps: the mapping table entries
|
||||
*/
|
||||
struct pinctrl_dt_map {
|
||||
struct list_head node;
|
||||
struct pinctrl_dev *pctldev;
|
||||
struct pinctrl_map *map;
|
||||
unsigned num_maps;
|
||||
};
|
||||
|
||||
static void dt_free_map(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_map *map, unsigned num_maps)
|
||||
{
|
||||
if (pctldev) {
|
||||
struct pinctrl_ops *ops = pctldev->desc->pctlops;
|
||||
ops->dt_free_map(pctldev, map, num_maps);
|
||||
} else {
|
||||
/* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
|
||||
kfree(map);
|
||||
}
|
||||
}
|
||||
|
||||
void pinctrl_dt_free_maps(struct pinctrl *p)
|
||||
{
|
||||
struct pinctrl_dt_map *dt_map, *n1;
|
||||
|
||||
list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) {
|
||||
pinctrl_unregister_map(dt_map->map);
|
||||
list_del(&dt_map->node);
|
||||
dt_free_map(dt_map->pctldev, dt_map->map,
|
||||
dt_map->num_maps);
|
||||
kfree(dt_map);
|
||||
}
|
||||
|
||||
of_node_put(p->dev->of_node);
|
||||
}
|
||||
|
||||
static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
|
||||
struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_map *map, unsigned num_maps)
|
||||
{
|
||||
int i;
|
||||
struct pinctrl_dt_map *dt_map;
|
||||
|
||||
/* Initialize common mapping table entry fields */
|
||||
for (i = 0; i < num_maps; i++) {
|
||||
map[i].dev_name = dev_name(p->dev);
|
||||
map[i].name = statename;
|
||||
if (pctldev)
|
||||
map[i].ctrl_dev_name = dev_name(pctldev->dev);
|
||||
}
|
||||
|
||||
/* Remember the converted mapping table entries */
|
||||
dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL);
|
||||
if (!dt_map) {
|
||||
dev_err(p->dev, "failed to alloc struct pinctrl_dt_map\n");
|
||||
dt_free_map(pctldev, map, num_maps);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dt_map->pctldev = pctldev;
|
||||
dt_map->map = map;
|
||||
dt_map->num_maps = num_maps;
|
||||
list_add_tail(&dt_map->node, &p->dt_maps);
|
||||
|
||||
return pinctrl_register_map(map, num_maps, false, true);
|
||||
}
|
||||
|
||||
static struct pinctrl_dev *find_pinctrl_by_of_node(struct device_node *np)
|
||||
{
|
||||
struct pinctrl_dev *pctldev;
|
||||
|
||||
list_for_each_entry(pctldev, &pinctrldev_list, node)
|
||||
if (pctldev->dev->of_node == np)
|
||||
return pctldev;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
|
||||
struct device_node *np_config)
|
||||
{
|
||||
struct device_node *np_pctldev;
|
||||
struct pinctrl_dev *pctldev;
|
||||
struct pinctrl_ops *ops;
|
||||
int ret;
|
||||
struct pinctrl_map *map;
|
||||
unsigned num_maps;
|
||||
|
||||
/* Find the pin controller containing np_config */
|
||||
np_pctldev = of_node_get(np_config);
|
||||
for (;;) {
|
||||
np_pctldev = of_get_next_parent(np_pctldev);
|
||||
if (!np_pctldev || of_node_is_root(np_pctldev)) {
|
||||
dev_info(p->dev, "could not find pctldev for node %s, deferring probe\n",
|
||||
np_config->full_name);
|
||||
of_node_put(np_pctldev);
|
||||
/* OK let's just assume this will appear later then */
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
pctldev = find_pinctrl_by_of_node(np_pctldev);
|
||||
if (pctldev)
|
||||
break;
|
||||
}
|
||||
of_node_put(np_pctldev);
|
||||
|
||||
/*
|
||||
* Call pinctrl driver to parse device tree node, and
|
||||
* generate mapping table entries
|
||||
*/
|
||||
ops = pctldev->desc->pctlops;
|
||||
if (!ops->dt_node_to_map) {
|
||||
dev_err(p->dev, "pctldev %s doesn't support DT\n",
|
||||
dev_name(pctldev->dev));
|
||||
return -ENODEV;
|
||||
}
|
||||
ret = ops->dt_node_to_map(pctldev, np_config, &map, &num_maps);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Stash the mapping table chunk away for later use */
|
||||
return dt_remember_or_free_map(p, statename, pctldev, map, num_maps);
|
||||
}
|
||||
|
||||
static int dt_remember_dummy_state(struct pinctrl *p, const char *statename)
|
||||
{
|
||||
struct pinctrl_map *map;
|
||||
|
||||
map = kzalloc(sizeof(*map), GFP_KERNEL);
|
||||
if (!map) {
|
||||
dev_err(p->dev, "failed to alloc struct pinctrl_map\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
|
||||
map->type = PIN_MAP_TYPE_DUMMY_STATE;
|
||||
|
||||
return dt_remember_or_free_map(p, statename, NULL, map, 1);
|
||||
}
|
||||
|
||||
int pinctrl_dt_to_map(struct pinctrl *p)
|
||||
{
|
||||
struct device_node *np = p->dev->of_node;
|
||||
int state, ret;
|
||||
char *propname;
|
||||
struct property *prop;
|
||||
const char *statename;
|
||||
const __be32 *list;
|
||||
int size, config;
|
||||
phandle phandle;
|
||||
struct device_node *np_config;
|
||||
|
||||
/* CONFIG_OF enabled, p->dev not instantiated from DT */
|
||||
if (!np) {
|
||||
dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* We may store pointers to property names within the node */
|
||||
of_node_get(np);
|
||||
|
||||
/* For each defined state ID */
|
||||
for (state = 0; ; state++) {
|
||||
/* Retrieve the pinctrl-* property */
|
||||
propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state);
|
||||
prop = of_find_property(np, propname, &size);
|
||||
kfree(propname);
|
||||
if (!prop)
|
||||
break;
|
||||
list = prop->value;
|
||||
size /= sizeof(*list);
|
||||
|
||||
/* Determine whether pinctrl-names property names the state */
|
||||
ret = of_property_read_string_index(np, "pinctrl-names",
|
||||
state, &statename);
|
||||
/*
|
||||
* If not, statename is just the integer state ID. But rather
|
||||
* than dynamically allocate it and have to free it later,
|
||||
* just point part way into the property name for the string.
|
||||
*/
|
||||
if (ret < 0) {
|
||||
/* strlen("pinctrl-") == 8 */
|
||||
statename = prop->name + 8;
|
||||
}
|
||||
|
||||
/* For every referenced pin configuration node in it */
|
||||
for (config = 0; config < size; config++) {
|
||||
phandle = be32_to_cpup(list++);
|
||||
|
||||
/* Look up the pin configuration node */
|
||||
np_config = of_find_node_by_phandle(phandle);
|
||||
if (!np_config) {
|
||||
dev_err(p->dev,
|
||||
"prop %s index %i invalid phandle\n",
|
||||
prop->name, config);
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Parse the node */
|
||||
ret = dt_to_map_one_config(p, statename, np_config);
|
||||
of_node_put(np_config);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* No entries in DT? Generate a dummy state table entry */
|
||||
if (!size) {
|
||||
ret = dt_remember_dummy_state(p, statename);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
pinctrl_dt_free_maps(p);
|
||||
return ret;
|
||||
}
|
||||
35
drivers/pinctrl/devicetree.h
Normal file
35
drivers/pinctrl/devicetree.h
Normal file
@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Internal interface to pinctrl device tree integration
|
||||
*
|
||||
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
|
||||
void pinctrl_dt_free_maps(struct pinctrl *p);
|
||||
int pinctrl_dt_to_map(struct pinctrl *p);
|
||||
|
||||
#else
|
||||
|
||||
static inline int pinctrl_dt_to_map(struct pinctrl *p)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void pinctrl_dt_free_maps(struct pinctrl *p)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -28,11 +28,17 @@ int pinconf_check_ops(struct pinctrl_dev *pctldev)
|
||||
const struct pinconf_ops *ops = pctldev->desc->confops;
|
||||
|
||||
/* We must be able to read out pin status */
|
||||
if (!ops->pin_config_get && !ops->pin_config_group_get)
|
||||
if (!ops->pin_config_get && !ops->pin_config_group_get) {
|
||||
dev_err(pctldev->dev,
|
||||
"pinconf must be able to read out pin status\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
/* We have to be able to config the pins in SOME way */
|
||||
if (!ops->pin_config_set && !ops->pin_config_group_set)
|
||||
if (!ops->pin_config_set && !ops->pin_config_group_set) {
|
||||
dev_err(pctldev->dev,
|
||||
"pinconf has to be able to set a pins config\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -379,8 +385,16 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting)
|
||||
|
||||
void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
|
||||
{
|
||||
struct pinctrl_dev *pctldev;
|
||||
const struct pinconf_ops *confops;
|
||||
int i;
|
||||
|
||||
pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
|
||||
if (pctldev)
|
||||
confops = pctldev->desc->confops;
|
||||
else
|
||||
confops = NULL;
|
||||
|
||||
switch (map->type) {
|
||||
case PIN_MAP_TYPE_CONFIGS_PIN:
|
||||
seq_printf(s, "pin ");
|
||||
@ -394,8 +408,15 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
|
||||
|
||||
seq_printf(s, "%s\n", map->data.configs.group_or_pin);
|
||||
|
||||
for (i = 0; i < map->data.configs.num_configs; i++)
|
||||
seq_printf(s, "config %08lx\n", map->data.configs.configs[i]);
|
||||
for (i = 0; i < map->data.configs.num_configs; i++) {
|
||||
seq_printf(s, "config ");
|
||||
if (confops && confops->pin_config_config_dbg_show)
|
||||
confops->pin_config_config_dbg_show(pctldev, s,
|
||||
map->data.configs.configs[i]);
|
||||
else
|
||||
seq_printf(s, "%08lx", map->data.configs.configs[i]);
|
||||
seq_printf(s, "\n");
|
||||
}
|
||||
}
|
||||
|
||||
void pinconf_show_setting(struct seq_file *s,
|
||||
@ -403,6 +424,7 @@ void pinconf_show_setting(struct seq_file *s,
|
||||
{
|
||||
struct pinctrl_dev *pctldev = setting->pctldev;
|
||||
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
|
||||
const struct pinconf_ops *confops = pctldev->desc->confops;
|
||||
struct pin_desc *desc;
|
||||
int i;
|
||||
|
||||
@ -428,8 +450,15 @@ void pinconf_show_setting(struct seq_file *s,
|
||||
* FIXME: We should really get the pin controler to dump the config
|
||||
* values, so they can be decoded to something meaningful.
|
||||
*/
|
||||
for (i = 0; i < setting->data.configs.num_configs; i++)
|
||||
seq_printf(s, " %08lx", setting->data.configs.configs[i]);
|
||||
for (i = 0; i < setting->data.configs.num_configs; i++) {
|
||||
seq_printf(s, " ");
|
||||
if (confops && confops->pin_config_config_dbg_show)
|
||||
confops->pin_config_config_dbg_show(pctldev, s,
|
||||
setting->data.configs.configs[i]);
|
||||
else
|
||||
seq_printf(s, "%08lx",
|
||||
setting->data.configs.configs[i]);
|
||||
}
|
||||
|
||||
seq_printf(s, "\n");
|
||||
}
|
||||
@ -448,10 +477,14 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev,
|
||||
static int pinconf_pins_show(struct seq_file *s, void *what)
|
||||
{
|
||||
struct pinctrl_dev *pctldev = s->private;
|
||||
const struct pinconf_ops *ops = pctldev->desc->confops;
|
||||
unsigned i, pin;
|
||||
|
||||
if (!ops || !ops->pin_config_get)
|
||||
return 0;
|
||||
|
||||
seq_puts(s, "Pin config settings per pin\n");
|
||||
seq_puts(s, "Format: pin (name): pinmux setting array\n");
|
||||
seq_puts(s, "Format: pin (name): configs\n");
|
||||
|
||||
mutex_lock(&pinctrl_mutex);
|
||||
|
||||
@ -495,17 +528,18 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
|
||||
struct pinctrl_dev *pctldev = s->private;
|
||||
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
|
||||
const struct pinconf_ops *ops = pctldev->desc->confops;
|
||||
unsigned ngroups = pctlops->get_groups_count(pctldev);
|
||||
unsigned selector = 0;
|
||||
|
||||
if (!ops || !ops->pin_config_group_get)
|
||||
return 0;
|
||||
|
||||
seq_puts(s, "Pin config settings per pin group\n");
|
||||
seq_puts(s, "Format: group (name): pinmux setting array\n");
|
||||
seq_puts(s, "Format: group (name): configs\n");
|
||||
|
||||
mutex_lock(&pinctrl_mutex);
|
||||
|
||||
while (pctlops->list_groups(pctldev, selector) >= 0) {
|
||||
while (selector < ngroups) {
|
||||
const char *gname = pctlops->get_group_name(pctldev, selector);
|
||||
|
||||
seq_printf(s, "%u (%s):", selector, gname);
|
||||
|
||||
@ -19,11 +19,6 @@ int pinconf_map_to_setting(struct pinctrl_map const *map,
|
||||
struct pinctrl_setting *setting);
|
||||
void pinconf_free_setting(struct pinctrl_setting const *setting);
|
||||
int pinconf_apply_setting(struct pinctrl_setting const *setting);
|
||||
void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
|
||||
void pinconf_show_setting(struct seq_file *s,
|
||||
struct pinctrl_setting const *setting);
|
||||
void pinconf_init_device_debugfs(struct dentry *devroot,
|
||||
struct pinctrl_dev *pctldev);
|
||||
|
||||
/*
|
||||
* You will only be interested in these if you're using PINCONF
|
||||
@ -61,6 +56,18 @@ static inline int pinconf_apply_setting(struct pinctrl_setting const *setting)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PINCONF) && defined(CONFIG_DEBUG_FS)
|
||||
|
||||
void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
|
||||
void pinconf_show_setting(struct seq_file *s,
|
||||
struct pinctrl_setting const *setting);
|
||||
void pinconf_init_device_debugfs(struct dentry *devroot,
|
||||
struct pinctrl_dev *pctldev);
|
||||
|
||||
#else
|
||||
|
||||
static inline void pinconf_show_map(struct seq_file *s,
|
||||
struct pinctrl_map const *map)
|
||||
{
|
||||
|
||||
@ -174,7 +174,7 @@ struct u300_gpio_confdata {
|
||||
|
||||
|
||||
/* Initial configuration */
|
||||
static const struct __initdata u300_gpio_confdata
|
||||
static const struct __initconst u300_gpio_confdata
|
||||
bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
|
||||
/* Port 0, pins 0-7 */
|
||||
{
|
||||
@ -255,7 +255,7 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
|
||||
}
|
||||
};
|
||||
|
||||
static const struct __initdata u300_gpio_confdata
|
||||
static const struct __initconst u300_gpio_confdata
|
||||
bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
|
||||
/* Port 0, pins 0-7 */
|
||||
{
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user