forked from Minki/linux
Merge tag 'imx-clk-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next
The i.MX clock updates for 4.5: - Add is_prepared function callback for pllv3 clock driver - Use imx_check_clocks() on imx6ul and imx7d clock drivers to save some code - Add a core clock for imx7d to support generic cpufreq driver - Support imx6q clock routing with OSC to anaclk2/2b - To support more precise pixel clocks on imx5, allow ipu_di_sel clock selectors to influence the PLLs that they are derived from - A cleanup on imx25 OSC clock
This commit is contained in:
Michael Turquette
commit
fcd5ac1a41
@ -96,13 +96,11 @@ static struct clk ** const uart_clks[] __initconst = {
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NULL
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};
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static int __init __mx25_clocks_init(unsigned long osc_rate,
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void __iomem *ccm_base)
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static int __init __mx25_clocks_init(void __iomem *ccm_base)
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{
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BUG_ON(!ccm_base);
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clk[dummy] = imx_clk_fixed("dummy", 0);
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clk[osc] = imx_clk_fixed("osc", osc_rate);
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clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL));
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clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL));
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clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
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@ -250,22 +248,10 @@ static int __init __mx25_clocks_init(unsigned long osc_rate,
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static void __init mx25_clocks_init_dt(struct device_node *np)
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{
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struct device_node *refnp;
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unsigned long osc_rate = 24000000;
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void __iomem *ccm;
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/* retrieve the freqency of fixed clocks from device tree */
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for_each_compatible_node(refnp, NULL, "fixed-clock") {
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u32 rate;
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if (of_property_read_u32(refnp, "clock-frequency", &rate))
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continue;
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if (of_device_is_compatible(refnp, "fsl,imx-osc"))
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osc_rate = rate;
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}
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ccm = of_iomap(np, 0);
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__mx25_clocks_init(osc_rate, ccm);
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__mx25_clocks_init(ccm);
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clk_data.clks = clk;
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clk_data.clk_num = ARRAY_SIZE(clk);
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@ -519,10 +519,10 @@ static void __init mx53_clocks_init(struct device_node *np)
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mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
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clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
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clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
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clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
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mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
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clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
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mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
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clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
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mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT);
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clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
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mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT);
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clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
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mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
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clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
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@ -70,7 +70,8 @@ static const char *cko_sels[] = { "cko1", "cko2", };
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static const char *lvds_sels[] = {
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"dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
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"pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
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"pcie_ref_125m", "sata_ref_100m",
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"pcie_ref_125m", "sata_ref_100m", "usbphy1", "usbphy2",
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"dummy", "dummy", "dummy", "dummy", "osc",
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};
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static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
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static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
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@ -399,9 +399,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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/* mask handshake of mmdc */
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writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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if (IS_ERR(clks[i]))
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pr_err("i.MX6UL clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));
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imx_check_clocks(clks, ARRAY_SIZE(clks));
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clk_data.clks = clks;
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clk_data.clk_num = ARRAY_SIZE(clks);
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@ -833,10 +833,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
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clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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if (IS_ERR(clks[i]))
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pr_err("i.MX7D clk %d: register failed with %ld\n",
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i, PTR_ERR(clks[i]));
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clks[IMX7D_CLK_ARM] = imx_clk_cpu("arm", "arm_a7_root_clk",
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clks[IMX7D_ARM_A7_ROOT_CLK],
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clks[IMX7D_ARM_A7_ROOT_SRC],
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clks[IMX7D_PLL_ARM_MAIN_CLK],
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clks[IMX7D_PLL_SYS_MAIN_CLK]);
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imx_check_clocks(clks, ARRAY_SIZE(clks));
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clk_data.clks = clks;
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clk_data.clk_num = ARRAY_SIZE(clks);
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@ -97,6 +97,16 @@ static void clk_pllv3_unprepare(struct clk_hw *hw)
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writel_relaxed(val, pll->base);
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}
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static int clk_pllv3_is_prepared(struct clk_hw *hw)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(hw);
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if (readl_relaxed(pll->base) & BM_PLL_LOCK)
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return 1;
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return 0;
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}
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static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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@ -139,6 +149,7 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
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static const struct clk_ops clk_pllv3_ops = {
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.prepare = clk_pllv3_prepare,
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.unprepare = clk_pllv3_unprepare,
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.is_prepared = clk_pllv3_is_prepared,
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.recalc_rate = clk_pllv3_recalc_rate,
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.round_rate = clk_pllv3_round_rate,
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.set_rate = clk_pllv3_set_rate,
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@ -193,6 +204,7 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
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static const struct clk_ops clk_pllv3_sys_ops = {
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.prepare = clk_pllv3_prepare,
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.unprepare = clk_pllv3_unprepare,
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.is_prepared = clk_pllv3_is_prepared,
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.recalc_rate = clk_pllv3_sys_recalc_rate,
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.round_rate = clk_pllv3_sys_round_rate,
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.set_rate = clk_pllv3_sys_set_rate,
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@ -265,6 +277,7 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
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static const struct clk_ops clk_pllv3_av_ops = {
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.prepare = clk_pllv3_prepare,
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.unprepare = clk_pllv3_unprepare,
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.is_prepared = clk_pllv3_is_prepared,
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.recalc_rate = clk_pllv3_av_recalc_rate,
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.round_rate = clk_pllv3_av_round_rate,
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.set_rate = clk_pllv3_av_set_rate,
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@ -279,6 +292,7 @@ static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
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static const struct clk_ops clk_pllv3_enet_ops = {
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.prepare = clk_pllv3_prepare,
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.unprepare = clk_pllv3_unprepare,
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.is_prepared = clk_pllv3_is_prepared,
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.recalc_rate = clk_pllv3_enet_recalc_rate,
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};
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@ -447,5 +447,6 @@
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#define IMX7D_SEMA4_HS_ROOT_CLK 434
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#define IMX7D_PLL_DRAM_TEST_DIV 435
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#define IMX7D_ADC_ROOT_CLK 436
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#define IMX7D_CLK_END 437
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#define IMX7D_CLK_ARM 437
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#define IMX7D_CLK_END 438
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#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
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