forked from Minki/linux
ARM: LPC32XX: Misc support functions
Misc support functions and prototypes used in the LPC32XX arch and platforms Signed-off-by: Kevin Wells <wellsk40@gmail.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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Kevin Wells
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271
arch/arm/mach-lpc32xx/common.c
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271
arch/arm/mach-lpc32xx/common.c
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/*
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* arch/arm/mach-lpc32xx/common.c
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*
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* Author: Kevin Wells <kevin.wells@nxp.com>
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*
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* Copyright (C) 2010 NXP Semiconductors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/i2c-pnx.h>
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#include <linux/io.h>
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#include <asm/mach/map.h>
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#include <mach/i2c.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include "common.h"
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/*
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* Watchdog timer
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*/
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static struct resource watchdog_resources[] = {
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[0] = {
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.start = LPC32XX_WDTIM_BASE,
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.end = LPC32XX_WDTIM_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device lpc32xx_watchdog_device = {
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.name = "pnx4008-watchdog",
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.id = -1,
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.num_resources = ARRAY_SIZE(watchdog_resources),
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.resource = watchdog_resources,
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};
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/*
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* I2C busses
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*/
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static struct i2c_pnx_data i2c0_data = {
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.name = I2C_CHIP_NAME "1",
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.base = LPC32XX_I2C1_BASE,
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.irq = IRQ_LPC32XX_I2C_1,
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};
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static struct i2c_pnx_data i2c1_data = {
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.name = I2C_CHIP_NAME "2",
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.base = LPC32XX_I2C2_BASE,
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.irq = IRQ_LPC32XX_I2C_2,
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};
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static struct i2c_pnx_data i2c2_data = {
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.name = "USB-I2C",
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.base = LPC32XX_OTG_I2C_BASE,
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.irq = IRQ_LPC32XX_USB_I2C,
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};
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struct platform_device lpc32xx_i2c0_device = {
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.name = "pnx-i2c",
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.id = 0,
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.dev = {
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.platform_data = &i2c0_data,
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},
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};
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struct platform_device lpc32xx_i2c1_device = {
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.name = "pnx-i2c",
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.id = 1,
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.dev = {
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.platform_data = &i2c1_data,
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},
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};
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struct platform_device lpc32xx_i2c2_device = {
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.name = "pnx-i2c",
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.id = 2,
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.dev = {
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.platform_data = &i2c2_data,
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},
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};
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/*
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* Returns the unique ID for the device
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*/
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void lpc32xx_get_uid(u32 devid[4])
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{
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int i;
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for (i = 0; i < 4; i++)
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devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
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}
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/*
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* Returns SYSCLK source
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* 0 = PLL397, 1 = main oscillator
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*/
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int clk_is_sysclk_mainosc(void)
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{
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if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
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LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
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return 1;
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return 0;
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}
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/*
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* System reset via the watchdog timer
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*/
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void lpc32xx_watchdog_reset(void)
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{
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/* Make sure WDT clocks are enabled */
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__raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
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LPC32XX_CLKPWR_TIMER_CLK_CTRL);
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/* Instant assert of RESETOUT_N with pulse length 1mS */
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__raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
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__raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
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}
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/*
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* Detects and returns IRAM size for the device variation
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*/
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#define LPC32XX_IRAM_BANK_SIZE SZ_128K
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static u32 iram_size;
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u32 lpc32xx_return_iram_size(void)
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{
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if (iram_size == 0) {
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u32 savedval1, savedval2;
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void __iomem *iramptr1, *iramptr2;
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iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
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iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
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savedval1 = __raw_readl(iramptr1);
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savedval2 = __raw_readl(iramptr2);
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if (savedval1 == savedval2) {
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__raw_writel(savedval2 + 1, iramptr2);
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if (__raw_readl(iramptr1) == savedval2 + 1)
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iram_size = LPC32XX_IRAM_BANK_SIZE;
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else
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iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
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__raw_writel(savedval2, iramptr2);
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} else
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iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
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}
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return iram_size;
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}
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/*
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* Computes PLL rate from PLL register and input clock
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*/
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u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
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{
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u32 ilfreq, p, m, n, fcco, fref, cfreq;
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int mode;
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/*
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* PLL requirements
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* ifreq must be >= 1MHz and <= 20MHz
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* FCCO must be >= 156MHz and <= 320MHz
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* FREF must be >= 1MHz and <= 27MHz
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* Assume the passed input data is not valid
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*/
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ilfreq = ifreq;
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m = pllsetup->pll_m;
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n = pllsetup->pll_n;
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p = pllsetup->pll_p;
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mode = (pllsetup->cco_bypass_b15 << 2) |
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(pllsetup->direct_output_b14 << 1) |
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pllsetup->fdbk_div_ctrl_b13;
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switch (mode) {
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case 0x0: /* Non-integer mode */
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cfreq = (m * ilfreq) / (2 * p * n);
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fcco = (m * ilfreq) / n;
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fref = ilfreq / n;
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break;
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case 0x1: /* integer mode */
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cfreq = (m * ilfreq) / n;
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fcco = (m * ilfreq) / (n * 2 * p);
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fref = ilfreq / n;
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break;
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case 0x2:
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case 0x3: /* Direct mode */
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cfreq = (m * ilfreq) / n;
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fcco = cfreq;
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fref = ilfreq / n;
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break;
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case 0x4:
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case 0x5: /* Bypass mode */
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cfreq = ilfreq / (2 * p);
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fcco = 156000000;
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fref = 1000000;
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break;
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case 0x6:
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case 0x7: /* Direct bypass mode */
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default:
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cfreq = ilfreq;
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fcco = 156000000;
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fref = 1000000;
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break;
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}
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if (fcco < 156000000 || fcco > 320000000)
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cfreq = 0;
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if (fref < 1000000 || fref > 27000000)
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cfreq = 0;
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return (u32) cfreq;
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}
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u32 clk_get_pclk_div(void)
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{
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return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
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}
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static struct map_desc lpc32xx_io_desc[] __initdata = {
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{
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.virtual = IO_ADDRESS(LPC32XX_AHB0_START),
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.pfn = __phys_to_pfn(LPC32XX_AHB0_START),
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.length = LPC32XX_AHB0_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = IO_ADDRESS(LPC32XX_AHB1_START),
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.pfn = __phys_to_pfn(LPC32XX_AHB1_START),
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.length = LPC32XX_AHB1_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = IO_ADDRESS(LPC32XX_FABAPB_START),
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.pfn = __phys_to_pfn(LPC32XX_FABAPB_START),
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.length = LPC32XX_FABAPB_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = IO_ADDRESS(LPC32XX_IRAM_BASE),
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.pfn = __phys_to_pfn(LPC32XX_IRAM_BASE),
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.length = (LPC32XX_IRAM_BANK_SIZE * 2),
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.type = MT_DEVICE
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},
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};
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void __init lpc32xx_map_io(void)
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{
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iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
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}
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73
arch/arm/mach-lpc32xx/common.h
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73
arch/arm/mach-lpc32xx/common.h
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@ -0,0 +1,73 @@
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/*
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* arch/arm/mach-lpc32xx/common.h
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*
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* Author: Kevin Wells <kevin.wells@nxp.com>
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*
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* Copyright (C) 2009-2010 NXP Semiconductors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __LPC32XX_COMMON_H
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#define __LPC32XX_COMMON_H
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#include <linux/platform_device.h>
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/*
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* Arch specific platform device structures
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*/
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extern struct platform_device lpc32xx_watchdog_device;
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extern struct platform_device lpc32xx_i2c0_device;
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extern struct platform_device lpc32xx_i2c1_device;
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extern struct platform_device lpc32xx_i2c2_device;
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/*
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* Other arch specific structures and functions
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*/
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extern struct sys_timer lpc32xx_timer;
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extern void __init lpc32xx_init_irq(void);
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extern void __init lpc32xx_map_io(void);
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extern void __init lpc32xx_serial_init(void);
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extern void __init lpc32xx_gpio_init(void);
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/*
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* Structure used for setting up and querying the PLLS
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*/
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struct clk_pll_setup {
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int analog_on;
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int cco_bypass_b15;
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int direct_output_b14;
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int fdbk_div_ctrl_b13;
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int pll_p;
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int pll_n;
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u32 pll_m;
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};
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extern int clk_is_sysclk_mainosc(void);
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extern u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup);
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extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval);
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extern u32 clk_get_pclk_div(void);
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/*
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* Returns the LPC32xx unique 128-bit chip ID
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*/
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extern void lpc32xx_get_uid(u32 devid[4]);
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extern void lpc32xx_watchdog_reset(void);
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extern u32 lpc32xx_return_iram_size(void);
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/*
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* Pointers used for sizing and copying suspend function data
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*/
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extern int lpc32xx_sys_suspend(void);
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extern int lpc32xx_sys_suspend_sz;
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#endif
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