forked from Minki/linux
MXC: i.MX25 timer support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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12b8eb8652
commit
fc2a9f0bc7
@ -47,7 +47,7 @@
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#define MX2_TSTAT_CAPT (1 << 1)
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#define MX2_TSTAT_COMP (1 << 0)
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/* MX31, MX35 */
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/* MX31, MX35, MX25 */
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#define MX3_TCTL_WAITEN (1 << 3)
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#define MX3_TCTL_CLK_IPG (1 << 6)
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#define MX3_TCTL_FRR (1 << 9)
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@ -66,7 +66,7 @@ static inline void gpt_irq_disable(void)
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{
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unsigned int tmp;
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if (cpu_is_mx3())
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if (cpu_is_mx3() || cpu_is_mx25())
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__raw_writel(0, timer_base + MX3_IR);
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else {
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tmp = __raw_readl(timer_base + MXC_TCTL);
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@ -76,7 +76,7 @@ static inline void gpt_irq_disable(void)
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static inline void gpt_irq_enable(void)
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{
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if (cpu_is_mx3())
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if (cpu_is_mx3() || cpu_is_mx25())
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__raw_writel(1<<0, timer_base + MX3_IR);
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else {
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__raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
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@ -90,7 +90,7 @@ static void gpt_irq_acknowledge(void)
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__raw_writel(0, timer_base + MX1_2_TSTAT);
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if (cpu_is_mx2())
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__raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT);
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if (cpu_is_mx3())
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if (cpu_is_mx3() || cpu_is_mx25())
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__raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT);
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}
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@ -117,7 +117,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
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{
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unsigned int c = clk_get_rate(timer_clk);
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if (cpu_is_mx3())
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if (cpu_is_mx3() || cpu_is_mx25())
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clocksource_mxc.read = mx3_get_cycles;
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clocksource_mxc.mult = clocksource_hz2mult(c,
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@ -180,7 +180,7 @@ static void mxc_set_mode(enum clock_event_mode mode,
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if (mode != clockevent_mode) {
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/* Set event time into far-far future */
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if (cpu_is_mx3())
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if (cpu_is_mx3() || cpu_is_mx25())
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__raw_writel(__raw_readl(timer_base + MX3_TCN) - 3,
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timer_base + MX3_TCMP);
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else
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@ -233,7 +233,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
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struct clock_event_device *evt = &clockevent_mxc;
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uint32_t tstat;
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if (cpu_is_mx3())
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if (cpu_is_mx3() || cpu_is_mx25())
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tstat = __raw_readl(timer_base + MX3_TSTAT);
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else
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tstat = __raw_readl(timer_base + MX1_2_TSTAT);
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@ -264,7 +264,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
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{
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unsigned int c = clk_get_rate(timer_clk);
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if (cpu_is_mx3())
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if (cpu_is_mx3() || cpu_is_mx25())
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clockevent_mxc.set_next_event = mx3_set_next_event;
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clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
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@ -296,7 +296,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
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__raw_writel(0, timer_base + MXC_TCTL);
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__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
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if (cpu_is_mx3())
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if (cpu_is_mx3() || cpu_is_mx25())
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tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN;
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else
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tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
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