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ARM: dts: sun8i: Add the H3/H5 CSI controller

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The H3 and H5 features the same CSI controller that was initially found on
the A31.

Add a DT node for it.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
Mylène Josserand 2017-09-18 10:55:28 +02:00 committed by Maxime Ripard
parent 4f16ca40de
commit f89120b6f5
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GPG Key ID: E3EF0D6F671851C5
1 changed files with 22 additions and 0 deletions
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22
arch/arm/boot/dts/sunxi-h3-h5.dtsi
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@ -393,6 +393,13 @@
interrupt-controller; interrupt-controller;
#interrupt-cells = <3>; #interrupt-cells = <3>;
csi_pins: csi {
pins = "PE0", "PE2", "PE3", "PE4", "PE5",
"PE6", "PE7", "PE8", "PE9", "PE10",
"PE11";
function = "csi";
};
emac_rgmii_pins: emac0 { emac_rgmii_pins: emac0 {
pins = "PD0", "PD1", "PD2", "PD3", "PD4", pins = "PD0", "PD1", "PD2", "PD3", "PD4",
"PD5", "PD7", "PD8", "PD9", "PD10", "PD5", "PD7", "PD8", "PD9", "PD10",
@ -744,6 +751,21 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
}; };
csi: camera@1cb0000 {
compatible = "allwinner,sun8i-h3-csi",
"allwinner,sun6i-a31-csi";
reg = <0x01cb0000 0x1000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CSI>,
<&ccu CLK_CSI_SCLK>,
<&ccu CLK_DRAM_CSI>;
clock-names = "bus", "mod", "ram";
resets = <&ccu RST_BUS_CSI>;
pinctrl-names = "default";
pinctrl-0 = <&csi_pins>;
status = "disabled";
};
hdmi: hdmi@1ee0000 { hdmi: hdmi@1ee0000 {
compatible = "allwinner,sun8i-h3-dw-hdmi", compatible = "allwinner,sun8i-h3-dw-hdmi",
"allwinner,sun8i-a83t-dw-hdmi"; "allwinner,sun8i-a83t-dw-hdmi";