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drm/amdgpu: fix S3 failed as RLC safe mode entry stucked in polloing gfx acq

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Fix gfx cgpg setting sequence for RLC deadlock at safe mode entry in polling gfx response.
The patch can fix VCN IB test failed and DAL get dispaly count failed issue.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Prike Liang 2019-10-15 17:11:49 +08:00 committed by Alex Deucher
parent c8486eef2c
commit f839110157
2 changed files with 4 additions and 5 deletions
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5
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View File

@ -4287,9 +4287,6 @@ static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
{
amdgpu_gfx_rlc_enter_safe_mode(adev);
if (is_support_sw_smu(adev) && !enable)
smu_set_gfx_cgpg(&adev->smu, enable);
if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
@ -4566,8 +4563,6 @@ static int gfx_v9_0_set_powergating_state(void *handle,
gfx_v9_0_enable_cp_power_gating(adev, false);
/* update gfx cgpg state */
if (is_support_sw_smu(adev) && enable)
smu_set_gfx_cgpg(&adev->smu, enable);
gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
/* update mgcg state */

4
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
View File

@ -1188,6 +1188,7 @@ static int smu_hw_init(void *handle)
if (adev->flags & AMD_IS_APU) {
smu_powergate_sdma(&adev->smu, false);
smu_powergate_vcn(&adev->smu, false);
smu_set_gfx_cgpg(&adev->smu, true);
}
if (!smu->pm_enabled)
@ -1350,6 +1351,9 @@ static int smu_resume(void *handle)
if (ret)
goto failed;
if (smu->is_apu)
smu_set_gfx_cgpg(&adev->smu, true);
mutex_unlock(&smu->mutex);
pr_info("SMU is resumed successfully!\n");