forked from Minki/linux
ASoC: davinci-mcasp: Change IO functions parameter list
Instead of passing __iomem address (mcasp->base + register_offset) pass the main mcasp structure and only access the mcasp->base in the low level IO functions. In most cases this helps with code readability and it will make it easier to switch over to regmap in the future. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Peter Ujfalusi
Mark Brown
parent
453c499028
commit
f68205a7f8
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@ -71,60 +71,67 @@ struct davinci_mcasp {
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#endif
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};
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static inline void mcasp_set_bits(void __iomem *reg, u32 val)
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static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
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u32 val)
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{
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void __iomem *reg = mcasp->base + offset;
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__raw_writel(__raw_readl(reg) | val, reg);
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}
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static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
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static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
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u32 val)
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{
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void __iomem *reg = mcasp->base + offset;
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__raw_writel((__raw_readl(reg) & ~(val)), reg);
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}
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static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
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static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
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u32 val, u32 mask)
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{
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void __iomem *reg = mcasp->base + offset;
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__raw_writel((__raw_readl(reg) & ~mask) | val, reg);
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}
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static inline void mcasp_set_reg(void __iomem *reg, u32 val)
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static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
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u32 val)
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{
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__raw_writel(val, reg);
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__raw_writel(val, mcasp->base + offset);
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}
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static inline u32 mcasp_get_reg(void __iomem *reg)
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static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
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{
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return (unsigned int)__raw_readl(reg);
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return (u32)__raw_readl(mcasp->base + offset);
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}
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static void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
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static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
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{
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int i = 0;
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mcasp_set_bits(regs, val);
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mcasp_set_bits(mcasp, ctl_reg, val);
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/* programming GBLCTL needs to read back from GBLCTL and verfiy */
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/* loop count is to avoid the lock-up */
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for (i = 0; i < 1000; i++) {
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if ((mcasp_get_reg(regs) & val) == val)
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if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
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break;
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}
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if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
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if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
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printk(KERN_ERR "GBLCTL write error\n");
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}
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static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
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{
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u32 rxfmctl = mcasp_get_reg(mcasp->base + DAVINCI_MCASP_RXFMCTL_REG);
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u32 aclkxctl = mcasp_get_reg(mcasp->base + DAVINCI_MCASP_ACLKXCTL_REG);
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u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
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u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
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return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
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}
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static void mcasp_start_rx(struct davinci_mcasp *mcasp)
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{
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mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
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mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
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/*
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* When ASYNC == 0 the transmit and receive sections operate
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@ -132,25 +139,22 @@ static void mcasp_start_rx(struct davinci_mcasp *mcasp)
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* sure that the TX signlas are enabled when starting reception.
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*/
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if (mcasp_is_synchronous(mcasp)) {
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mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG,
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TXHCLKRST);
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mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG,
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TXCLKRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
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}
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mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
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mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXBUF_REG, 0);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
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mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
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mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
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mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXBUF_REG, 0);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
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mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
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mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
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if (mcasp_is_synchronous(mcasp))
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mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG,
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TXFSRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
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}
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static void mcasp_start_tx(struct davinci_mcasp *mcasp)
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@ -158,14 +162,14 @@ static void mcasp_start_tx(struct davinci_mcasp *mcasp)
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u8 offset = 0, i;
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u32 cnt;
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mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
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mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
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mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
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mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXBUF_REG, 0);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
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mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
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mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
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mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXBUF_REG, 0);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
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for (i = 0; i < mcasp->num_serializer; i++) {
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if (mcasp->serial_dir[i] == TX_MODE) {
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offset = i;
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@ -175,11 +179,11 @@ static void mcasp_start_tx(struct davinci_mcasp *mcasp)
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/* wait for TX ready */
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cnt = 0;
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while (!(mcasp_get_reg(mcasp->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
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while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
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TXSTATE) && (cnt < 100000))
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cnt++;
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mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXBUF_REG, 0);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
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}
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static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
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@ -191,15 +195,15 @@ static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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if (mcasp->txnumevt) { /* enable FIFO */
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reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
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mcasp_clr_bits(mcasp->base + reg, FIFO_ENABLE);
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mcasp_set_bits(mcasp->base + reg, FIFO_ENABLE);
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mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
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mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
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}
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mcasp_start_tx(mcasp);
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} else {
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if (mcasp->rxnumevt) { /* enable FIFO */
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reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
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mcasp_clr_bits(mcasp->base + reg, FIFO_ENABLE);
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mcasp_set_bits(mcasp->base + reg, FIFO_ENABLE);
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mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
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mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
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}
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mcasp_start_rx(mcasp);
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}
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@ -212,10 +216,10 @@ static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
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* running
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*/
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if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
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mcasp_set_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
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mcasp_set_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
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mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
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}
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static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
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@ -229,8 +233,8 @@ static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
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if (mcasp_is_synchronous(mcasp) && mcasp->streams)
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val = TXHCLKRST | TXCLKRST | TXFSRST;
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mcasp_set_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, val);
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mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
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}
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static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
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@ -242,13 +246,13 @@ static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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if (mcasp->txnumevt) { /* disable FIFO */
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reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
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mcasp_clr_bits(mcasp->base + reg, FIFO_ENABLE);
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mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
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}
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mcasp_stop_tx(mcasp);
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} else {
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if (mcasp->rxnumevt) { /* disable FIFO */
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reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
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mcasp_clr_bits(mcasp->base + reg, FIFO_ENABLE);
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mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
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}
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mcasp_stop_rx(mcasp);
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}
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@ -258,62 +262,57 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
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void __iomem *base = mcasp->base;
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_DSP_B:
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case SND_SOC_DAIFMT_AC97:
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mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
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mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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break;
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default:
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/* configure a full-word SYNC pulse (LRCLK) */
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mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
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mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
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mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
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/* make 1st data bit occur one ACLK cycle after the frame sync */
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mcasp_set_bits(base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
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mcasp_set_bits(base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
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mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
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mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
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break;
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}
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* codec is clock and frame slave */
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mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
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mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
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mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
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mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
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mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
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mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
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mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
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ACLKX | ACLKR);
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mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
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AFSX | AFSR);
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mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
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mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
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break;
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case SND_SOC_DAIFMT_CBM_CFS:
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/* codec is clock master and frame slave */
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mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
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mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
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mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
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mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
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mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
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mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
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ACLKX | ACLKR);
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mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
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AFSX | AFSR);
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
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mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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/* codec is clock and frame master */
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mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
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mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
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mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
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mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
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mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
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ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
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ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
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break;
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default:
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@ -322,35 +321,35 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_IB_NF:
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mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
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mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
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mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
|
||||
|
||||
mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
||||
mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
||||
mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
||||
break;
|
||||
|
||||
case SND_SOC_DAIFMT_NB_IF:
|
||||
mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
|
||||
mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
|
||||
|
||||
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
||||
mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
||||
mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
||||
break;
|
||||
|
||||
case SND_SOC_DAIFMT_IB_IF:
|
||||
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
|
||||
mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
|
||||
mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
|
||||
|
||||
mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
||||
mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
||||
break;
|
||||
|
||||
case SND_SOC_DAIFMT_NB_NF:
|
||||
mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
|
||||
mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
|
||||
mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
|
||||
|
||||
mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
||||
mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
||||
mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
@ -366,16 +365,16 @@ static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div
|
|||
|
||||
switch (div_id) {
|
||||
case 0: /* MCLK divider */
|
||||
mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG,
|
||||
mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
|
||||
AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
|
||||
mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_AHCLKRCTL_REG,
|
||||
mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
|
||||
AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
|
||||
break;
|
||||
|
||||
case 1: /* BCLK divider */
|
||||
mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_ACLKXCTL_REG,
|
||||
mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
|
||||
ACLKXDIV(div - 1), ACLKXDIV_MASK);
|
||||
mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_ACLKRCTL_REG,
|
||||
mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
|
||||
ACLKRDIV(div - 1), ACLKRDIV_MASK);
|
||||
break;
|
||||
|
||||
|
|
@ -396,13 +395,13 @@ static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
|
|||
struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
|
||||
|
||||
if (dir == SND_SOC_CLOCK_OUT) {
|
||||
mcasp_set_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
|
||||
mcasp_set_bits(mcasp->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
|
||||
mcasp_set_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
|
||||
} else {
|
||||
mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
|
||||
mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
|
||||
mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
|
||||
mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
|
||||
mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
|
||||
mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -432,19 +431,18 @@ static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
|
|||
fmt = (word_length >> 1) - 1;
|
||||
|
||||
if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
|
||||
mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_RXFMT_REG,
|
||||
RXSSZ(fmt), RXSSZ(0x0F));
|
||||
mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG,
|
||||
TXSSZ(fmt), TXSSZ(0x0F));
|
||||
mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG,
|
||||
TXROT(tx_rotate), TXROT(7));
|
||||
mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_RXFMT_REG,
|
||||
RXROT(rx_rotate), RXROT(7));
|
||||
mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXMASK_REG,
|
||||
mask);
|
||||
mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
|
||||
RXSSZ(0x0F));
|
||||
mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
|
||||
TXSSZ(0x0F));
|
||||
mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
|
||||
TXROT(7));
|
||||
mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
|
||||
RXROT(7));
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
|
||||
}
|
||||
|
||||
mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXMASK_REG, mask);
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -461,38 +459,33 @@ static int davinci_hw_common_param(struct davinci_mcasp *mcasp, int stream,
|
|||
u32 reg;
|
||||
/* Default configuration */
|
||||
if (mcasp->version != MCASP_VERSION_4)
|
||||
mcasp_set_bits(mcasp->base + DAVINCI_MCASP_PWREMUMGT_REG,
|
||||
MCASP_SOFT);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
|
||||
|
||||
/* All PINS as McASP */
|
||||
mcasp_set_reg(mcasp->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
|
||||
|
||||
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
|
||||
mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_XEVTCTL_REG,
|
||||
TXDATADMADIS);
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
|
||||
mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
|
||||
} else {
|
||||
mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
|
||||
mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_REVTCTL_REG,
|
||||
RXDATADMADIS);
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
|
||||
mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
|
||||
}
|
||||
|
||||
for (i = 0; i < mcasp->num_serializer; i++) {
|
||||
mcasp_set_bits(mcasp->base + DAVINCI_MCASP_XRSRCTL_REG(i),
|
||||
mcasp->serial_dir[i]);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
|
||||
mcasp->serial_dir[i]);
|
||||
if (mcasp->serial_dir[i] == TX_MODE &&
|
||||
tx_ser < max_active_serializers) {
|
||||
mcasp_set_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG,
|
||||
AXR(i));
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
|
||||
tx_ser++;
|
||||
} else if (mcasp->serial_dir[i] == RX_MODE &&
|
||||
rx_ser < max_active_serializers) {
|
||||
mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG,
|
||||
AXR(i));
|
||||
mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
|
||||
rx_ser++;
|
||||
} else {
|
||||
mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_XRSRCTL_REG(i),
|
||||
SRMOD_INACTIVE, SRMOD_MASK);
|
||||
mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
|
||||
SRMOD_INACTIVE, SRMOD_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -512,9 +505,9 @@ static int davinci_hw_common_param(struct davinci_mcasp *mcasp, int stream,
|
|||
mcasp->txnumevt = 1;
|
||||
|
||||
reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
|
||||
mcasp_mod_bits(mcasp->base + reg, tx_ser, NUMDMA_MASK);
|
||||
mcasp_mod_bits(mcasp->base + reg,
|
||||
((mcasp->txnumevt * tx_ser) << 8), NUMEVT_MASK);
|
||||
mcasp_mod_bits(mcasp, reg, tx_ser, NUMDMA_MASK);
|
||||
mcasp_mod_bits(mcasp, reg, ((mcasp->txnumevt * tx_ser) << 8),
|
||||
NUMEVT_MASK);
|
||||
}
|
||||
|
||||
if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
|
||||
|
|
@ -522,9 +515,9 @@ static int davinci_hw_common_param(struct davinci_mcasp *mcasp, int stream,
|
|||
mcasp->rxnumevt = 1;
|
||||
|
||||
reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
|
||||
mcasp_mod_bits(mcasp->base + reg, rx_ser, NUMDMA_MASK);
|
||||
mcasp_mod_bits(mcasp->base + reg,
|
||||
((mcasp->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
|
||||
mcasp_mod_bits(mcasp, reg, rx_ser, NUMDMA_MASK);
|
||||
mcasp_mod_bits(mcasp, reg, ((mcasp->rxnumevt * rx_ser) << 8),
|
||||
NUMEVT_MASK);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -540,7 +533,7 @@ static void davinci_hw_param(struct davinci_mcasp *mcasp, int stream)
|
|||
for (i = 0; i < active_slots; i++)
|
||||
mask |= (1 << i);
|
||||
|
||||
mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
|
||||
mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
|
||||
|
||||
if (!mcasp->dat_port)
|
||||
busel = TXSEL;
|
||||
|
|
@ -548,26 +541,24 @@ static void davinci_hw_param(struct davinci_mcasp *mcasp, int stream)
|
|||
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
/* bit stream is MSB first with no delay */
|
||||
/* DSP_B mode */
|
||||
mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXTDM_REG, mask);
|
||||
mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG,
|
||||
busel | TXORD);
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
|
||||
|
||||
if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32))
|
||||
mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_TXFMCTL_REG,
|
||||
FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
|
||||
mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
|
||||
FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
|
||||
else
|
||||
printk(KERN_ERR "playback tdm slot %d not supported\n",
|
||||
mcasp->tdm_slots);
|
||||
} else {
|
||||
/* bit stream is MSB first with no delay */
|
||||
/* DSP_B mode */
|
||||
mcasp_set_bits(mcasp->base + DAVINCI_MCASP_RXFMT_REG,
|
||||
busel | RXORD);
|
||||
mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXTDM_REG, mask);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
|
||||
|
||||
if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32))
|
||||
mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_RXFMCTL_REG,
|
||||
FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
|
||||
mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
|
||||
FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
|
||||
else
|
||||
printk(KERN_ERR "capture tdm slot %d not supported\n",
|
||||
mcasp->tdm_slots);
|
||||
|
|
@ -579,27 +570,24 @@ static void davinci_hw_dit_param(struct davinci_mcasp *mcasp)
|
|||
{
|
||||
/* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
|
||||
and LSB first */
|
||||
mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG,
|
||||
TXROT(6) | TXSSZ(15));
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
|
||||
|
||||
/* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
|
||||
mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXFMCTL_REG,
|
||||
AFSXE | FSXMOD(0x180));
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
|
||||
|
||||
/* Set the TX tdm : for all the slots */
|
||||
mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
|
||||
|
||||
/* Set the TX clock controls : div = 1 and internal */
|
||||
mcasp_set_bits(mcasp->base + DAVINCI_MCASP_ACLKXCTL_REG,
|
||||
ACLKXE | TX_ASYNC);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
|
||||
|
||||
mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
|
||||
mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
|
||||
|
||||
/* Only 44100 and 48000 are valid, both have the same setting */
|
||||
mcasp_set_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
|
||||
|
||||
/* Enable the DIT */
|
||||
mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
|
||||
mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
|
||||
}
|
||||
|
||||
static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
|
||||
|
|
@ -1106,15 +1094,14 @@ static int davinci_mcasp_remove(struct platform_device *pdev)
|
|||
static int davinci_mcasp_suspend(struct device *dev)
|
||||
{
|
||||
struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
|
||||
void __iomem *base = mcasp->base;
|
||||
|
||||
mcasp->context.txfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_TXFMCTL_REG);
|
||||
mcasp->context.rxfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_RXFMCTL_REG);
|
||||
mcasp->context.txfmt = mcasp_get_reg(base + DAVINCI_MCASP_TXFMT_REG);
|
||||
mcasp->context.rxfmt = mcasp_get_reg(base + DAVINCI_MCASP_RXFMT_REG);
|
||||
mcasp->context.aclkxctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKXCTL_REG);
|
||||
mcasp->context.aclkrctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKRCTL_REG);
|
||||
mcasp->context.pdir = mcasp_get_reg(base + DAVINCI_MCASP_PDIR_REG);
|
||||
mcasp->context.txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
|
||||
mcasp->context.rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
|
||||
mcasp->context.txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
|
||||
mcasp->context.rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
|
||||
mcasp->context.aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
|
||||
mcasp->context.aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
|
||||
mcasp->context.pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1122,15 +1109,14 @@ static int davinci_mcasp_suspend(struct device *dev)
|
|||
static int davinci_mcasp_resume(struct device *dev)
|
||||
{
|
||||
struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
|
||||
void __iomem *base = mcasp->base;
|
||||
|
||||
mcasp_set_reg(base + DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl);
|
||||
mcasp_set_reg(base + DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl);
|
||||
mcasp_set_reg(base + DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt);
|
||||
mcasp_set_reg(base + DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt);
|
||||
mcasp_set_reg(base + DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl);
|
||||
mcasp_set_reg(base + DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl);
|
||||
mcasp_set_reg(base + DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir);
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl);
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl);
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt);
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt);
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl);
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl);
|
||||
mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user