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drm/amd/pm: correct the checks for sclk/mclk SS support

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Correct sclk/mclk SS support checks.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan
2020-09-25 12:59:45 +08:00
committed by Alex Deucher
parent a8588b8bb3
commit f6638d0e6f
4 changed files with 26 additions and 1 deletions
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5
drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c
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@@ -478,6 +478,11 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_RegulatorHot); PHM_PlatformCaps_RegulatorHot);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MemorySpreadSpectrumSupport);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EngineSpreadSpectrumSupport);
phm_cap_set(hwmgr->platform_descriptor.platformCaps, phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_AutomaticDCTransition); PHM_PlatformCaps_AutomaticDCTransition);

13
drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
View File

@@ -1231,7 +1231,7 @@ uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr)
/** /**
* Get the asic internal spread spectrum table * Get the asic internal spread spectrum table
*/ */
static ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device) ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device)
{ {
ATOM_ASIC_INTERNAL_SS_INFO *table = NULL; ATOM_ASIC_INTERNAL_SS_INFO *table = NULL;
u8 frev, crev; u8 frev, crev;
@@ -1245,6 +1245,17 @@ static ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device)
return table; return table;
} }
bool atomctrl_is_asic_internal_ss_supported(struct pp_hwmgr *hwmgr)
{
ATOM_ASIC_INTERNAL_SS_INFO *table =
asic_internal_ss_get_ss_table(hwmgr->adev);
if (table)
return true;
else
return false;
}
/** /**
* Get the asic internal spread spectrum assignment * Get the asic internal spread spectrum assignment
*/ */

2
drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
View File

@@ -296,6 +296,8 @@ extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pi
extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage); extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
extern int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, uint16_t virtual_voltage_id, uint16_t *voltage); extern int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, uint16_t virtual_voltage_id, uint16_t *voltage);
extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr); extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
bool atomctrl_is_asic_internal_ss_supported(struct pp_hwmgr *hwmgr);
extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo); extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);
extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo); extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table); extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);

7
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
View File

@@ -1811,6 +1811,13 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
(adev->asic_type == CHIP_POLARIS12) || (adev->asic_type == CHIP_POLARIS12) ||
(adev->asic_type == CHIP_VEGAM)) (adev->asic_type == CHIP_VEGAM))
data->disable_edc_leakage_controller = false; data->disable_edc_leakage_controller = false;
if (!atomctrl_is_asic_internal_ss_supported(hwmgr)) {
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MemorySpreadSpectrumSupport);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EngineSpreadSpectrumSupport);
}
} }
static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr) static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr)