forked from Minki/linux
video: mb862xxfb: add support for L1 displaying
Allow displaying L1 video data on top of the primary L0 layer. The L1 layer position and dimensions can be configured and the layer enabled/disabled by using the appropriate L1 controls added by this patch. Signed-off-by: Anatolij Gustschin <agust@denx.de>
This commit is contained in:
Anatolij Gustschin
parent
f8a6b1f448
commit
f64d8a5fde
@ -51,10 +51,16 @@
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#define GC_L0OA0 0x00000024
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#define GC_L0DA0 0x00000028
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#define GC_L0DY_L0DX 0x0000002c
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#define GC_L1M 0x00000030
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#define GC_L1DA 0x00000034
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#define GC_DCM1 0x00000100
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#define GC_L0EM 0x00000110
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#define GC_L0WY_L0WX 0x00000114
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#define GC_L0WH_L0WW 0x00000118
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#define GC_L1EM 0x00000120
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#define GC_L1WY_L1WX 0x00000124
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#define GC_L1WH_L1WW 0x00000128
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#define GC_DLS 0x00000180
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#define GC_DCM2 0x00000104
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#define GC_DCM3 0x00000108
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#define GC_CPM_CUTC 0x000000a0
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@ -66,6 +72,11 @@
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#define GC_CPM_CEN0 0x00100000
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#define GC_CPM_CEN1 0x00200000
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#define GC_DCM1_DEN 0x80000000
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#define GC_DCM1_L1E 0x00020000
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#define GC_L1M_16 0x80000000
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#define GC_L1M_YC 0x40000000
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#define GC_L1M_CS 0x20000000
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#define GC_DCM01_ESY 0x00000004
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#define GC_DCM01_SC 0x00003f00
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@ -77,6 +88,7 @@
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#define GC_L0M_L0C_16 0x80000000
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#define GC_L0EM_L0EC_24 0x40000000
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#define GC_L0M_L0W_UNIT 64
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#define GC_L1EM_DM 0x02000000
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#define GC_DISP_REFCLK_400 400
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@ -101,6 +113,25 @@
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#define I2C_TRX 0x80
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#define I2C_LRB 0x10
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/* Capture registers and bits */
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#define GC_CAP_VCM 0x00000000
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#define GC_CAP_CSC 0x00000004
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#define GC_CAP_VCS 0x00000008
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#define GC_CAP_CBM 0x00000010
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#define GC_CAP_CBOA 0x00000014
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#define GC_CAP_CBLA 0x00000018
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#define GC_CAP_IMG_START 0x0000001C
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#define GC_CAP_IMG_END 0x00000020
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#define GC_CAP_CMSS 0x00000048
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#define GC_CAP_CMDS 0x0000004C
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#define GC_VCM_VIE 0x80000000
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#define GC_VCM_CM 0x03000000
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#define GC_VCM_VS_PAL 0x00000002
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#define GC_CBM_OO 0x80000000
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#define GC_CBM_HRV 0x00000010
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#define GC_CBM_CBST 0x00000001
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/* Carmine specific */
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#define MB86297_DRAW_BASE 0x00020000
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#define MB86297_DISP0_BASE 0x00100000
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@ -1,6 +1,26 @@
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#ifndef __MB862XX_H__
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#define __MB862XX_H__
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struct mb862xx_l1_cfg {
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unsigned short sx;
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unsigned short sy;
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unsigned short sw;
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unsigned short sh;
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unsigned short dx;
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unsigned short dy;
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unsigned short dw;
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unsigned short dh;
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int mirror;
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};
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#define MB862XX_BASE 'M'
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#define MB862XX_L1_GET_CFG _IOR(MB862XX_BASE, 0, struct mb862xx_l1_cfg*)
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#define MB862XX_L1_SET_CFG _IOW(MB862XX_BASE, 1, struct mb862xx_l1_cfg*)
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#define MB862XX_L1_ENABLE _IOW(MB862XX_BASE, 2, int)
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#define MB862XX_L1_CAP_CTL _IOW(MB862XX_BASE, 3, int)
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#ifdef __KERNEL__
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#define PCI_VENDOR_ID_FUJITSU_LIMITED 0x10cf
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#define PCI_DEVICE_ID_FUJITSU_CORALP 0x2019
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#define PCI_DEVICE_ID_FUJITSU_CORALPA 0x201e
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@ -38,6 +58,8 @@ struct mb862xxfb_par {
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void __iomem *mmio_base; /* remapped registers */
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size_t mapped_vram; /* length of remapped vram */
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size_t mmio_len; /* length of register region */
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unsigned long cap_buf; /* capture buffers offset */
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size_t cap_len; /* length of capture buffers */
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void __iomem *host; /* relocatable reg. bases */
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void __iomem *i2c;
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@ -60,6 +82,9 @@ struct mb862xxfb_par {
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struct i2c_adapter *adap; /* GDC I2C bus adapter */
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int i2c_rs;
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struct mb862xx_l1_cfg l1_cfg;
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int l1_stride;
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u32 pseudo_palette[16];
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};
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@ -91,4 +116,6 @@ static inline void mb862xx_i2c_exit(struct mb862xxfb_par *par) { }
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#define pack(a, b) (((a) << 16) | (b))
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#endif /* __KERNEL__ */
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#endif
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@ -27,7 +27,7 @@
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#define NR_PALETTE 256
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#define MB862XX_MEM_SIZE 0x1000000
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#define CORALP_MEM_SIZE 0x4000000
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#define CORALP_MEM_SIZE 0x2000000
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#define CARMINE_MEM_SIZE 0x8000000
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#define DRV_NAME "mb862xxfb"
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@ -309,6 +309,97 @@ static int mb862xxfb_blank(int mode, struct fb_info *fbi)
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return 0;
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}
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static int mb862xxfb_ioctl(struct fb_info *fbi, unsigned int cmd,
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unsigned long arg)
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{
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struct mb862xxfb_par *par = fbi->par;
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struct mb862xx_l1_cfg *l1_cfg = &par->l1_cfg;
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void __user *argp = (void __user *)arg;
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int *enable;
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u32 l1em = 0;
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switch (cmd) {
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case MB862XX_L1_GET_CFG:
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if (copy_to_user(argp, l1_cfg, sizeof(*l1_cfg)))
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return -EFAULT;
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break;
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case MB862XX_L1_SET_CFG:
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if (copy_from_user(l1_cfg, argp, sizeof(*l1_cfg)))
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return -EFAULT;
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if ((l1_cfg->sw >= l1_cfg->dw) && (l1_cfg->sh >= l1_cfg->dh)) {
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/* downscaling */
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outreg(cap, GC_CAP_CSC,
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pack((l1_cfg->sh << 11) / l1_cfg->dh,
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(l1_cfg->sw << 11) / l1_cfg->dw));
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l1em = inreg(disp, GC_L1EM);
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l1em &= ~GC_L1EM_DM;
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} else if ((l1_cfg->sw <= l1_cfg->dw) &&
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(l1_cfg->sh <= l1_cfg->dh)) {
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/* upscaling */
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outreg(cap, GC_CAP_CSC,
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pack((l1_cfg->sh << 11) / l1_cfg->dh,
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(l1_cfg->sw << 11) / l1_cfg->dw));
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outreg(cap, GC_CAP_CMSS,
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pack(l1_cfg->sw >> 1, l1_cfg->sh));
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outreg(cap, GC_CAP_CMDS,
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pack(l1_cfg->dw >> 1, l1_cfg->dh));
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l1em = inreg(disp, GC_L1EM);
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l1em |= GC_L1EM_DM;
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}
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if (l1_cfg->mirror) {
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outreg(cap, GC_CAP_CBM,
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inreg(cap, GC_CAP_CBM) | GC_CBM_HRV);
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l1em |= l1_cfg->dw * 2 - 8;
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} else {
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outreg(cap, GC_CAP_CBM,
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inreg(cap, GC_CAP_CBM) & ~GC_CBM_HRV);
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l1em &= 0xffff0000;
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}
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outreg(disp, GC_L1EM, l1em);
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break;
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case MB862XX_L1_ENABLE:
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enable = (int *)arg;
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if (*enable) {
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outreg(disp, GC_L1DA, par->cap_buf);
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outreg(cap, GC_CAP_IMG_START,
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pack(l1_cfg->sy >> 1, l1_cfg->sx));
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outreg(cap, GC_CAP_IMG_END,
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pack(l1_cfg->sh, l1_cfg->sw));
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outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS |
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(par->l1_stride << 16));
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outreg(disp, GC_L1WY_L1WX,
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pack(l1_cfg->dy, l1_cfg->dx));
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outreg(disp, GC_L1WH_L1WW,
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pack(l1_cfg->dh - 1, l1_cfg->dw));
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outreg(disp, GC_DLS, 1);
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outreg(cap, GC_CAP_VCM,
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GC_VCM_VIE | GC_VCM_CM | GC_VCM_VS_PAL);
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outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) |
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GC_DCM1_DEN | GC_DCM1_L1E);
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} else {
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outreg(cap, GC_CAP_VCM,
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inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
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outreg(disp, GC_DCM1,
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inreg(disp, GC_DCM1) & ~GC_DCM1_L1E);
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}
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break;
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case MB862XX_L1_CAP_CTL:
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enable = (int *)arg;
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if (*enable) {
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outreg(cap, GC_CAP_VCM,
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inreg(cap, GC_CAP_VCM) | GC_VCM_VIE);
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} else {
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outreg(cap, GC_CAP_VCM,
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inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
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}
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/* framebuffer ops */
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static struct fb_ops mb862xxfb_ops = {
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.owner = THIS_MODULE,
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@ -320,6 +411,7 @@ static struct fb_ops mb862xxfb_ops = {
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.fb_fillrect = cfb_fillrect,
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.fb_copyarea = cfb_copyarea,
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.fb_imageblit = cfb_imageblit,
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.fb_ioctl = mb862xxfb_ioctl,
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};
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/* initialize fb_info data */
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@ -328,6 +420,7 @@ static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
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struct mb862xxfb_par *par = fbi->par;
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struct mb862xx_gc_mode *mode = par->gc_mode;
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unsigned long reg;
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int stride;
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fbi->fbops = &mb862xxfb_ops;
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fbi->pseudo_palette = par->pseudo_palette;
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@ -420,6 +513,27 @@ static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
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fbi->fix.line_length = (fbi->var.xres_virtual *
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fbi->var.bits_per_pixel) / 8;
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fbi->fix.smem_len = fbi->fix.line_length * fbi->var.yres_virtual;
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/*
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* reserve space for capture buffers and two cursors
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* at the end of vram: 720x576 * 2 * 2.2 + 64x64 * 16.
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*/
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par->cap_buf = par->mapped_vram - 0x1bd800 - 0x10000;
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par->cap_len = 0x1bd800;
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par->l1_cfg.sx = 0;
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par->l1_cfg.sy = 0;
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par->l1_cfg.sw = 720;
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par->l1_cfg.sh = 576;
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par->l1_cfg.dx = 0;
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par->l1_cfg.dy = 0;
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par->l1_cfg.dw = 720;
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par->l1_cfg.dh = 576;
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stride = par->l1_cfg.sw * (fbi->var.bits_per_pixel / 8);
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par->l1_stride = stride / 64 + ((stride % 64) ? 1 : 0);
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outreg(cap, GC_CAP_CBM, GC_CBM_OO | GC_CBM_CBST |
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(par->l1_stride << 16));
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outreg(cap, GC_CAP_CBOA, par->cap_buf);
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outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len);
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return 0;
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}
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