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drm/amdgpu: only use one gfx pipe for Sienna_Cichlid

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Only enable one gfx pipe for sienna_cichlid currently.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao
2020-04-17 17:33:35 +08:00
committed by Alex Deucher
parent 338d90b613
commit f64668f9aa
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
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@@ -55,7 +55,7 @@
* 2. Async ring * 2. Async ring
*/ */
#define GFX10_NUM_GFX_RINGS_NV1X 1 #define GFX10_NUM_GFX_RINGS_NV1X 1
#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1
#define GFX10_MEC_HPD_SIZE 2048 #define GFX10_MEC_HPD_SIZE 2048
#define F32_CE_PROGRAM_RAM_SIZE 65536 #define F32_CE_PROGRAM_RAM_SIZE 65536
@@ -4232,7 +4232,7 @@ static int gfx_v10_0_sw_init(void *handle)
break; break;
case CHIP_SIENNA_CICHLID: case CHIP_SIENNA_CICHLID:
adev->gfx.me.num_me = 1; adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 2; adev->gfx.me.num_pipe_per_me = 1;
adev->gfx.me.num_queue_per_pipe = 1; adev->gfx.me.num_queue_per_pipe = 1;
adev->gfx.mec.num_mec = 2; adev->gfx.mec.num_mec = 2;
adev->gfx.mec.num_pipe_per_mec = 4; adev->gfx.mec.num_pipe_per_mec = 4;