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clk: imx: clk-fracn-gppll: correct rdiv

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According to Reference Manual:
 000b - Divide by 1
 001b - Divide by 1
 010b - Divide by 2
 011b - Divide by 3
 100b - Divide by 4
 101b - Divide by 5
 110b - Divide by 6
 111b - Divide by 7

So only need increase rdiv by 1 when the register value is 0.

Fixes: 1b26cb8a77 ("clk: imx: support fracn gppll")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20220609132902.3504651-7-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
This commit is contained in:
Peng Fan 2022-06-09 21:29:01 +08:00 committed by Abel Vesa
parent 5ebaf9f7da
commit f300cb7fcc
1 changed files with 2 additions and 1 deletions
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3
drivers/clk/imx/clk-fracn-gppll.c
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@ -149,7 +149,8 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
if (rate)
return (unsigned long)rate;
rdiv = rdiv + 1;
if (!rdiv)
rdiv = rdiv + 1;
switch (odiv) {
case 0: