mlx5-fixes-2020-05-28
-----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEGhZs6bAKwk/OTgTpSD+KveBX+j4FAl7Ra5oACgkQSD+KveBX +j6TVQgAr/LLADIfJJxxMWEU9hjEdBx1H0ojxkh/OZRqwkkKsffmeeQm2Ovei1aY VRhyj6kr2UGYu970dtDzEVTZePdk+Hgapl3v6cIXM4IMPKGsUkYrhcaopyub1vRV g/3uClIbVmgtxX7NBSJL1e6KGvrGQJ9OFEaNw8gHrN5+ba4qW9PIhMnoybQ0S2r4 eE39I4ZDWU6SAWqbVNTmiwpycPb6mtTRu3zfeX04+4hprQTPpyJ5rKtvKABLVRoY upkOSPCxUVIzspci/FlfXNzXb08MelVl2o7LUzklQVIiQpnsnY+hBg+y8qTMQ4TA ErFI/P2vl+UwOwqKV7RwB78q3l9A4w== =hk6W -----END PGP SIGNATURE----- Merge tag 'mlx5-fixes-2020-05-28' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux Saeed Mahameed says: ==================== mlx5 fixes 2020-05-28 This series introduces some fixes to mlx5 driver. v1->v2: - Fix bad sha1, Jakub. - Added one more patch by Pablo. net/mlx5e: replace EINVAL in mlx5e_flower_parse_meta() Nothing major, the only patch worth mentioning is the suspend/resume crash fix by adding the missing pci device handlers, the fix is very straight forward and as Dexuan already expressed, the patch is important for Azure users to avoid crash on VM hibernation, patch is marked for -stable v4.6 below. Conflict note: ('net/mlx5e: Fix MLX5_TC_CT dependencies') has a trivial one line conflict with current net-next, which can be resolved by simply using the line from net-next. Please pull and let me know if there is any problem. For -stable v4.6 ('net/mlx5: Fix crash upon suspend/resume') For -stable v5.6 ('net/mlx5e: replace EINVAL in mlx5e_flower_parse_meta()') ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
f2b122d3d6
@ -80,7 +80,7 @@ config MLX5_ESWITCH
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config MLX5_TC_CT
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bool "MLX5 TC connection tracking offload support"
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depends on MLX5_CORE_EN && NET_SWITCHDEV && NF_FLOW_TABLE && NET_ACT_CT && NET_TC_SKB_EXT
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depends on MLX5_ESWITCH && NF_FLOW_TABLE && NET_ACT_CT && NET_TC_SKB_EXT
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default y
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help
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Say Y here if you want to support offloading connection tracking rules
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@ -1068,10 +1068,12 @@ void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
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void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
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int num_channels);
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void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
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u8 cq_period_mode);
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void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
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u8 cq_period_mode);
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void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode);
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void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode);
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void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode);
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void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode);
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void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
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void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
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struct mlx5e_params *params);
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@ -369,17 +369,19 @@ enum mlx5e_fec_supported_link_mode {
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*_policy = MLX5_GET(pplm_reg, _buf, fec_override_admin_##link); \
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} while (0)
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#define MLX5E_FEC_OVERRIDE_ADMIN_50G_POLICY(buf, policy, write, link) \
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do { \
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u16 *__policy = &(policy); \
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bool _write = (write); \
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\
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if (_write && *__policy) \
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*__policy = find_first_bit((u_long *)__policy, \
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sizeof(u16) * BITS_PER_BYTE);\
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MLX5E_FEC_OVERRIDE_ADMIN_POLICY(buf, *__policy, _write, link); \
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if (!_write && *__policy) \
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*__policy = 1 << *__policy; \
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#define MLX5E_FEC_OVERRIDE_ADMIN_50G_POLICY(buf, policy, write, link) \
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do { \
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unsigned long policy_long; \
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u16 *__policy = &(policy); \
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bool _write = (write); \
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\
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policy_long = *__policy; \
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if (_write && *__policy) \
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*__policy = find_first_bit(&policy_long, \
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sizeof(policy_long) * BITS_PER_BYTE);\
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MLX5E_FEC_OVERRIDE_ADMIN_POLICY(buf, *__policy, _write, link); \
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if (!_write && *__policy) \
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*__policy = 1 << *__policy; \
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} while (0)
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/* get/set FEC admin field for a given speed */
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@ -527,8 +527,8 @@ int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
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struct dim_cq_moder *rx_moder, *tx_moder;
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struct mlx5_core_dev *mdev = priv->mdev;
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struct mlx5e_channels new_channels = {};
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bool reset_rx, reset_tx;
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int err = 0;
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bool reset;
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if (!MLX5_CAP_GEN(mdev, cq_moderation))
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return -EOPNOTSUPP;
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@ -566,15 +566,28 @@ int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
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}
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/* we are opened */
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reset = (!!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled) ||
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(!!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled);
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reset_rx = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled;
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reset_tx = !!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled;
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if (!reset) {
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if (!reset_rx && !reset_tx) {
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mlx5e_set_priv_channels_coalesce(priv, coal);
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priv->channels.params = new_channels.params;
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goto out;
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}
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if (reset_rx) {
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u8 mode = MLX5E_GET_PFLAG(&new_channels.params,
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MLX5E_PFLAG_RX_CQE_BASED_MODER);
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mlx5e_reset_rx_moderation(&new_channels.params, mode);
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}
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if (reset_tx) {
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u8 mode = MLX5E_GET_PFLAG(&new_channels.params,
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MLX5E_PFLAG_TX_CQE_BASED_MODER);
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mlx5e_reset_tx_moderation(&new_channels.params, mode);
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}
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err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
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out:
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@ -665,11 +678,12 @@ static const u32 pplm_fec_2_ethtool_linkmodes[] = {
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static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
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struct ethtool_link_ksettings *link_ksettings)
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{
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u_long active_fec = 0;
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unsigned long active_fec_long;
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u32 active_fec;
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u32 bitn;
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int err;
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err = mlx5e_get_fec_mode(dev, (u32 *)&active_fec, NULL);
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err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
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if (err)
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return (err == -EOPNOTSUPP) ? 0 : err;
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@ -682,10 +696,11 @@ static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
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MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1,
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ETHTOOL_LINK_MODE_FEC_LLRS_BIT);
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active_fec_long = active_fec;
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/* active fec is a bit set, find out which bit is set and
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* advertise the corresponding ethtool bit
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*/
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bitn = find_first_bit(&active_fec, sizeof(u32) * BITS_PER_BYTE);
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bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE);
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if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes))
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__set_bit(pplm_fec_2_ethtool_linkmodes[bitn],
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link_ksettings->link_modes.advertising);
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@ -1517,8 +1532,8 @@ static int mlx5e_get_fecparam(struct net_device *netdev,
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{
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struct mlx5e_priv *priv = netdev_priv(netdev);
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struct mlx5_core_dev *mdev = priv->mdev;
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u16 fec_configured = 0;
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u32 fec_active = 0;
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u16 fec_configured;
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u32 fec_active;
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int err;
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err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
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@ -1526,14 +1541,14 @@ static int mlx5e_get_fecparam(struct net_device *netdev,
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if (err)
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return err;
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fecparam->active_fec = pplm2ethtool_fec((u_long)fec_active,
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sizeof(u32) * BITS_PER_BYTE);
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fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active,
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sizeof(unsigned long) * BITS_PER_BYTE);
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if (!fecparam->active_fec)
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return -EOPNOTSUPP;
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fecparam->fec = pplm2ethtool_fec((u_long)fec_configured,
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sizeof(u16) * BITS_PER_BYTE);
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fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured,
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sizeof(unsigned long) * BITS_PER_BYTE);
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return 0;
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}
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@ -4716,7 +4716,7 @@ static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
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DIM_CQ_PERIOD_MODE_START_FROM_EQE;
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}
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void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
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void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
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{
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if (params->tx_dim_enabled) {
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u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
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@ -4725,13 +4725,9 @@ void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
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} else {
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params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
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}
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MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
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params->tx_cq_moderation.cq_period_mode ==
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MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
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}
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void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
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void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode)
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{
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if (params->rx_dim_enabled) {
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u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
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@ -4740,7 +4736,19 @@ void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
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} else {
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params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
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}
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}
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void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
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{
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mlx5e_reset_tx_moderation(params, cq_period_mode);
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MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
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params->tx_cq_moderation.cq_period_mode ==
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MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
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}
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void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
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{
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mlx5e_reset_rx_moderation(params, cq_period_mode);
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MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
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params->rx_cq_moderation.cq_period_mode ==
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MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
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@ -2068,7 +2068,7 @@ static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
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flow_rule_match_meta(rule, &match);
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if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
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NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
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return -EINVAL;
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return -EOPNOTSUPP;
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}
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ingress_dev = __dev_get_by_index(dev_net(filter_dev),
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@ -2076,13 +2076,13 @@ static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
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if (!ingress_dev) {
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NL_SET_ERR_MSG_MOD(extack,
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"Can't find the ingress port to match on");
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return -EINVAL;
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return -ENOENT;
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}
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if (ingress_dev != filter_dev) {
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NL_SET_ERR_MSG_MOD(extack,
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"Can't match on the ingress filter port");
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return -EINVAL;
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return -EOPNOTSUPP;
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}
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return 0;
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@ -3849,10 +3849,6 @@ static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
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if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
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NL_SET_ERR_MSG_MOD(extack,
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"devices are not on same switch HW, can't offload forwarding");
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netdev_warn(priv->netdev,
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"devices %s %s not on same switch HW, can't offload forwarding\n",
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priv->netdev->name,
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out_dev->name);
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return -EOPNOTSUPP;
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}
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@ -4614,7 +4610,7 @@ void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
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dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
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dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
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rpriv->prev_vf_vport_stats = cur_stats;
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flow_stats_update(&ma->stats, dpkts, dbytes, jiffies,
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flow_stats_update(&ma->stats, dbytes, dpkts, jiffies,
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FLOW_ACTION_HW_STATS_DELAYED);
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}
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@ -1549,6 +1549,22 @@ static void shutdown(struct pci_dev *pdev)
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mlx5_pci_disable_device(dev);
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}
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static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
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mlx5_unload_one(dev, false);
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return 0;
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}
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static int mlx5_resume(struct pci_dev *pdev)
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{
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struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
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return mlx5_load_one(dev, false);
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}
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static const struct pci_device_id mlx5_core_pci_table[] = {
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{ PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
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{ PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
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@ -1592,6 +1608,8 @@ static struct pci_driver mlx5_core_driver = {
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.id_table = mlx5_core_pci_table,
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.probe = init_one,
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.remove = remove_one,
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.suspend = mlx5_suspend,
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.resume = mlx5_resume,
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.shutdown = shutdown,
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.err_handler = &mlx5_err_handler,
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.sriov_configure = mlx5_core_sriov_configure,
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