forked from Minki/linux
ARM: imx: use __iomem pointers for MMIO
ARM is moving to stricter checks on readl/write functions, so we need to use the correct types everywhere. This found a bug in mach-armadillo5x0.c, where we attempt mmio on the MXC_CCM_RCSR address that is currently defined to 0xc and consequently causes an illegal address access. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Shawn Guo <shawn.guo@linaro.org>
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a21e5e282b
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@ -259,13 +259,13 @@ static void __init kzm_board_init(void)
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*/
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static struct map_desc kzm_io_desc[] __initdata = {
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{
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.virtual = MX31_CS4_BASE_ADDR_VIRT,
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.virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
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.length = MX31_CS4_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = MX31_CS5_BASE_ADDR_VIRT,
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.virtual = (unsigned long)MX31_CS5_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
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.length = MX31_CS5_SIZE,
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.type = MT_DEVICE
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@ -540,7 +540,7 @@ static void __init mxc_init_audio(void)
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*/
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static struct map_desc mx31ads_io_desc[] __initdata = {
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{
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.virtual = MX31_CS4_BASE_ADDR_VIRT,
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.virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
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.length = CS4_CS8900_MMIO_START,
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.type = MT_DEVICE
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@ -207,7 +207,7 @@ static struct platform_device physmap_flash_device = {
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*/
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static struct map_desc mx31lite_io_desc[] __initdata = {
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{
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.virtual = MX31_CS4_BASE_ADDR_VIRT,
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.virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
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.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
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.length = MX31_CS4_SIZE,
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.type = MT_DEVICE
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@ -76,7 +76,7 @@
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#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
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#define MX31_ROMP_BASE_ADDR 0x60000000
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#define MX31_ROMP_BASE_ADDR_VIRT 0xfc500000
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#define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000)
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#define MX31_ROMP_SIZE SZ_1M
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#define MX31_AVIC_BASE_ADDR 0x68000000
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@ -92,11 +92,11 @@
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#define MX31_CS3_BASE_ADDR 0xb2000000
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#define MX31_CS4_BASE_ADDR 0xb4000000
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#define MX31_CS4_BASE_ADDR_VIRT 0xf6000000
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#define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000)
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#define MX31_CS4_SIZE SZ_32M
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#define MX31_CS5_BASE_ADDR 0xb6000000
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#define MX31_CS5_BASE_ADDR_VIRT 0xf8000000
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#define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000)
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#define MX31_CS5_SIZE SZ_32M
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#define MX31_X_MEMC_BASE_ADDR 0xb8000000
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