forked from Minki/linux
sh: remove old TMU driver
This patch removes the old TMU driver (CONFIG_SH_TMU/timer-tmu.c) As replacement, select the sh_tmu driver with CONFIG_SH_TIMER_TMU and configure timer channel using platform data. If multiple TMU channels are enabled using platform data, use the earlytimer parameter on the kernel command line to select channel. For instance, use "earlytimer=sh_tmu.0" to select the first channel. To verify which timer is being used, look at printouts or the timer irq count in /proc/interrupts. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
2b23a8826a
commit
f19900b2e6
@ -473,16 +473,9 @@ source "arch/sh/boards/Kconfig"
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menu "Timer and clock configuration"
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config SH_TMU
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bool "TMU timer support"
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depends on CPU_SH3 || CPU_SH4
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default y
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help
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This enables the use of the TMU as the system timer.
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config SH_TIMER_TMU
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bool "TMU timer driver"
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depends on !SH_TMU && SYS_SUPPORTS_TMU
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depends on SYS_SUPPORTS_TMU
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default y
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help
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This enables the build of the TMU timer driver.
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@ -18,7 +18,6 @@ struct sys_timer {
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struct sys_timer_ops *ops;
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};
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extern struct sys_timer tmu_timer;
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extern struct sys_timer *sys_timer;
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/* arch/sh/kernel/timers/timer.c */
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@ -1,67 +0,0 @@
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/*
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* include/asm-sh/cpu-sh3/timer.h
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*
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* Copyright (C) 2004 Lineo Solutions, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH3_TIMER_H
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#define __ASM_CPU_SH3_TIMER_H
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/*
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* ---------------------------------------------------------------------------
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* TMU Common definitions for SH3 processors
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* SH7706
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* SH7709S
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* SH7727
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* SH7729R
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* SH7710
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* SH7720
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* SH7710
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* ---------------------------------------------------------------------------
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*/
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#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
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#define TMU_TOCR 0xfffffe90 /* Byte access */
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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#define TMU_012_TSTR 0xa412fe92 /* Byte access */
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#define TMU0_TCOR 0xa412fe94 /* Long access */
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#define TMU0_TCNT 0xa412fe98 /* Long access */
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#define TMU0_TCR 0xa412fe9c /* Word access */
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#define TMU1_TCOR 0xa412fea0 /* Long access */
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#define TMU1_TCNT 0xa412fea4 /* Long access */
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#define TMU1_TCR 0xa412fea8 /* Word access */
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#define TMU2_TCOR 0xa412feac /* Long access */
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#define TMU2_TCNT 0xa412feb0 /* Long access */
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#define TMU2_TCR 0xa412feb4 /* Word access */
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#else
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#define TMU_012_TSTR 0xfffffe92 /* Byte access */
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#define TMU0_TCOR 0xfffffe94 /* Long access */
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#define TMU0_TCNT 0xfffffe98 /* Long access */
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#define TMU0_TCR 0xfffffe9c /* Word access */
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#define TMU1_TCOR 0xfffffea0 /* Long access */
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#define TMU1_TCNT 0xfffffea4 /* Long access */
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#define TMU1_TCR 0xfffffea8 /* Word access */
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#define TMU2_TCOR 0xfffffeac /* Long access */
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#define TMU2_TCNT 0xfffffeb0 /* Long access */
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#define TMU2_TCR 0xfffffeb4 /* Word access */
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#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
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#define TMU2_TCPR2 0xfffffeb8 /* Long access */
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#endif
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#endif
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#endif /* __ASM_CPU_SH3_TIMER_H */
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@ -1,60 +0,0 @@
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/*
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* include/asm-sh/cpu-sh4/timer.h
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*
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* Copyright (C) 2004 Lineo Solutions, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH4_TIMER_H
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#define __ASM_CPU_SH4_TIMER_H
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/*
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* ---------------------------------------------------------------------------
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* TMU Common definitions for SH4 processors
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* SH7750S/SH7750R
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* SH7751/SH7751R
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* SH7760
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* SH-X3
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* ---------------------------------------------------------------------------
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*/
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#ifdef CONFIG_CPU_SUBTYPE_SHX3
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#define TMU_012_BASE 0xffc10000
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#define TMU_345_BASE 0xffc20000
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#else
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#define TMU_012_BASE 0xffd80000
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#define TMU_345_BASE 0xfe100000
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#endif
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#define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */
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#define TMU_012_TSTR (TMU_012_BASE + 0x04)
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#define TMU_345_TSTR (TMU_345_BASE + 0x04)
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#define TMU0_TCOR (TMU_012_BASE + 0x08)
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#define TMU0_TCNT (TMU_012_BASE + 0x0c)
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#define TMU0_TCR (TMU_012_BASE + 0x10)
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#define TMU1_TCOR (TMU_012_BASE + 0x14)
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#define TMU1_TCNT (TMU_012_BASE + 0x18)
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#define TMU1_TCR (TMU_012_BASE + 0x1c)
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#define TMU2_TCOR (TMU_012_BASE + 0x20)
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#define TMU2_TCNT (TMU_012_BASE + 0x24)
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#define TMU2_TCR (TMU_012_BASE + 0x28)
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#define TMU2_TCPR (TMU_012_BASE + 0x2c)
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#define TMU3_TCOR (TMU_345_BASE + 0x08)
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#define TMU3_TCNT (TMU_345_BASE + 0x0c)
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#define TMU3_TCR (TMU_345_BASE + 0x10)
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#define TMU4_TCOR (TMU_345_BASE + 0x14)
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#define TMU4_TCNT (TMU_345_BASE + 0x18)
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#define TMU4_TCR (TMU_345_BASE + 0x1c)
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#define TMU5_TCOR (TMU_345_BASE + 0x20)
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#define TMU5_TCNT (TMU_345_BASE + 0x24)
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#define TMU5_TCR (TMU_345_BASE + 0x28)
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#endif /* __ASM_CPU_SH4_TIMER_H */
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@ -3,5 +3,3 @@
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#
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obj-y := timer.o
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obj-$(CONFIG_SH_TMU) += timer-tmu.o
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@ -1,297 +0,0 @@
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/*
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* arch/sh/kernel/timers/timer-tmu.c - TMU Timer Support
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*
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* Copyright (C) 2005 - 2007 Paul Mundt
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*
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* TMU handling code hacked out of arch/sh/kernel/time.c
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*
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* Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
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* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
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* Copyright (C) 2002, 2003, 2004 Paul Mundt
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* Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/seqlock.h>
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#include <linux/clockchips.h>
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#include <asm/timer.h>
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#include <asm/rtc.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/clock.h>
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#define TMU_TOCR_INIT 0x00
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#define TMU_TCR_INIT 0x0020
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#define TMU0 (0)
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#define TMU1 (1)
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static inline void _tmu_start(int tmu_num)
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{
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ctrl_outb(ctrl_inb(TMU_012_TSTR) | (0x1<<tmu_num), TMU_012_TSTR);
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}
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static inline void _tmu_set_irq(int tmu_num, int enabled)
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{
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register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
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ctrl_outw( (enabled ? ctrl_inw(tmu_tcr) | (1<<5) : ctrl_inw(tmu_tcr) & ~(1<<5)), tmu_tcr);
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}
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static inline void _tmu_stop(int tmu_num)
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{
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ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~(0x1<<tmu_num), TMU_012_TSTR);
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}
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static inline void _tmu_clear_status(int tmu_num)
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{
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register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
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/* Clear UNF bit */
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ctrl_outw(ctrl_inw(tmu_tcr) & ~0x100, tmu_tcr);
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}
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static inline unsigned long _tmu_read(int tmu_num)
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{
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return ctrl_inl(TMU0_TCNT+0xC*tmu_num);
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}
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static int tmu_timer_start(void)
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{
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_tmu_start(TMU0);
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_tmu_start(TMU1);
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_tmu_set_irq(TMU0,1);
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return 0;
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}
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static int tmu_timer_stop(void)
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{
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_tmu_stop(TMU0);
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_tmu_stop(TMU1);
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_tmu_clear_status(TMU0);
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return 0;
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}
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/*
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* also when the module_clk is scaled the TMU1
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* will show the same frequency
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*/
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static int tmus_are_scaled;
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static cycle_t tmu_timer_read(struct clocksource *cs)
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{
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return ((cycle_t)(~_tmu_read(TMU1)))<<tmus_are_scaled;
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}
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static unsigned long tmu_latest_interval[3];
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static void tmu_timer_set_interval(int tmu_num, unsigned long interval, unsigned int reload)
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{
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unsigned long tmu_tcnt = TMU0_TCNT + tmu_num*0xC;
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unsigned long tmu_tcor = TMU0_TCOR + tmu_num*0xC;
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_tmu_stop(tmu_num);
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ctrl_outl(interval, tmu_tcnt);
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tmu_latest_interval[tmu_num] = interval;
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/*
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* TCNT reloads from TCOR on underflow, clear it if we don't
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* intend to auto-reload
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*/
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ctrl_outl( reload ? interval : 0 , tmu_tcor);
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_tmu_start(tmu_num);
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}
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static int tmu_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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tmu_timer_set_interval(TMU0,cycles, evt->mode == CLOCK_EVT_MODE_PERIODIC);
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_tmu_set_irq(TMU0,1);
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return 0;
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}
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static void tmu_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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ctrl_outl(tmu_latest_interval[TMU0], TMU0_TCOR);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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ctrl_outl(0, TMU0_TCOR);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static struct clock_event_device tmu0_clockevent = {
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.name = "tmu0",
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.shift = 32,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = tmu_set_mode,
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.set_next_event = tmu_set_next_event,
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};
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static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
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{
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struct clock_event_device *evt = &tmu0_clockevent;
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_tmu_clear_status(TMU0);
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_tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT);
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switch (tmu0_clockevent.mode) {
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_PERIODIC:
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evt->event_handler(evt);
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break;
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default:
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break;
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}
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return IRQ_HANDLED;
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}
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static struct irqaction tmu0_irq = {
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.name = "periodic/oneshot timer",
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.handler = tmu_timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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};
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static void __init tmu_clk_init(struct clk *clk)
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{
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u8 divisor = TMU_TCR_INIT & 0x7;
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int tmu_num = clk->name[3]-'0';
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ctrl_outw(TMU_TCR_INIT, TMU0_TCR+(tmu_num*0xC));
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clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
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}
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static void tmu_clk_recalc(struct clk *clk)
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{
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int tmu_num = clk->name[3]-'0';
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unsigned long prev_rate = clk_get_rate(clk);
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unsigned long flags;
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u8 divisor = ctrl_inw(TMU0_TCR+tmu_num*0xC) & 0x7;
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clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
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if(prev_rate==clk_get_rate(clk))
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return;
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if(tmu_num)
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return; /* No more work on TMU1 */
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local_irq_save(flags);
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tmus_are_scaled = (prev_rate > clk->rate);
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_tmu_stop(TMU0);
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tmu0_clockevent.mult = div_sc(clk->rate, NSEC_PER_SEC,
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tmu0_clockevent.shift);
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tmu0_clockevent.max_delta_ns =
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clockevent_delta2ns(-1, &tmu0_clockevent);
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tmu0_clockevent.min_delta_ns =
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clockevent_delta2ns(1, &tmu0_clockevent);
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if (tmus_are_scaled)
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tmu_latest_interval[TMU0] >>= 1;
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else
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tmu_latest_interval[TMU0] <<= 1;
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tmu_timer_set_interval(TMU0,
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tmu_latest_interval[TMU0],
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tmu0_clockevent.mode == CLOCK_EVT_MODE_PERIODIC);
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_tmu_start(TMU0);
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local_irq_restore(flags);
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}
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static struct clk_ops tmu_clk_ops = {
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.init = tmu_clk_init,
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.recalc = tmu_clk_recalc,
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};
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static struct clk tmu0_clk = {
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.name = "tmu0_clk",
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.ops = &tmu_clk_ops,
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};
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static struct clk tmu1_clk = {
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.name = "tmu1_clk",
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.ops = &tmu_clk_ops,
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};
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static int tmu_timer_init(void)
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{
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unsigned long interval;
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unsigned long frequency;
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setup_irq(CONFIG_SH_TIMER_IRQ, &tmu0_irq);
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tmu0_clk.parent = clk_get(NULL, "module_clk");
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tmu1_clk.parent = clk_get(NULL, "module_clk");
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tmu_timer_stop();
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#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
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!defined(CONFIG_CPU_SUBTYPE_SH7721) && \
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!defined(CONFIG_CPU_SUBTYPE_SH7760) && \
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!defined(CONFIG_CPU_SUBTYPE_SH7785) && \
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!defined(CONFIG_CPU_SUBTYPE_SH7786) && \
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!defined(CONFIG_CPU_SUBTYPE_SHX3)
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ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
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#endif
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clk_register(&tmu0_clk);
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clk_register(&tmu1_clk);
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clk_enable(&tmu0_clk);
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clk_enable(&tmu1_clk);
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frequency = clk_get_rate(&tmu0_clk);
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interval = (frequency + HZ / 2) / HZ;
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tmu_timer_set_interval(TMU0,interval, 1);
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tmu_timer_set_interval(TMU1,~0,1);
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_tmu_start(TMU1);
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clocksource_sh.rating = 200;
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clocksource_sh.mask = CLOCKSOURCE_MASK(32);
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clocksource_sh.read = tmu_timer_read;
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clocksource_sh.shift = 10;
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clocksource_sh.mult = clocksource_hz2mult(clk_get_rate(&tmu1_clk),
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clocksource_sh.shift);
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clocksource_sh.flags = CLOCK_SOURCE_IS_CONTINUOUS;
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clocksource_register(&clocksource_sh);
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tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC,
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tmu0_clockevent.shift);
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tmu0_clockevent.max_delta_ns =
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||||
clockevent_delta2ns(-1, &tmu0_clockevent);
|
||||
tmu0_clockevent.min_delta_ns =
|
||||
clockevent_delta2ns(1, &tmu0_clockevent);
|
||||
|
||||
tmu0_clockevent.cpumask = cpumask_of(0);
|
||||
tmu0_clockevent.rating = 100;
|
||||
|
||||
clockevents_register_device(&tmu0_clockevent);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sys_timer_ops tmu_timer_ops = {
|
||||
.init = tmu_timer_init,
|
||||
.start = tmu_timer_start,
|
||||
.stop = tmu_timer_stop,
|
||||
};
|
||||
|
||||
struct sys_timer tmu_timer = {
|
||||
.name = "tmu",
|
||||
.ops = &tmu_timer_ops,
|
||||
};
|
||||
@ -14,9 +14,6 @@
|
||||
#include <asm/timer.h>
|
||||
|
||||
static struct sys_timer *sys_timers[] = {
|
||||
#ifdef CONFIG_SH_TMU
|
||||
&tmu_timer,
|
||||
#endif
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user