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Revert "drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping"

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This reverts commit 991d9557b0 ("drm/i915/tgl/dsi: Gate the ddi clocks
after pll mapping"). The Bspec was updated recently with the pll ungate
sequence similar to that of icl dsi enable sequence. Hence reverting.

Bspec: 49187
Fixes: 991d9557b0 ("drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping")
Cc: <stable@vger.kernel.org> # v5.4+
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211109120428.15211-1-vandita.kulkarni@intel.com
(cherry picked from commit 4579509ef1)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Vandita Kulkarni
2021-11-09 17:34:28 +05:30
committed by Rodrigo Vivi
parent fa55b7dcdc
commit f15863b277
1 changed files with 2 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/drm/i915/display/icl_dsi.c
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@@ -696,9 +696,6 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
for_each_dsi_phy(phy, intel_dsi->phys) { for_each_dsi_phy(phy, intel_dsi->phys) {
if (DISPLAY_VER(dev_priv) >= 12)
val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
else
val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
} }
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
@@ -1135,8 +1132,6 @@ static void
gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state) const struct intel_crtc_state *crtc_state)
{ {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
/* step 4a: power up all lanes of the DDI used by DSI */ /* step 4a: power up all lanes of the DDI used by DSI */
gen11_dsi_power_up_lanes(encoder); gen11_dsi_power_up_lanes(encoder);
@@ -1162,7 +1157,6 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
gen11_dsi_configure_transcoder(encoder, crtc_state); gen11_dsi_configure_transcoder(encoder, crtc_state);
/* Step 4l: Gate DDI clocks */ /* Step 4l: Gate DDI clocks */
if (DISPLAY_VER(dev_priv) == 11)
gen11_dsi_gate_clocks(encoder); gen11_dsi_gate_clocks(encoder);
} }