ath10k: Add hw param for 64-bit address support
WCN3990 target supports 37-bit addressing mode. In order to accommodate extended address support, add hw param to indicate if the target supports addressing above 32-bits. Signed-off-by: Rakesh Pillai <pillair@qti.qualcomm.com> Signed-off-by: Govind Singh <govinds@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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@ -78,6 +78,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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.target_64bit = false,
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},
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{
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.id = QCA9887_HW_1_0_VERSION,
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@ -105,6 +106,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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.target_64bit = false,
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},
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{
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.id = QCA6174_HW_2_1_VERSION,
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@ -131,6 +133,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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.target_64bit = false,
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},
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{
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.id = QCA6174_HW_2_1_VERSION,
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@ -157,6 +160,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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.target_64bit = false,
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},
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{
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.id = QCA6174_HW_3_0_VERSION,
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@ -183,6 +187,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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.target_64bit = false,
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},
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{
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.id = QCA6174_HW_3_2_VERSION,
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@ -212,6 +217,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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.target_64bit = false,
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},
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{
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.id = QCA99X0_HW_2_0_DEV_VERSION,
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@ -244,6 +250,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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.target_64bit = false,
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},
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{
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.id = QCA9984_HW_1_0_DEV_VERSION,
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@ -281,6 +288,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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.target_64bit = false,
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},
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{
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.id = QCA9888_HW_2_0_DEV_VERSION,
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@ -317,6 +325,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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.target_64bit = false,
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},
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{
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.id = QCA9377_HW_1_0_DEV_VERSION,
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@ -343,6 +352,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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.target_64bit = false,
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},
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{
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.id = QCA9377_HW_1_1_DEV_VERSION,
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@ -371,6 +381,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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.target_64bit = false,
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},
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{
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.id = QCA4019_HW_1_0_DEV_VERSION,
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@ -404,6 +415,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_peers = TARGET_TLV_NUM_PEERS,
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.ast_skid_limit = 0x10,
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.num_wds_entries = 0x20,
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.target_64bit = false,
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},
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{
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.id = WCN3990_HW_1_0_DEV_VERSION,
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@ -422,6 +434,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.num_peers = TARGET_HL_10_TLV_NUM_PEERS,
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.ast_skid_limit = TARGET_HL_10_TLV_AST_SKID_LIMIT,
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.num_wds_entries = TARGET_HL_10_TLV_NUM_WDS_ENTRIES,
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.target_64bit = true,
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},
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};
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@ -561,6 +561,9 @@ struct ath10k_hw_params {
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u32 num_peers;
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u32 ast_skid_limit;
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u32 num_wds_entries;
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/* Targets supporting physical addressing capability above 32-bits */
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bool target_64bit;
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};
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struct htt_rx_desc;
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