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clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6

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The pll6 has a /4 output that is used as an input to the ahb mux clock.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai 2015-03-25 01:22:08 +08:00 committed by Maxime Ripard
parent 934fe5f48a
commit f101796966
1 changed files with 2 additions and 1 deletions
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3
drivers/clk/sunxi/clk-sunxi.c
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@ -1088,11 +1088,12 @@ static const struct divs_data pll5_divs_data __initconst = {
static const struct divs_data pll6_divs_data __initconst = { static const struct divs_data pll6_divs_data __initconst = {
.factors = &sun4i_pll6_data, .factors = &sun4i_pll6_data,
.ndivs = 3, .ndivs = 4,
.div = { .div = {
{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
{ .fixed = 2 }, /* P, other */ { .fixed = 2 }, /* P, other */
{ .self = 1 }, /* base factor clock, 2x */ { .self = 1 }, /* base factor clock, 2x */
{ .fixed = 4 }, /* pll6 / 4, used as ahb input */
} }
}; };