forked from Minki/linux
regulator: mt6366: Add support for MT6366 regulator
The MT6366 is a regulator found on boards based on MediaTek MT8186 and probably other SoCs. It is a so called pmic and connects as a slave to SoC using SPI, wrapped inside the pmic-wrapper. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Link: https://lore.kernel.org/r/20220401080212.27383-2-johnson.wang@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Johnson Wang
Mark Brown
parent
f704882033
commit
f0e3c6261a
@ -130,6 +130,102 @@ struct mt6358_regulator_info {
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.qi = BIT(15), \
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}
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#define MT6366_BUCK(match, vreg, min, max, step, \
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volt_ranges, vosel_mask, _da_vsel_reg, _da_vsel_mask, \
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_modeset_reg, _modeset_shift) \
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[MT6366_ID_##vreg] = { \
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.desc = { \
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.name = #vreg, \
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.of_match = of_match_ptr(match), \
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.ops = &mt6358_volt_range_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = MT6366_ID_##vreg, \
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.owner = THIS_MODULE, \
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.n_voltages = ((max) - (min)) / (step) + 1, \
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.linear_ranges = volt_ranges, \
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.n_linear_ranges = ARRAY_SIZE(volt_ranges), \
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.vsel_reg = MT6358_BUCK_##vreg##_ELR0, \
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.vsel_mask = vosel_mask, \
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.enable_reg = MT6358_BUCK_##vreg##_CON0, \
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.enable_mask = BIT(0), \
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.of_map_mode = mt6358_map_mode, \
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}, \
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.status_reg = MT6358_BUCK_##vreg##_DBG1, \
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.qi = BIT(0), \
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.da_vsel_reg = _da_vsel_reg, \
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.da_vsel_mask = _da_vsel_mask, \
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.modeset_reg = _modeset_reg, \
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.modeset_mask = BIT(_modeset_shift), \
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}
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#define MT6366_LDO(match, vreg, ldo_volt_table, \
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ldo_index_table, enreg, enbit, vosel, \
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vosel_mask) \
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[MT6366_ID_##vreg] = { \
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.desc = { \
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.name = #vreg, \
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.of_match = of_match_ptr(match), \
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.ops = &mt6358_volt_table_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = MT6366_ID_##vreg, \
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.owner = THIS_MODULE, \
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.n_voltages = ARRAY_SIZE(ldo_volt_table), \
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.volt_table = ldo_volt_table, \
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.vsel_reg = vosel, \
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.vsel_mask = vosel_mask, \
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.enable_reg = enreg, \
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.enable_mask = BIT(enbit), \
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}, \
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.status_reg = MT6358_LDO_##vreg##_CON1, \
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.qi = BIT(15), \
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.index_table = ldo_index_table, \
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.n_table = ARRAY_SIZE(ldo_index_table), \
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}
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#define MT6366_LDO1(match, vreg, min, max, step, \
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volt_ranges, _da_vsel_reg, _da_vsel_mask, \
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vosel, vosel_mask) \
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[MT6366_ID_##vreg] = { \
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.desc = { \
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.name = #vreg, \
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.of_match = of_match_ptr(match), \
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.ops = &mt6358_volt_range_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = MT6366_ID_##vreg, \
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.owner = THIS_MODULE, \
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.n_voltages = ((max) - (min)) / (step) + 1, \
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.linear_ranges = volt_ranges, \
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.n_linear_ranges = ARRAY_SIZE(volt_ranges), \
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.vsel_reg = vosel, \
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.vsel_mask = vosel_mask, \
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.enable_reg = MT6358_LDO_##vreg##_CON0, \
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.enable_mask = BIT(0), \
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}, \
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.da_vsel_reg = _da_vsel_reg, \
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.da_vsel_mask = _da_vsel_mask, \
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.status_reg = MT6358_LDO_##vreg##_DBG1, \
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.qi = BIT(0), \
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}
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#define MT6366_REG_FIXED(match, vreg, \
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enreg, enbit, volt) \
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[MT6366_ID_##vreg] = { \
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.desc = { \
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.name = #vreg, \
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.of_match = of_match_ptr(match), \
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.ops = &mt6358_volt_fixed_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = MT6366_ID_##vreg, \
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.owner = THIS_MODULE, \
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.n_voltages = 1, \
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.enable_reg = enreg, \
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.enable_mask = BIT(enbit), \
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.min_uV = volt, \
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}, \
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.status_reg = MT6358_LDO_##vreg##_CON1, \
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.qi = BIT(15), \
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}
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static const struct linear_range buck_volt_range1[] = {
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REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
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};
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@ -409,6 +505,9 @@ static struct mt6358_regulator_info mt6358_regulators[] = {
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MT6358_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250,
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buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f,
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MT6358_VCORE_VGPU_ANA_CON0, 1),
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MT6358_BUCK("buck_vcore_sshub", VCORE_SSHUB, 500000, 1293750, 6250,
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buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_SSHUB_ELR0, 0x7f,
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MT6358_VCORE_VGPU_ANA_CON0, 1),
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MT6358_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
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buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f,
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MT6358_VPA_ANA_CON0, 3),
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@ -488,6 +587,10 @@ static struct mt6358_regulator_info mt6358_regulators[] = {
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MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250,
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buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00,
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MT6358_LDO_VSRAM_CON2, 0x7f),
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MT6358_LDO1("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, 500000,
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1293750, 6250, buck_volt_range1,
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MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f,
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MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f),
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MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250,
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buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00,
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MT6358_LDO_VSRAM_CON3, 0x7f),
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@ -496,24 +599,124 @@ static struct mt6358_regulator_info mt6358_regulators[] = {
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MT6358_LDO_VSRAM_CON1, 0x7f),
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};
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/* The array is indexed by id(MT6366_ID_XXX) */
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static struct mt6358_regulator_info mt6366_regulators[] = {
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MT6366_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500,
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buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f,
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MT6358_VDRAM1_ANA_CON0, 8),
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MT6366_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250,
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buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f,
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MT6358_VCORE_VGPU_ANA_CON0, 1),
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MT6366_BUCK("buck_vcore_sshub", VCORE_SSHUB, 500000, 1293750, 6250,
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buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_SSHUB_ELR0, 0x7f,
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MT6358_VCORE_VGPU_ANA_CON0, 1),
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MT6366_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
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buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f,
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MT6358_VPA_ANA_CON0, 3),
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MT6366_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250,
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buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f,
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MT6358_VPROC_ANA_CON0, 1),
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MT6366_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250,
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buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f,
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MT6358_VPROC_ANA_CON0, 2),
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MT6366_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250,
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buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f,
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MT6358_VCORE_VGPU_ANA_CON0, 2),
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MT6366_BUCK("buck_vs2", VS2, 500000, 2087500, 12500,
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buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f,
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MT6358_VS2_ANA_CON0, 8),
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MT6366_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250,
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buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f,
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MT6358_VMODEM_ANA_CON0, 8),
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MT6366_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500,
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buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f,
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MT6358_VS1_ANA_CON0, 8),
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MT6366_REG_FIXED("ldo_vrf12", VRF12,
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MT6358_LDO_VRF12_CON0, 0, 1200000),
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MT6366_REG_FIXED("ldo_vio18", VIO18,
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MT6358_LDO_VIO18_CON0, 0, 1800000),
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MT6366_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
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MT6366_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
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MT6366_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
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MT6366_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
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MT6366_REG_FIXED("ldo_vaux18", VAUX18,
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MT6358_LDO_VAUX18_CON0, 0, 1800000),
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MT6366_REG_FIXED("ldo_vbif28", VBIF28,
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MT6358_LDO_VBIF28_CON0, 0, 2800000),
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MT6366_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
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MT6366_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
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MT6366_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
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MT6366_REG_FIXED("ldo_vaud28", VAUD28,
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MT6358_LDO_VAUD28_CON0, 0, 2800000),
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MT6366_LDO("ldo_vdram2", VDRAM2, vdram2_voltages, vdram2_idx,
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MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10),
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MT6366_LDO("ldo_vsim1", VSIM1, vsim_voltages, vsim_idx,
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MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
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MT6366_LDO("ldo_vibr", VIBR, vibr_voltages, vibr_idx,
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MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
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MT6366_LDO("ldo_vusb", VUSB, vusb_voltages, vusb_idx,
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MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
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MT6366_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, vefuse_idx,
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MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
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MT6366_LDO("ldo_vmch", VMCH, vmch_vemc_voltages, vmch_vemc_idx,
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MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
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MT6366_LDO("ldo_vemc", VEMC, vmch_vemc_voltages, vmch_vemc_idx,
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MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
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MT6366_LDO("ldo_vcn33_bt", VCN33_BT, vcn33_bt_wifi_voltages,
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vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_0,
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0, MT6358_VCN33_ANA_CON0, 0x300),
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MT6366_LDO("ldo_vcn33_wifi", VCN33_WIFI, vcn33_bt_wifi_voltages,
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vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_1,
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0, MT6358_VCN33_ANA_CON0, 0x300),
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MT6366_LDO("ldo_vmc", VMC, vmc_voltages, vmc_idx,
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MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
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MT6366_LDO("ldo_vsim2", VSIM2, vsim_voltages, vsim_idx,
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MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
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MT6366_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250,
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buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00,
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MT6358_LDO_VSRAM_CON0, 0x7f),
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MT6366_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250,
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buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00,
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MT6358_LDO_VSRAM_CON2, 0x7f),
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MT6366_LDO1("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, 500000,
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1293750, 6250, buck_volt_range1,
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MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f,
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MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f),
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MT6366_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250,
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buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00,
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MT6358_LDO_VSRAM_CON3, 0x7f),
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MT6366_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250,
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buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00,
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MT6358_LDO_VSRAM_CON1, 0x7f),
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};
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static int mt6358_regulator_probe(struct platform_device *pdev)
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{
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struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
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struct regulator_config config = {};
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struct regulator_dev *rdev;
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int i;
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struct mt6358_regulator_info *mt6358_info;
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int i, max_regulator;
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for (i = 0; i < MT6358_MAX_REGULATOR; i++) {
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if (mt6397->chip_id == MT6366_CHIP_ID) {
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max_regulator = MT6366_MAX_REGULATOR;
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mt6358_info = mt6366_regulators;
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} else {
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max_regulator = MT6358_MAX_REGULATOR;
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mt6358_info = mt6358_regulators;
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}
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for (i = 0; i < max_regulator; i++) {
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config.dev = &pdev->dev;
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config.driver_data = &mt6358_regulators[i];
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config.driver_data = &mt6358_info[i];
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config.regmap = mt6397->regmap;
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rdev = devm_regulator_register(&pdev->dev,
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&mt6358_regulators[i].desc,
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&mt6358_info[i].desc,
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&config);
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if (IS_ERR(rdev)) {
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dev_err(&pdev->dev, "failed to register %s\n",
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mt6358_regulators[i].desc.name);
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mt6358_info[i].desc.name);
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return PTR_ERR(rdev);
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}
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}
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@ -48,9 +48,54 @@ enum {
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MT6358_ID_VLDO28,
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MT6358_ID_VAUD28,
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MT6358_ID_VSIM2,
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MT6358_ID_VCORE_SSHUB,
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MT6358_ID_VSRAM_OTHERS_SSHUB,
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MT6358_ID_RG_MAX,
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};
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enum {
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MT6366_ID_VDRAM1 = 0,
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MT6366_ID_VCORE,
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MT6366_ID_VPA,
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MT6366_ID_VPROC11,
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MT6366_ID_VPROC12,
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MT6366_ID_VGPU,
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MT6366_ID_VS2,
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MT6366_ID_VMODEM,
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MT6366_ID_VS1,
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MT6366_ID_VDRAM2,
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MT6366_ID_VSIM1,
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MT6366_ID_VIBR,
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MT6366_ID_VRF12,
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MT6366_ID_VIO18,
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MT6366_ID_VUSB,
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MT6366_ID_VCN18,
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MT6366_ID_VFE28,
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MT6366_ID_VSRAM_PROC11,
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MT6366_ID_VCN28,
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MT6366_ID_VSRAM_OTHERS,
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MT6366_ID_VSRAM_GPU,
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MT6366_ID_VXO22,
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MT6366_ID_VEFUSE,
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MT6366_ID_VAUX18,
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MT6366_ID_VMCH,
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MT6366_ID_VBIF28,
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MT6366_ID_VSRAM_PROC12,
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MT6366_ID_VEMC,
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MT6366_ID_VIO28,
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MT6366_ID_VA12,
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MT6366_ID_VRF18,
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MT6366_ID_VCN33_BT,
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MT6366_ID_VCN33_WIFI,
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MT6366_ID_VMC,
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MT6366_ID_VAUD28,
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MT6366_ID_VSIM2,
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MT6366_ID_VCORE_SSHUB,
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MT6366_ID_VSRAM_OTHERS_SSHUB,
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MT6366_ID_RG_MAX,
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};
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#define MT6358_MAX_REGULATOR MT6358_ID_RG_MAX
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#define MT6366_MAX_REGULATOR MT6366_ID_RG_MAX
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#endif /* __LINUX_REGULATOR_MT6358_H */
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