forked from Minki/linux
irqchip: s3c24xx: add devicetree support
Add the necessary code to initialize the interrupt controller thru devicetree data using the irqchip infrastructure. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Heiko Stuebner
Kukjin Kim
parent
f5a2552450
commit
f0774d41da
@ -0,0 +1,53 @@
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Samsung S3C24XX Interrupt Controllers
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The S3C24XX SoCs contain a custom set of interrupt controllers providing a
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varying number of interrupt sources. The set consists of a main- and sub-
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controller and on newer SoCs even a second main controller.
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Required properties:
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- compatible: Compatible property value should be "samsung,s3c2410-irq"
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for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
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- reg: Physical base address of the controller and length of memory mapped
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region.
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The value shall be 4 and interrupt descriptor shall
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have the following format:
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<ctrl_num parent_irq ctrl_irq type>
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ctrl_num contains the controller to use:
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- 0 ... main controller
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- 1 ... sub controller
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- 2 ... second main controller on s3c2416 and s3c2450
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parent_irq contains the parent bit in the main controller and will be
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ignored in main controllers
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ctrl_irq contains the interrupt bit of the controller
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type contains the trigger type to use
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Example:
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interrupt-controller@4a000000 {
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compatible = "samsung,s3c2410-irq";
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reg = <0x4a000000 0x100>;
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interrupt-controller;
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#interrupt-cells=<4>;
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};
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[...]
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serial@50000000 {
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compatible = "samsung,s3c2410-uart";
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reg = <0x50000000 0x4000>;
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interrupt-parent = <&subintc>;
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interrupts = <1 28 0 4>, <1 28 1 4>;
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};
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rtc@57000000 {
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compatible = "samsung,s3c2410-rtc";
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reg = <0x57000000 0x100>;
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interrupt-parent = <&intc>;
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interrupts = <0 30 0 3>, <0 8 0 3>;
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};
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@ -25,6 +25,9 @@
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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@ -36,6 +39,8 @@
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#include <plat/regs-irqtype.h>
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#include <plat/pm.h>
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#include "irqchip.h"
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#define S3C_IRQTYPE_NONE 0
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#define S3C_IRQTYPE_EINT 1
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#define S3C_IRQTYPE_EDGE 2
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@ -94,7 +99,10 @@ static void s3c_irq_mask(struct irq_data *data)
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if (parent_intc) {
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parent_data = &parent_intc->irqs[irq_data->parent_irq];
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/* check to see if we need to mask the parent IRQ */
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/* check to see if we need to mask the parent IRQ
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* The parent_irq is always in main_intc, so the hwirq
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* for find_mapping does not need an offset in any case.
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*/
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if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
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irqno = irq_find_mapping(parent_intc->domain,
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irq_data->parent_irq);
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@ -294,10 +302,18 @@ static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
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struct s3c_irq_intc *intc = irq_data->intc;
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struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
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unsigned long src;
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unsigned long msk;
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unsigned int n;
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unsigned int offset;
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/* we're using individual domains for the non-dt case
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* and one big domain for the dt case where the subintc
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* starts at hwirq number 32.
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*/
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offset = (intc->domain->of_node) ? 32 : 0;
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chained_irq_enter(chip, desc);
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@ -310,14 +326,15 @@ static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
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while (src) {
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n = __ffs(src);
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src &= ~(1 << n);
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generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
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irq = irq_find_mapping(sub_intc->domain, offset + n);
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generic_handle_irq(irq);
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}
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chained_irq_exit(chip, desc);
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}
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static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
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struct pt_regs *regs)
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struct pt_regs *regs, int intc_offset)
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{
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int pnd;
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int offset;
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@ -327,6 +344,10 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
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if (!pnd)
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return false;
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/* non-dt machines use individual domains */
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if (!intc->domain->of_node)
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intc_offset = 0;
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/* We have a problem that the INTOFFSET register does not always
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* show one interrupt. Occasionally we get two interrupts through
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* the prioritiser, and this causes the INTOFFSET register to show
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@ -343,7 +364,7 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
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if (!(pnd & (1 << offset)))
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offset = __ffs(pnd);
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irq = irq_find_mapping(intc->domain, offset);
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irq = irq_find_mapping(intc->domain, intc_offset + offset);
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handle_IRQ(irq, regs);
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return true;
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}
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@ -352,11 +373,11 @@ asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
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{
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do {
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if (likely(s3c_intc[0]))
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if (s3c24xx_handle_intc(s3c_intc[0], regs))
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if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
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continue;
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if (s3c_intc[2])
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if (s3c24xx_handle_intc(s3c_intc[2], regs))
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if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
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continue;
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break;
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@ -1134,3 +1155,201 @@ void __init s3c2443_init_irq(void)
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s3c_intc[0], 0x4a000018);
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}
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#endif
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#ifdef CONFIG_OF
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static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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unsigned int ctrl_num = hw / 32;
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unsigned int intc_hw = hw % 32;
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struct s3c_irq_intc *intc = s3c_intc[ctrl_num];
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struct s3c_irq_intc *parent_intc = intc->parent;
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struct s3c_irq_data *irq_data = &intc->irqs[intc_hw];
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/* attach controller pointer to irq_data */
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irq_data->intc = intc;
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irq_data->offset = intc_hw;
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if (!parent_intc)
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irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq);
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else
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irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
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handle_edge_irq);
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irq_set_chip_data(virq, irq_data);
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set_irq_flags(virq, IRQF_VALID);
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return 0;
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}
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/* Translate our of irq notation
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* format: <ctrl_num ctrl_irq parent_irq type>
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*/
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static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_type)
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{
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struct s3c_irq_intc *intc;
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struct s3c_irq_intc *parent_intc;
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struct s3c_irq_data *irq_data;
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struct s3c_irq_data *parent_irq_data;
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int irqno;
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if (WARN_ON(intsize < 4))
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return -EINVAL;
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if (intspec[0] > 2 || !s3c_intc[intspec[0]]) {
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pr_err("controller number %d invalid\n", intspec[0]);
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return -EINVAL;
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}
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intc = s3c_intc[intspec[0]];
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*out_hwirq = intspec[0] * 32 + intspec[2];
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*out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
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parent_intc = intc->parent;
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if (parent_intc) {
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irq_data = &intc->irqs[intspec[2]];
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irq_data->parent_irq = intspec[1];
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parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
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parent_irq_data->sub_intc = intc;
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parent_irq_data->sub_bits |= (1UL << intspec[2]);
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/* parent_intc is always s3c_intc[0], so no offset */
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irqno = irq_create_mapping(parent_intc->domain, intspec[1]);
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if (irqno < 0) {
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pr_err("irq: could not map parent interrupt\n");
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return irqno;
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}
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irq_set_chained_handler(irqno, s3c_irq_demux);
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}
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return 0;
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}
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static struct irq_domain_ops s3c24xx_irq_ops_of = {
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.map = s3c24xx_irq_map_of,
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.xlate = s3c24xx_irq_xlate_of,
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};
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struct s3c24xx_irq_of_ctrl {
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char *name;
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unsigned long offset;
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struct s3c_irq_intc **handle;
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struct s3c_irq_intc **parent;
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struct irq_domain_ops *ops;
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};
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static int __init s3c_init_intc_of(struct device_node *np,
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struct device_node *interrupt_parent,
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struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl)
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{
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struct s3c_irq_intc *intc;
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struct s3c24xx_irq_of_ctrl *ctrl;
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struct irq_domain *domain;
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void __iomem *reg_base;
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int i;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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pr_err("irq-s3c24xx: could not map irq registers\n");
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return -EINVAL;
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}
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domain = irq_domain_add_linear(np, num_ctrl * 32,
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&s3c24xx_irq_ops_of, NULL);
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if (!domain) {
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pr_err("irq: could not create irq-domain\n");
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return -EINVAL;
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}
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for (i = 0; i < num_ctrl; i++) {
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ctrl = &s3c_ctrl[i];
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pr_debug("irq: found controller %s\n", ctrl->name);
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intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
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if (!intc)
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return -ENOMEM;
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intc->domain = domain;
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intc->irqs = kzalloc(sizeof(struct s3c_irq_data) * 32,
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GFP_KERNEL);
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if (!intc->irqs) {
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kfree(intc);
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return -ENOMEM;
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}
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if (ctrl->parent) {
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intc->reg_pending = reg_base + ctrl->offset;
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intc->reg_mask = reg_base + ctrl->offset + 0x4;
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if (*(ctrl->parent)) {
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intc->parent = *(ctrl->parent);
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} else {
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pr_warn("irq: parent of %s missing\n",
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ctrl->name);
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kfree(intc->irqs);
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kfree(intc);
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continue;
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}
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} else {
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intc->reg_pending = reg_base + ctrl->offset;
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intc->reg_mask = reg_base + ctrl->offset + 0x08;
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intc->reg_intpnd = reg_base + ctrl->offset + 0x10;
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}
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s3c24xx_clear_intc(intc);
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s3c_intc[i] = intc;
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}
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set_handle_irq(s3c24xx_handle_irq);
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return 0;
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}
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static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
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{
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.name = "intc",
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.offset = 0,
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}, {
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.name = "subintc",
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.offset = 0x18,
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.parent = &s3c_intc[0],
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}
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};
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int __init s3c2410_init_intc_of(struct device_node *np,
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struct device_node *interrupt_parent,
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struct s3c24xx_irq_of_ctrl *ctrl, int num_ctrl)
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{
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return s3c_init_intc_of(np, interrupt_parent,
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s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl));
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}
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IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
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static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
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{
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.name = "intc",
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.offset = 0,
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}, {
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.name = "subintc",
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.offset = 0x18,
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.parent = &s3c_intc[0],
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}, {
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.name = "intc2",
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.offset = 0x40,
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}
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};
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int __init s3c2416_init_intc_of(struct device_node *np,
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struct device_node *interrupt_parent,
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struct s3c24xx_irq_of_ctrl *ctrl, int num_ctrl)
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{
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return s3c_init_intc_of(np, interrupt_parent,
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s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl));
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}
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IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);
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#endif
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