forked from Minki/linux
clk: shmobile: rz: Add CPG/MSTP Clock Domain support
Add Clock Domain support to the RZ Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume. SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock should be tagged in DT with a proper "power-domains" property. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -2,6 +2,8 @@
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The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
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The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
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CPU and GPU clocks, and several fixed ratio dividers.
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CPU and GPU clocks, and several fixed ratio dividers.
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The CPG also provides a Clock Domain for SoC devices, in combination with the
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CPG Module Stop (MSTP) Clocks.
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Required Properties:
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Required Properties:
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@ -14,10 +16,18 @@ Required Properties:
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- #clock-cells: Must be 1
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "pll",
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- clock-output-names: The names of the clocks. Supported clocks are "pll",
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"i", and "g"
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"i", and "g"
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- #power-domain-cells: Must be 0
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SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
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through an MSTP clock should refer to the CPG device node in their
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"power-domains" property, as documented by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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Example
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Examples
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-------
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--------
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- CPG device node:
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cpg_clocks: cpg_clocks@fcfe0000 {
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cpg_clocks: cpg_clocks@fcfe0000 {
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#clock-cells = <1>;
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#clock-cells = <1>;
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@ -26,4 +36,19 @@ Example
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reg = <0xfcfe0000 0x18>;
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reg = <0xfcfe0000 0x18>;
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clocks = <&extal_clk>, <&usb_x1_clk>;
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clocks = <&extal_clk>, <&usb_x1_clk>;
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clock-output-names = "pll", "i", "g";
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clock-output-names = "pll", "i", "g";
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#power-domain-cells = <0>;
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};
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- CPG/MSTP Clock Domain member device node:
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mtu2: timer@fcff0000 {
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compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
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reg = <0xfcff0000 0x400>;
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tgi0a";
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clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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};
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@ -51,6 +51,7 @@ config ARCH_EMEV2
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config ARCH_R7S72100
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config ARCH_R7S72100
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bool "RZ/A1H (R7S72100)"
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bool "RZ/A1H (R7S72100)"
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select PM_GENERIC_DOMAINS if PM
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select SYS_SUPPORTS_SH_MTU2
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select SYS_SUPPORTS_SH_MTU2
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config ARCH_R8A73A4
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config ARCH_R8A73A4
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*/
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/shmobile.h>
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of.h>
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@ -99,5 +100,7 @@ static void __init rz_cpg_clocks_init(struct device_node *np)
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}
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}
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of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
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of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
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cpg_mstp_add_clk_domain(np);
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}
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}
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CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
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CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
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