Staging: dt3155: fix coding style issues in dt3155_io.c
This fixes up the sparse and coding style issues found in the dt3155_io.c file. No code is changed, only formatting and removing unused code. Cc: Scott Smedley <ss@aao.gov.au> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Greg Kroah-Hartman
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@ -1,236 +1,175 @@
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/*
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* Copyright 1996,2002,2005 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan,
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* Jason Lapenta, Scott Smedley
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*
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* This file is part of the DT3155 Device Driver.
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*
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* The DT3155 Device Driver is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* The DT3155 Device Driver is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
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* Public License for more details.
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*/
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Copyright 1996,2002,2005 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan,
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Jason Lapenta, Scott Smedley
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This file is part of the DT3155 Device Driver.
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The DT3155 Device Driver is free software; you can redistribute it
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and/or modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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The DT3155 Device Driver is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied warranty
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of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with the DT3155 Device Driver; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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MA 02111-1307 USA
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-- Changes --
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Date Programmer Description of changes made
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-------------------------------------------------------------------
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10-Oct-2001 SS port to 2.4 kernel.
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24-Jul-2002 SS GPL licence.
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26-Jul-2002 SS Bug fix: timing logic was wrong.
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08-Aug-2005 SS port to 2.6 kernel.
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*/
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/* This file provides some basic register io routines. It is modified
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from demo code provided by Data Translations. */
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#ifdef __KERNEL__
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#include <asm/delay.h>
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#endif
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#if 0
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#include <sys/param.h>
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#include <sys/time.h>
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#include <unistd.h>
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#endif
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/*
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* This file provides some basic register io routines. It is modified from
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* demo code provided by Data Translations.
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*/
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#include <linux/delay.h>
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#include "dt3155.h"
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#include "dt3155_io.h"
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#include "dt3155_drv.h"
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#ifndef __KERNEL__
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#include <stdio.h>
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#endif
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/****** local copies of board's 32 bit registers ******/
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u64 even_dma_start_r; /* bit 0 should always be 0 */
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u64 odd_dma_start_r; /* .. */
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u64 even_dma_stride_r; /* bits 0&1 should always be 0 */
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u64 odd_dma_stride_r; /* .. */
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u64 even_pixel_fmt_r;
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u64 odd_pixel_fmt_r;
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u64 even_dma_start_r; /* bit 0 should always be 0 */
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u64 odd_dma_start_r; /* .. */
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u64 even_dma_stride_r; /* bits 0&1 should always be 0 */
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u64 odd_dma_stride_r; /* .. */
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u64 even_pixel_fmt_r;
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u64 odd_pixel_fmt_r;
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FIFO_TRIGGER_R fifo_trigger_r;
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XFER_MODE_R xfer_mode_r;
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CSR1_R csr1_r;
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RETRY_WAIT_CNT_R retry_wait_cnt_r;
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INT_CSR_R int_csr_r;
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FIFO_TRIGGER_R fifo_trigger_r;
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XFER_MODE_R xfer_mode_r;
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CSR1_R csr1_r;
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RETRY_WAIT_CNT_R retry_wait_cnt_r;
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INT_CSR_R int_csr_r;
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u64 even_fld_mask_r;
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u64 odd_fld_mask_r;
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u64 even_fld_mask_r;
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u64 odd_fld_mask_r;
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MASK_LENGTH_R mask_length_r;
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FIFO_FLAG_CNT_R fifo_flag_cnt_r;
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IIC_CLK_DUR_R iic_clk_dur_r;
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IIC_CSR1_R iic_csr1_r;
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IIC_CSR2_R iic_csr2_r;
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DMA_UPPER_LMT_R even_dma_upper_lmt_r;
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DMA_UPPER_LMT_R odd_dma_upper_lmt_r;
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MASK_LENGTH_R mask_length_r;
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FIFO_FLAG_CNT_R fifo_flag_cnt_r;
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IIC_CLK_DUR_R iic_clk_dur_r;
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IIC_CSR1_R iic_csr1_r;
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IIC_CSR2_R iic_csr2_r;
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DMA_UPPER_LMT_R even_dma_upper_lmt_r;
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DMA_UPPER_LMT_R odd_dma_upper_lmt_r;
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/******** local copies of board's 8 bit I2C registers ******/
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I2C_CSR2 i2c_csr2;
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I2C_EVEN_CSR i2c_even_csr;
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I2C_ODD_CSR i2c_odd_csr;
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I2C_CONFIG i2c_config;
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u8 i2c_dt_id;
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u8 i2c_x_clip_start;
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u8 i2c_y_clip_start;
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u8 i2c_x_clip_end;
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u8 i2c_y_clip_end;
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u8 i2c_ad_addr;
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u8 i2c_ad_lut;
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I2C_AD_CMD i2c_ad_cmd;
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u8 i2c_dig_out;
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u8 i2c_pm_lut_addr;
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u8 i2c_pm_lut_data;
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I2C_CSR2 i2c_csr2;
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I2C_EVEN_CSR i2c_even_csr;
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I2C_ODD_CSR i2c_odd_csr;
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I2C_CONFIG i2c_config;
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u8 i2c_dt_id;
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u8 i2c_x_clip_start;
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u8 i2c_y_clip_start;
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u8 i2c_x_clip_end;
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u8 i2c_y_clip_end;
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u8 i2c_ad_addr;
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u8 i2c_ad_lut;
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I2C_AD_CMD i2c_ad_cmd;
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u8 i2c_dig_out;
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u8 i2c_pm_lut_addr;
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u8 i2c_pm_lut_data;
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// return the time difference (in microseconds) b/w <a> & <b>.
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long elapsed2 (const struct timeval *pStart, const struct timeval *pEnd)
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/*
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* wait_ibsyclr()
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*
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* This function handles read/write timing and r/w timeout error
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*
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* Returns TRUE if NEW_CYCLE clears
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* Returns FALSE if NEW_CYCLE doesn't clear in roughly 3 msecs, otherwise
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* returns 0
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*/
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static int wait_ibsyclr(u8 *lpReg)
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{
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long i = (pEnd->tv_sec - pStart->tv_sec) * 1000000;
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i += pEnd->tv_usec - pStart->tv_usec;
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return i;
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/* wait 100 microseconds */
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udelay(100L);
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/* __delay(loops_per_sec/10000); */
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if (iic_csr2_r.fld.NEW_CYCLE) {
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/* if NEW_CYCLE didn't clear */
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/* TIMEOUT ERROR */
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dt3155_errno = DT_ERR_I2C_TIMEOUT;
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return FALSE;
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} else
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return TRUE; /* no error */
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}
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/***********************************************************************
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wait_ibsyclr()
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This function handles read/write timing and r/w timeout error
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Returns TRUE if NEW_CYCLE clears
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Returns FALSE if NEW_CYCLE doesn't clear in roughly 3 msecs,
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otherwise returns 0
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***********************************************************************/
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int wait_ibsyclr(u8 * lpReg)
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/*
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* WriteI2C()
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*
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* This function handles writing to 8-bit DT3155 registers
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*
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* 1st parameter is pointer to 32-bit register base address
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* 2nd parameter is reg. index;
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* 3rd is value to be written
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*
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* Returns TRUE - Successful completion
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* FALSE - Timeout error - cycle did not complete!
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*/
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int WriteI2C(u8 *lpReg, u_short wIregIndex, u8 byVal)
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{
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/* wait 100 microseconds */
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int writestat; /* status for return */
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#ifdef __KERNEL__
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udelay(100L);
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/* __delay(loops_per_sec/10000); */
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if (iic_csr2_r.fld.NEW_CYCLE )
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{ /* if NEW_CYCLE didn't clear */
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/* TIMEOUT ERROR */
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dt3155_errno = DT_ERR_I2C_TIMEOUT;
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return FALSE;
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}
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else
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return TRUE; /* no error */
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#else
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struct timeval StartTime;
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struct timeval EndTime;
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/* read 32 bit IIC_CSR2 register data into union */
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const int to_3ms = 3000; /* time out of 3ms = 3000us */
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ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg);
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gettimeofday( &StartTime, NULL );
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do {
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/* get new iic_csr2 value: */
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ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg);
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gettimeofday( &EndTime, NULL );
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}
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while ((elapsed2(&StartTime, &EndTime) < to_3ms) && iic_csr2_r.fld.NEW_CYCLE);
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/* for write operation */
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iic_csr2_r.fld.DIR_RD = 0;
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/* I2C address of I2C register: */
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iic_csr2_r.fld.DIR_ADDR = wIregIndex;
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/* 8 bit data to be written to I2C reg */
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iic_csr2_r.fld.DIR_WR_DATA = byVal;
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/* will start a direct I2C cycle: */
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iic_csr2_r.fld.NEW_CYCLE = 1;
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if (iic_csr2_r.fld.NEW_CYCLE )
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{ /* if NEW_CYCLE didn't clear */
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printf("Timed out waiting for NEW_CYCLE to clear!");
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return FALSE;
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}
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else
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return TRUE; /* no error */
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#endif
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/* xfer union data into 32 bit IIC_CSR2 register */
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WriteMReg((lpReg + IIC_CSR2), iic_csr2_r.reg);
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/* wait for IIC cycle to finish */
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writestat = wait_ibsyclr(lpReg);
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return writestat;
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}
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/***********************************************************************
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WriteI2C()
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This function handles writing to 8-bit DT3155 registers
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1st parameter is pointer to 32-bit register base address
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2nd parameter is reg. index;
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3rd is value to be written
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Returns TRUE - Successful completion
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FALSE - Timeout error - cycle did not complete!
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***********************************************************************/
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int WriteI2C (u8 * lpReg, u_short wIregIndex, u8 byVal)
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/*
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* ReadI2C()
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*
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* This function handles reading from 8-bit DT3155 registers
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*
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* 1st parameter is pointer to 32-bit register base address
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* 2nd parameter is reg. index;
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* 3rd is adrs of value to be read
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*
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* Returns TRUE - Successful completion
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* FALSE - Timeout error - cycle did not complete!
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*/
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int ReadI2C(u8 *lpReg, u_short wIregIndex, u8 *byVal)
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{
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int writestat; /* status for return */
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int writestat; /* status for return */
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/* read 32 bit IIC_CSR2 register data into union */
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/* read 32 bit IIC_CSR2 register data into union */
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ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg);
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ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg);
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/* for read operation */
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iic_csr2_r.fld.DIR_RD = 1;
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iic_csr2_r.fld.DIR_RD = 0; /* for write operation */
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iic_csr2_r.fld.DIR_ADDR = wIregIndex; /* I2C address of I2C register: */
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iic_csr2_r.fld.DIR_WR_DATA = byVal; /* 8 bit data to be written to I2C reg */
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iic_csr2_r.fld.NEW_CYCLE = 1; /* will start a direct I2C cycle: */
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/* I2C address of I2C register: */
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iic_csr2_r.fld.DIR_ADDR = wIregIndex;
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/* xfer union data into 32 bit IIC_CSR2 register */
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/* will start a direct I2C cycle: */
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iic_csr2_r.fld.NEW_CYCLE = 1;
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WriteMReg((lpReg + IIC_CSR2), iic_csr2_r.reg);
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/* xfer union's data into 32 bit IIC_CSR2 register */
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WriteMReg((lpReg + IIC_CSR2), iic_csr2_r.reg);
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/* wait for IIC cycle to finish */
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/* wait for IIC cycle to finish */
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writestat = wait_ibsyclr(lpReg);
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writestat = wait_ibsyclr( lpReg );
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return writestat; /* return with status */
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}
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/***********************************************************************
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ReadI2C()
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This function handles reading from 8-bit DT3155 registers
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1st parameter is pointer to 32-bit register base address
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2nd parameter is reg. index;
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3rd is adrs of value to be read
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Returns TRUE - Successful completion
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FALSE - Timeout error - cycle did not complete!
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***********************************************************************/
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int ReadI2C (u8 * lpReg, u_short wIregIndex, u8 * byVal)
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{
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int writestat; /* status for return */
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/* read 32 bit IIC_CSR2 register data into union */
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ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg);
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/* for read operation */
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iic_csr2_r.fld.DIR_RD = 1;
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/* I2C address of I2C register: */
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iic_csr2_r.fld.DIR_ADDR = wIregIndex;
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/* will start a direct I2C cycle: */
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iic_csr2_r.fld.NEW_CYCLE = 1;
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/* xfer union's data into 32 bit IIC_CSR2 register */
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WriteMReg((lpReg + IIC_CSR2), iic_csr2_r.reg);
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/* wait for IIC cycle to finish */
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writestat = wait_ibsyclr(lpReg);
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/* Next 2 commands read 32 bit IIC_CSR1 register's data into union */
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/* first read data is in IIC_CSR1 */
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ReadMReg((lpReg + IIC_CSR1), iic_csr1_r.reg);
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/* now get data u8 out of register */
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*byVal = (u8) iic_csr1_r.fld.RD_DATA;
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return writestat; /* return with status */
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/* Next 2 commands read 32 bit IIC_CSR1 register's data into union */
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/* first read data is in IIC_CSR1 */
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ReadMReg((lpReg + IIC_CSR1), iic_csr1_r.reg);
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/* now get data u8 out of register */
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*byVal = (u8) iic_csr1_r.fld.RD_DATA;
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return writestat;
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}
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