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x86: select x2apic ops in early apic probe only if x2apic mode is enabled

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If BIOS hands over the control to OS in legacy xapic mode, select
legacy xapic related ops in the early apic probe and shift to x2apic
ops later in the boot sequence, only after enabling x2apic mode.

If BIOS hands over the control in x2apic mode, select x2apic related
ops in the early apic probe.

This fixes the early boot panic, where we were selecting x2apic ops,
while the cpu is still in legacy xapic mode.

Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Cc: Yinghai Lu <yinghai@kernel.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Suresh Siddha 2009-02-21 14:23:21 -08:00 committed by Ingo Molnar
parent 9be1b56a3e
commit ef1f87aa7b
5 changed files with 18 additions and 21 deletions
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2
arch/x86/include/asm/apic.h
View File

@ -146,7 +146,7 @@ static inline u64 native_x2apic_icr_read(void)
return val;
}
extern int x2apic;
extern int x2apic, x2apic_phys;
extern void check_x2apic(void);
extern void enable_x2apic(void);
extern void enable_IR_x2apic(void);

9
arch/x86/kernel/apic/apic.c
View File

@ -1265,14 +1265,7 @@ void __cpuinit end_local_APIC_setup(void)
#ifdef CONFIG_X86_X2APIC
void check_x2apic(void)
{
int msr, msr2;
if (!cpu_has_x2apic)
return;
rdmsr(MSR_IA32_APICBASE, msr, msr2);
if (msr & X2APIC_ENABLE) {
if (x2apic_enabled()) {
pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
x2apic_preenabled = x2apic = 1;
}

13
arch/x86/kernel/apic/probe_64.c
View File

@ -50,9 +50,16 @@ static struct apic *apic_probe[] __initdata = {
void __init default_setup_apic_routing(void)
{
#ifdef CONFIG_X86_X2APIC
if (apic == &apic_x2apic_phys || apic == &apic_x2apic_cluster) {
if (!intr_remapping_enabled)
apic = &apic_flat;
if (x2apic && (apic != &apic_x2apic_phys &&
#ifdef CONFIG_X86_UV
apic != &apic_x2apic_uv_x &&
#endif
apic != &apic_x2apic_cluster)) {
if (x2apic_phys)
apic = &apic_x2apic_phys;
else
apic = &apic_x2apic_cluster;
printk(KERN_INFO "Setting APIC routing to %s\n", apic->name);
}
#endif

5
arch/x86/kernel/apic/x2apic_cluster.c
View File

@ -14,10 +14,7 @@ DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
if (cpu_has_x2apic)
return 1;
return 0;
return x2apic_enabled();
}
/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */

10
arch/x86/kernel/apic/x2apic_phys.c
View File

@ -10,7 +10,7 @@
#include <asm/apic.h>
#include <asm/ipi.h>
static int x2apic_phys;
int x2apic_phys;
static int set_x2apic_phys_mode(char *arg)
{
@ -21,10 +21,10 @@ early_param("x2apic_phys", set_x2apic_phys_mode);
static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
if (cpu_has_x2apic && x2apic_phys)
return 1;
return 0;
if (x2apic_phys)
return x2apic_enabled();
else
return 0;
}
/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */