bnx2x: Add timestamping and PTP hardware clock support
This adds a PHC to the bnx2x driver. Driver supports timestamping send/receive PTP packets, as well as adjusting the on-chip clock. The driver has been tested with linuxptp project. Signed-off-by: Michal Kalderon <Michal.Kalderon@qlogic.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com> Signed-off-by: Ariel Elior <Ariel.Elior@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michal Kalderon
committed by
David S. Miller
David S. Miller
parent
e42780b66a
commit
eeed018cbf
@@ -63,7 +63,6 @@
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#include "bnx2x_vfpf.h"
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#include "bnx2x_dcb.h"
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#include "bnx2x_sp.h"
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#include <linux/firmware.h>
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#include "bnx2x_fw_file_hdr.h"
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/* FW files */
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@@ -290,6 +289,8 @@ static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
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* General service functions
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****************************************************************************/
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static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
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static void __storm_memset_dma_mapping(struct bnx2x *bp,
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u32 addr, dma_addr_t mapping)
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{
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@@ -523,6 +524,7 @@ int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
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* as long as this code is called both from syscall context and
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* from ndo_set_rx_mode() flow that may be called from BH.
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*/
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spin_lock_bh(&bp->dmae_lock);
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/* reset completion */
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@@ -551,7 +553,9 @@ int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
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}
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unlock:
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spin_unlock_bh(&bp->dmae_lock);
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return rc;
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}
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@@ -5452,6 +5456,14 @@ static void bnx2x_eq_int(struct bnx2x *bp)
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break;
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goto next_spqe;
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case EVENT_RING_OPCODE_SET_TIMESYNC:
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DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
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"got set_timesync ramrod completion\n");
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if (f_obj->complete_cmd(bp, f_obj,
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BNX2X_F_CMD_SET_TIMESYNC))
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break;
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goto next_spqe;
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}
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switch (opcode | bp->state) {
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@@ -9033,6 +9045,48 @@ static int bnx2x_func_wait_started(struct bnx2x *bp)
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return 0;
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}
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static void bnx2x_disable_ptp(struct bnx2x *bp)
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{
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int port = BP_PORT(bp);
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/* Disable sending PTP packets to host */
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REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
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NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
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/* Reset PTP event detection rules */
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REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
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NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
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REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
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NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
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REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
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NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
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REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
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NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
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/* Disable the PTP feature */
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REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
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NIG_REG_P0_PTP_EN, 0x0);
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}
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/* Called during unload, to stop PTP-related stuff */
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void bnx2x_stop_ptp(struct bnx2x *bp)
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{
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/* Cancel PTP work queue. Should be done after the Tx queues are
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* drained to prevent additional scheduling.
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*/
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cancel_work_sync(&bp->ptp_task);
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if (bp->ptp_tx_skb) {
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dev_kfree_skb_any(bp->ptp_tx_skb);
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bp->ptp_tx_skb = NULL;
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}
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/* Disable PTP in HW */
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bnx2x_disable_ptp(bp);
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DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
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}
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void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
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{
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int port = BP_PORT(bp);
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@@ -9151,6 +9205,13 @@ unload_error:
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#endif
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}
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/* stop_ptp should be after the Tx queues are drained to prevent
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* scheduling to the cancelled PTP work queue. It should also be after
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* function stop ramrod is sent, since as part of this ramrod FW access
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* PTP registers.
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*/
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bnx2x_stop_ptp(bp);
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/* Disable HW interrupts, NAPI */
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bnx2x_netif_stop(bp, 1);
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/* Delete all NAPI objects */
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@@ -12023,6 +12084,9 @@ static int bnx2x_init_bp(struct bnx2x *bp)
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bp->dump_preset_idx = 1;
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if (CHIP_IS_E3B0(bp))
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bp->flags |= PTP_SUPPORTED;
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return rc;
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}
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@@ -12355,13 +12419,17 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
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struct bnx2x *bp = netdev_priv(dev);
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struct mii_ioctl_data *mdio = if_mii(ifr);
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DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
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mdio->phy_id, mdio->reg_num, mdio->val_in);
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if (!netif_running(dev))
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return -EAGAIN;
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return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
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switch (cmd) {
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case SIOCSHWTSTAMP:
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return bnx2x_hwtstamp_ioctl(bp, ifr);
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default:
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DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
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mdio->phy_id, mdio->reg_num, mdio->val_in);
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return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
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}
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}
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#ifdef CONFIG_NET_POLL_CONTROLLER
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@@ -13005,6 +13073,191 @@ static int set_is_vf(int chip_id)
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}
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}
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/* nig_tsgen registers relative address */
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#define tsgen_ctrl 0x0
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#define tsgen_freecount 0x10
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#define tsgen_synctime_t0 0x20
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#define tsgen_offset_t0 0x28
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#define tsgen_drift_t0 0x30
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#define tsgen_synctime_t1 0x58
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#define tsgen_offset_t1 0x60
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#define tsgen_drift_t1 0x68
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/* FW workaround for setting drift */
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static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
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int best_val, int best_period)
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{
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struct bnx2x_func_state_params func_params = {NULL};
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struct bnx2x_func_set_timesync_params *set_timesync_params =
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&func_params.params.set_timesync;
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/* Prepare parameters for function state transitions */
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__set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
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__set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
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func_params.f_obj = &bp->func_obj;
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func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
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/* Function parameters */
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set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
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set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
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set_timesync_params->add_sub_drift_adjust_value =
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drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
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set_timesync_params->drift_adjust_value = best_val;
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set_timesync_params->drift_adjust_period = best_period;
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return bnx2x_func_state_change(bp, &func_params);
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}
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static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
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{
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struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
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int rc;
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int drift_dir = 1;
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int val, period, period1, period2, dif, dif1, dif2;
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int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
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DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
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if (!netif_running(bp->dev)) {
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DP(BNX2X_MSG_PTP,
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"PTP adjfreq called while the interface is down\n");
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return -EFAULT;
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}
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if (ppb < 0) {
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ppb = -ppb;
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drift_dir = 0;
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}
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if (ppb == 0) {
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best_val = 1;
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best_period = 0x1FFFFFF;
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} else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
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best_val = 31;
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best_period = 1;
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} else {
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/* Changed not to allow val = 8, 16, 24 as these values
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* are not supported in workaround.
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*/
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for (val = 0; val <= 31; val++) {
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if ((val & 0x7) == 0)
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continue;
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period1 = val * 1000000 / ppb;
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period2 = period1 + 1;
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if (period1 != 0)
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dif1 = ppb - (val * 1000000 / period1);
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else
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dif1 = BNX2X_MAX_PHC_DRIFT;
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if (dif1 < 0)
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dif1 = -dif1;
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dif2 = ppb - (val * 1000000 / period2);
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if (dif2 < 0)
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dif2 = -dif2;
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dif = (dif1 < dif2) ? dif1 : dif2;
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period = (dif1 < dif2) ? period1 : period2;
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if (dif < best_dif) {
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best_dif = dif;
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best_val = val;
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best_period = period;
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}
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}
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}
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rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
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best_period);
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if (rc) {
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BNX2X_ERR("Failed to set drift\n");
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return -EFAULT;
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}
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DP(BNX2X_MSG_PTP, "Configrued val = %d, period = %d\n", best_val,
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best_period);
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return 0;
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}
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static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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{
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struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
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u64 now;
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DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
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now = timecounter_read(&bp->timecounter);
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now += delta;
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/* Re-init the timecounter */
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timecounter_init(&bp->timecounter, &bp->cyclecounter, now);
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return 0;
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}
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static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
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{
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struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
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u64 ns;
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u32 remainder;
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ns = timecounter_read(&bp->timecounter);
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DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
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ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
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ts->tv_nsec = remainder;
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return 0;
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}
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static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
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const struct timespec *ts)
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{
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struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
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u64 ns;
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ns = ts->tv_sec * 1000000000ULL;
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ns += ts->tv_nsec;
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DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
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/* Re-init the timecounter */
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timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
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return 0;
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}
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/* Enable (or disable) ancillary features of the phc subsystem */
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static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
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struct ptp_clock_request *rq, int on)
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{
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struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
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BNX2X_ERR("PHC ancillary features are not supported\n");
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return -ENOTSUPP;
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}
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void bnx2x_register_phc(struct bnx2x *bp)
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{
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/* Fill the ptp_clock_info struct and register PTP clock*/
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bp->ptp_clock_info.owner = THIS_MODULE;
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snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
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bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
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bp->ptp_clock_info.n_alarm = 0;
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bp->ptp_clock_info.n_ext_ts = 0;
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bp->ptp_clock_info.n_per_out = 0;
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bp->ptp_clock_info.pps = 0;
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bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
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bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
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bp->ptp_clock_info.gettime = bnx2x_ptp_gettime;
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bp->ptp_clock_info.settime = bnx2x_ptp_settime;
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bp->ptp_clock_info.enable = bnx2x_ptp_enable;
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bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
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if (IS_ERR(bp->ptp_clock)) {
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bp->ptp_clock = NULL;
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BNX2X_ERR("PTP clock registeration failed\n");
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}
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}
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static int bnx2x_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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@@ -13176,6 +13429,8 @@ static int bnx2x_init_one(struct pci_dev *pdev,
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"Unknown",
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dev->base_addr, bp->pdev->irq, dev->dev_addr);
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bnx2x_register_phc(bp);
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return 0;
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init_one_exit:
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@@ -13202,6 +13457,11 @@ static void __bnx2x_remove(struct pci_dev *pdev,
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struct bnx2x *bp,
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bool remove_netdev)
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{
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if (bp->ptp_clock) {
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ptp_clock_unregister(bp->ptp_clock);
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bp->ptp_clock = NULL;
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}
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/* Delete storage MAC address */
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if (!NO_FCOE(bp)) {
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rtnl_lock();
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@@ -14177,3 +14437,332 @@ int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
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REG_RD(bp, pretend_reg);
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return 0;
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}
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static void bnx2x_ptp_task(struct work_struct *work)
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{
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struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
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int port = BP_PORT(bp);
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u32 val_seq;
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u64 timestamp, ns;
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struct skb_shared_hwtstamps shhwtstamps;
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/* Read Tx timestamp registers */
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val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
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NIG_REG_P0_TLLH_PTP_BUF_SEQID);
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if (val_seq & 0x10000) {
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/* There is a valid timestamp value */
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timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
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NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
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timestamp <<= 32;
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timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
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NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
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/* Reset timestamp register to allow new timestamp */
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REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
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NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
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ns = timecounter_cyc2time(&bp->timecounter, timestamp);
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memset(&shhwtstamps, 0, sizeof(shhwtstamps));
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shhwtstamps.hwtstamp = ns_to_ktime(ns);
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skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
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dev_kfree_skb_any(bp->ptp_tx_skb);
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bp->ptp_tx_skb = NULL;
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DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
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timestamp, ns);
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} else {
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DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
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/* Reschedule to keep checking for a valid timestamp value */
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schedule_work(&bp->ptp_task);
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}
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}
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void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
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{
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int port = BP_PORT(bp);
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u64 timestamp, ns;
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timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
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NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
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timestamp <<= 32;
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timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
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NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
|
||||
|
||||
/* Reset timestamp register to allow new timestamp */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
|
||||
NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
|
||||
|
||||
ns = timecounter_cyc2time(&bp->timecounter, timestamp);
|
||||
|
||||
skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
|
||||
|
||||
DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
|
||||
timestamp, ns);
|
||||
}
|
||||
|
||||
/* Read the PHC */
|
||||
static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
|
||||
{
|
||||
struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
|
||||
int port = BP_PORT(bp);
|
||||
u32 wb_data[2];
|
||||
u64 phc_cycles;
|
||||
|
||||
REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
|
||||
NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
|
||||
phc_cycles = wb_data[1];
|
||||
phc_cycles = (phc_cycles << 32) + wb_data[0];
|
||||
|
||||
DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
|
||||
|
||||
return phc_cycles;
|
||||
}
|
||||
|
||||
static void bnx2x_init_cyclecounter(struct bnx2x *bp)
|
||||
{
|
||||
memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
|
||||
bp->cyclecounter.read = bnx2x_cyclecounter_read;
|
||||
bp->cyclecounter.mask = CLOCKSOURCE_MASK(64);
|
||||
bp->cyclecounter.shift = 1;
|
||||
bp->cyclecounter.mult = 1;
|
||||
}
|
||||
|
||||
static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
|
||||
{
|
||||
struct bnx2x_func_state_params func_params = {NULL};
|
||||
struct bnx2x_func_set_timesync_params *set_timesync_params =
|
||||
&func_params.params.set_timesync;
|
||||
|
||||
/* Prepare parameters for function state transitions */
|
||||
__set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
|
||||
__set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
|
||||
|
||||
func_params.f_obj = &bp->func_obj;
|
||||
func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
|
||||
|
||||
/* Function parameters */
|
||||
set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
|
||||
set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
|
||||
|
||||
return bnx2x_func_state_change(bp, &func_params);
|
||||
}
|
||||
|
||||
int bnx2x_enable_ptp_packets(struct bnx2x *bp)
|
||||
{
|
||||
struct bnx2x_queue_state_params q_params;
|
||||
int rc, i;
|
||||
|
||||
/* send queue update ramrod to enable PTP packets */
|
||||
memset(&q_params, 0, sizeof(q_params));
|
||||
__set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
|
||||
q_params.cmd = BNX2X_Q_CMD_UPDATE;
|
||||
__set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
|
||||
&q_params.params.update.update_flags);
|
||||
__set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
|
||||
&q_params.params.update.update_flags);
|
||||
|
||||
/* send the ramrod on all the queues of the PF */
|
||||
for_each_eth_queue(bp, i) {
|
||||
struct bnx2x_fastpath *fp = &bp->fp[i];
|
||||
|
||||
/* Set the appropriate Queue object */
|
||||
q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
|
||||
|
||||
/* Update the Queue state */
|
||||
rc = bnx2x_queue_state_change(bp, &q_params);
|
||||
if (rc) {
|
||||
BNX2X_ERR("Failed to enable PTP packets\n");
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int bnx2x_configure_ptp_filters(struct bnx2x *bp)
|
||||
{
|
||||
int port = BP_PORT(bp);
|
||||
int rc;
|
||||
|
||||
if (!bp->hwtstamp_ioctl_called)
|
||||
return 0;
|
||||
|
||||
switch (bp->tx_type) {
|
||||
case HWTSTAMP_TX_ON:
|
||||
bp->flags |= TX_TIMESTAMPING_EN;
|
||||
REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
|
||||
NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
|
||||
REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
|
||||
NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
|
||||
break;
|
||||
case HWTSTAMP_TX_ONESTEP_SYNC:
|
||||
BNX2X_ERR("One-step timestamping is not supported\n");
|
||||
return -ERANGE;
|
||||
}
|
||||
|
||||
switch (bp->rx_filter) {
|
||||
case HWTSTAMP_FILTER_NONE:
|
||||
break;
|
||||
case HWTSTAMP_FILTER_ALL:
|
||||
case HWTSTAMP_FILTER_SOME:
|
||||
bp->rx_filter = HWTSTAMP_FILTER_NONE;
|
||||
break;
|
||||
case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
|
||||
case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
|
||||
case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
|
||||
bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
|
||||
/* Initialize PTP detection for UDP/IPv4 events */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
|
||||
NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
|
||||
NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
|
||||
break;
|
||||
case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
|
||||
case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
|
||||
case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
|
||||
bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
|
||||
/* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
|
||||
NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
|
||||
NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
|
||||
break;
|
||||
case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
|
||||
case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
|
||||
case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
|
||||
bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
|
||||
/* Initialize PTP detection L2 events */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
|
||||
NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
|
||||
NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
|
||||
|
||||
break;
|
||||
case HWTSTAMP_FILTER_PTP_V2_EVENT:
|
||||
case HWTSTAMP_FILTER_PTP_V2_SYNC:
|
||||
case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
|
||||
bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
|
||||
/* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
|
||||
NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
|
||||
NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Indicate to FW that this PF expects recorded PTP packets */
|
||||
rc = bnx2x_enable_ptp_packets(bp);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* Enable sending PTP packets to host */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
|
||||
NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
|
||||
{
|
||||
struct hwtstamp_config config;
|
||||
int rc;
|
||||
|
||||
DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
|
||||
|
||||
if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
|
||||
return -EFAULT;
|
||||
|
||||
DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
|
||||
config.tx_type, config.rx_filter);
|
||||
|
||||
if (config.flags) {
|
||||
BNX2X_ERR("config.flags is reserved for future use\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
bp->hwtstamp_ioctl_called = 1;
|
||||
bp->tx_type = config.tx_type;
|
||||
bp->rx_filter = config.rx_filter;
|
||||
|
||||
rc = bnx2x_configure_ptp_filters(bp);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
config.rx_filter = bp->rx_filter;
|
||||
|
||||
return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
|
||||
-EFAULT : 0;
|
||||
}
|
||||
|
||||
/* Configrues HW for PTP */
|
||||
static int bnx2x_configure_ptp(struct bnx2x *bp)
|
||||
{
|
||||
int rc, port = BP_PORT(bp);
|
||||
u32 wb_data[2];
|
||||
|
||||
/* Reset PTP event detection rules - will be configured in the IOCTL */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
|
||||
NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
|
||||
NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
|
||||
REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
|
||||
NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
|
||||
REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
|
||||
NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
|
||||
|
||||
/* Disable PTP packets to host - will be configured in the IOCTL*/
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
|
||||
NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
|
||||
|
||||
/* Enable the PTP feature */
|
||||
REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
|
||||
NIG_REG_P0_PTP_EN, 0x3F);
|
||||
|
||||
/* Enable the free-running counter */
|
||||
wb_data[0] = 0;
|
||||
wb_data[1] = 0;
|
||||
REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
|
||||
|
||||
/* Reset drift register (offset register is not reset) */
|
||||
rc = bnx2x_send_reset_timesync_ramrod(bp);
|
||||
if (rc) {
|
||||
BNX2X_ERR("Failed to reset PHC drift register\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
/* Reset possibly old timestamps */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
|
||||
NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
|
||||
REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
|
||||
NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Called during load, to initialize PTP-related stuff */
|
||||
void bnx2x_init_ptp(struct bnx2x *bp)
|
||||
{
|
||||
int rc;
|
||||
|
||||
/* Configure PTP in HW */
|
||||
rc = bnx2x_configure_ptp(bp);
|
||||
if (rc) {
|
||||
BNX2X_ERR("Stopping PTP initialization\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Init work queue for Tx timestamping */
|
||||
INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
|
||||
|
||||
/* Init cyclecounter and timecounter. This is done only in the first
|
||||
* load. If done in every load, PTP application will fail when doing
|
||||
* unload / load (e.g. MTU change) while it is running.
|
||||
*/
|
||||
if (!bp->timecounter_init_done) {
|
||||
bnx2x_init_cyclecounter(bp);
|
||||
timecounter_init(&bp->timecounter, &bp->cyclecounter,
|
||||
ktime_to_ns(ktime_get_real()));
|
||||
bp->timecounter_init_done = 1;
|
||||
}
|
||||
|
||||
DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user