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drm/i915: Rename graphics reset registers.

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The graphics domains are listed as GRDOM in the documentation, and the
GDRST PCI config register (0xc0) is only valid on I965 and GM45.  Newer
chips (like Sandy Bridge) have a different GDRST.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Kenneth Graunke 2010-09-11 01:24:50 -07:00 committed by Chris Wilson
parent f49f058619
commit eeccdcac07
3 changed files with 10 additions and 8 deletions
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6
drivers/gpu/drm/i915/i915_drv.c
View File

@ -330,7 +330,7 @@ int i915_resume(struct drm_device *dev)
static int i965_reset_complete(struct drm_device *dev) static int i965_reset_complete(struct drm_device *dev)
{ {
u8 gdrst; u8 gdrst;
pci_read_config_byte(dev->pdev, GDRST, &gdrst); pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
return gdrst & 0x1; return gdrst & 0x1;
} }
@ -375,8 +375,8 @@ int i965_reset(struct drm_device *dev, u8 flags)
* well as the reset bit (GR/bit 0). Setting the GR bit * well as the reset bit (GR/bit 0). Setting the GR bit
* triggers the reset; when done, the hardware will clear it. * triggers the reset; when done, the hardware will clear it.
*/ */
pci_read_config_byte(dev->pdev, GDRST, &gdrst); pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | 0x1); pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
/* Wait for the hardware to reset (but no more than 500 ms) */ /* Wait for the hardware to reset (but no more than 500 ms) */
if (wait_for(i965_reset_complete(dev), 500)) { if (wait_for(i965_reset_complete(dev), 500)) {

2
drivers/gpu/drm/i915/i915_irq.c
View File

@ -401,7 +401,7 @@ static void i915_error_work_func(struct work_struct *work)
case 4: case 4:
DRM_DEBUG_DRIVER("resetting chip\n"); DRM_DEBUG_DRIVER("resetting chip\n");
kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
if (!i965_reset(dev, GDRST_RENDER)) { if (!i965_reset(dev, GRDOM_RENDER)) {
atomic_set(&dev_priv->mm.wedged, 0); atomic_set(&dev_priv->mm.wedged, 0);
kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
} }

10
drivers/gpu/drm/i915/i915_reg.h
View File

@ -108,10 +108,12 @@
#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
#define LBB 0xf4 #define LBB 0xf4
#define GDRST 0xc0
#define GDRST_FULL (0<<2) /* Graphics reset regs */
#define GDRST_RENDER (1<<2) #define I965_GDRST 0xc0
#define GDRST_MEDIA (3<<2) #define GRDOM_FULL (0<<2)
#define GRDOM_RENDER (1<<2)
#define GRDOM_MEDIA (3<<2)
/* VGA stuff */ /* VGA stuff */