staging: wilc1000: refactor interrupt handling for sdio
Make use of FIELD_PREP/FIELD_GET macro to refactor the interrupt handling for SDIO. Signed-off-by: Ajay Singh <ajay.kathat@microchip.com> Link: https://lore.kernel.org/r/20200214172250.13026-4-ajay.kathat@microchip.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -26,7 +26,6 @@ static const struct sdio_device_id wilc_sdio_ids[] = {
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struct wilc_sdio {
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struct wilc_sdio {
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bool irq_gpio;
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bool irq_gpio;
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u32 block_size;
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u32 block_size;
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int nint;
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int has_thrpt_enh3;
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int has_thrpt_enh3;
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};
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};
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@ -790,6 +789,7 @@ static int wilc_sdio_read_int(struct wilc *wilc, u32 *int_status)
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struct sdio_func *func = dev_to_sdio_func(wilc->dev);
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struct sdio_func *func = dev_to_sdio_func(wilc->dev);
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struct wilc_sdio *sdio_priv = wilc->bus_data;
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struct wilc_sdio *sdio_priv = wilc->bus_data;
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u32 tmp;
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u32 tmp;
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u8 irq_flags;
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struct sdio_cmd52 cmd;
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struct sdio_cmd52 cmd;
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wilc_sdio_read_size(wilc, &tmp);
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wilc_sdio_read_size(wilc, &tmp);
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@ -798,44 +798,22 @@ static int wilc_sdio_read_int(struct wilc *wilc, u32 *int_status)
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* Read IRQ flags
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* Read IRQ flags
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**/
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**/
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if (!sdio_priv->irq_gpio) {
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if (!sdio_priv->irq_gpio) {
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int i;
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cmd.read_write = 0;
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cmd.function = 1;
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cmd.function = 1;
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cmd.address = 0x04;
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cmd.address = 0x04;
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cmd.data = 0;
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wilc_sdio_cmd52(wilc, &cmd);
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if (cmd.data & BIT(0))
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tmp |= INT_0;
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if (cmd.data & BIT(2))
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tmp |= INT_1;
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if (cmd.data & BIT(3))
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tmp |= INT_2;
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if (cmd.data & BIT(4))
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tmp |= INT_3;
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if (cmd.data & BIT(5))
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tmp |= INT_4;
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for (i = sdio_priv->nint; i < MAX_NUM_INT; i++) {
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if ((tmp >> (IRG_FLAGS_OFFSET + i)) & 0x1) {
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dev_err(&func->dev,
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"Unexpected interrupt (1) : tmp=%x, data=%x\n",
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tmp, cmd.data);
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break;
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}
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}
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} else {
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} else {
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u32 irq_flags;
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cmd.read_write = 0;
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cmd.function = 0;
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cmd.function = 0;
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cmd.raw = 0;
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cmd.address = 0xf7;
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cmd.address = 0xf7;
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cmd.data = 0;
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wilc_sdio_cmd52(wilc, &cmd);
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irq_flags = cmd.data & 0x1f;
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tmp |= ((irq_flags >> 0) << IRG_FLAGS_OFFSET);
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}
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}
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cmd.raw = 0;
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cmd.read_write = 0;
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cmd.data = 0;
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wilc_sdio_cmd52(wilc, &cmd);
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irq_flags = cmd.data;
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tmp |= FIELD_PREP(IRG_FLAGS_MASK, cmd.data);
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if (FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags))
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dev_err(&func->dev, "Unexpected interrupt (1) int=%lx\n",
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FIELD_GET(UNHANDLED_IRQ_MASK, irq_flags));
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*int_status = tmp;
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*int_status = tmp;
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@ -890,38 +868,36 @@ static int wilc_sdio_clear_int_ext(struct wilc *wilc, u32 val)
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* Must clear each interrupt individually.
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* Must clear each interrupt individually.
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*/
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*/
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u32 flags;
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u32 flags;
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int i;
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flags = val & (BIT(MAX_NUM_INT) - 1);
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flags = val & (BIT(MAX_NUM_INT) - 1);
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if (flags) {
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for (i = 0; i < NUM_INT_EXT && flags; i++) {
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int i;
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if (flags & BIT(i)) {
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struct sdio_cmd52 cmd;
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for (i = 0; i < sdio_priv->nint; i++) {
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cmd.read_write = 1;
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if (flags & 1) {
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cmd.function = 0;
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struct sdio_cmd52 cmd;
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cmd.raw = 0;
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cmd.address = 0xf8;
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cmd.data = BIT(i);
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cmd.read_write = 1;
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ret = wilc_sdio_cmd52(wilc, &cmd);
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cmd.function = 0;
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if (ret) {
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cmd.raw = 0;
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cmd.address = 0xf8;
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cmd.data = BIT(i);
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ret = wilc_sdio_cmd52(wilc, &cmd);
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if (ret) {
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dev_err(&func->dev,
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"Failed cmd52, set 0xf8 data (%d) ...\n",
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__LINE__);
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return ret;
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}
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}
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flags >>= 1;
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}
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for (i = sdio_priv->nint; i < MAX_NUM_INT; i++) {
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if (flags & 1)
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dev_err(&func->dev,
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dev_err(&func->dev,
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"Unexpected interrupt cleared %d...\n",
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"Failed cmd52, set 0xf8 data (%d) ...\n",
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i);
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__LINE__);
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flags >>= 1;
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return ret;
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}
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flags &= ~BIT(i);
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}
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}
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for (i = NUM_INT_EXT; i < MAX_NUM_INT && flags; i++) {
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if (flags & BIT(i)) {
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dev_err(&func->dev,
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"Unexpected interrupt cleared %d...\n",
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i);
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flags &= ~BIT(i);
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}
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}
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}
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}
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}
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}
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@ -967,8 +943,6 @@ static int wilc_sdio_sync_ext(struct wilc *wilc, int nint)
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return -EINVAL;
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return -EINVAL;
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}
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}
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sdio_priv->nint = nint;
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/**
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/**
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* Disable power sequencer
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* Disable power sequencer
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**/
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**/
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@ -12,7 +12,6 @@
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struct wilc_spi {
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struct wilc_spi {
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int crc_off;
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int crc_off;
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int nint;
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};
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};
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static const struct wilc_hif_func wilc_hif_spi;
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static const struct wilc_hif_func wilc_hif_spi;
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@ -916,7 +915,6 @@ static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
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static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
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static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
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{
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{
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struct spi_device *spi = to_spi_device(wilc->dev);
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struct spi_device *spi = to_spi_device(wilc->dev);
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struct wilc_spi *spi_priv = wilc->bus_data;
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u32 reg;
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u32 reg;
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int ret, i;
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int ret, i;
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@ -925,8 +923,6 @@ static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
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return -EINVAL;
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return -EINVAL;
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}
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}
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spi_priv->nint = nint;
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/*
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/*
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* interrupt pin mux select
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* interrupt pin mux select
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*/
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*/
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@ -176,6 +176,8 @@
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#define INT_4 BIT(IRG_FLAGS_OFFSET + 4)
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#define INT_4 BIT(IRG_FLAGS_OFFSET + 4)
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#define INT_5 BIT(IRG_FLAGS_OFFSET + 5)
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#define INT_5 BIT(IRG_FLAGS_OFFSET + 5)
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#define MAX_NUM_INT 5
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#define MAX_NUM_INT 5
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#define IRG_FLAGS_MASK GENMASK(IRG_FLAGS_OFFSET + MAX_NUM_INT, \
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IRG_FLAGS_OFFSET)
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/*******************************************/
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/*******************************************/
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/* E0 and later Interrupt flags. */
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/* E0 and later Interrupt flags. */
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@ -203,6 +205,7 @@
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#define DATA_INT_EXT INT_0
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#define DATA_INT_EXT INT_0
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#define ALL_INT_EXT DATA_INT_EXT
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#define ALL_INT_EXT DATA_INT_EXT
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#define NUM_INT_EXT 1
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#define NUM_INT_EXT 1
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#define UNHANDLED_IRQ_MASK GENMASK(MAX_NUM_INT - 1, NUM_INT_EXT)
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#define DATA_INT_CLR CLR_INT0
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#define DATA_INT_CLR CLR_INT0
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