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MIPS: Netlogic: L1D cacheflush before thread enable on XLPII

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On XLPII CPUs, the L1D cache has to be flushed with regular cache
operations before enabling threads in a core.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6276/
This commit is contained in:
Yonghong Song 2013-12-21 16:52:16 +05:30 committed by Ralf Baechle
parent d3b9428502
commit ed8dfc46e0
1 changed files with 23 additions and 2 deletions
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25
arch/mips/netlogic/common/reset.S
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@ -36,6 +36,7 @@
#include <asm/asm.h> #include <asm/asm.h>
#include <asm/asm-offsets.h> #include <asm/asm-offsets.h>
#include <asm/cacheops.h>
#include <asm/regdef.h> #include <asm/regdef.h>
#include <asm/mipsregs.h> #include <asm/mipsregs.h>
#include <asm/stackframe.h> #include <asm/stackframe.h>
@ -74,10 +75,18 @@
.endm .endm
/* /*
* Low level flush for L1D cache on XLP, the normal cache ops does * L1D cache has to be flushed before enabling threads in XLP.
* not do the complete and correct cache flush. * On XLP8xx/XLP3xx, we do a low level flush using processor control
* registers. On XLPII CPUs, usual cache instructions work.
*/ */
.macro xlp_flush_l1_dcache .macro xlp_flush_l1_dcache
mfc0 t0, CP0_EBASE, 0
andi t0, t0, 0xff00
slt t1, t0, 0x1200
beqz t1, 15f
nop
/* XLP8xx low level cache flush */
li t0, LSU_DEBUG_DATA0 li t0, LSU_DEBUG_DATA0
li t1, LSU_DEBUG_ADDR li t1, LSU_DEBUG_ADDR
li t2, 0 /* index */ li t2, 0 /* index */
@ -103,6 +112,18 @@
addi t2, 1 addi t2, 1
bne t3, t2, 11b bne t3, t2, 11b
nop nop
b 17f
nop
/* XLPII CPUs, Invalidate all 64k of L1 D-cache */
15:
li t0, 0x80000000
li t1, 0x80010000
16: cache Index_Writeback_Inv_D, 0(t0)
addiu t0, t0, 32
bne t0, t1, 16b
nop
17:
.endm .endm
/* /*