drm/amd/display: Fixed 4K black issue by refactor update surface.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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committed by
Alex Deucher
parent
86e2e1bee0
commit
ed15194032
@@ -1482,17 +1482,19 @@ void dc_update_surfaces_for_stream(struct dc *dc,
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}
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/* not sure if we still need this */
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for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
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struct core_stream *stream = pipe_ctx->stream;
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if (update_type == UPDATE_TYPE_FULL) {
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for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
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struct core_stream *stream = pipe_ctx->stream;
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if (pipe_ctx->surface != surface)
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continue;
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if (pipe_ctx->surface != surface)
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continue;
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resource_build_scaling_params(updates[i].surface, pipe_ctx);
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if (dc->debug.surface_visual_confirm) {
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pipe_ctx->scl_data.recout.height -= 2;
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pipe_ctx->scl_data.recout.width -= 2;
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resource_build_scaling_params(updates[i].surface, pipe_ctx);
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if (dc->debug.surface_visual_confirm) {
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pipe_ctx->scl_data.recout.height -= 2;
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pipe_ctx->scl_data.recout.width -= 2;
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}
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}
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}
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@@ -1563,10 +1565,12 @@ void dc_update_surfaces_for_stream(struct dc *dc,
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}
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if (update_type == UPDATE_TYPE_FULL) {
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core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
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} else if (updates[i].flip_addr) {
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/* only apply for top pipe */
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if (!pipe_ctx->top_pipe)
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core_dc->hwss.apply_ctx_for_surface(core_dc,
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surface, context);
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} else if (updates[i].flip_addr)
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core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
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}
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if (update_type == UPDATE_TYPE_FAST)
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continue;
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