forked from Minki/linux
[NET] sunqe: Convert to new SBUS driver layer.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
parent
52a34c7fe4
commit
ecba38abfd
@ -1,10 +1,9 @@
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/* $Id: sunqe.c,v 1.55 2002/01/15 06:48:55 davem Exp $
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* sunqe.c: Sparc QuadEthernet 10baseT SBUS card driver.
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/* sunqe.c: Sparc QuadEthernet 10baseT SBUS card driver.
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* Once again I am out to prove that every ethernet
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* controller out there can be most efficiently programmed
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* if you make it look like a LANCE.
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*
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* Copyright (C) 1996, 1999, 2003 David S. Miller (davem@redhat.com)
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* Copyright (C) 1996, 1999, 2003, 2006 David S. Miller (davem@davemloft.net)
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*/
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#include <linux/module.h>
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@ -41,9 +40,9 @@
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#include "sunqe.h"
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#define DRV_NAME "sunqe"
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#define DRV_VERSION "3.0"
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#define DRV_RELDATE "8/24/03"
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#define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
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#define DRV_VERSION "4.0"
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#define DRV_RELDATE "June 23, 2006"
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#define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
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static char version[] =
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DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
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@ -755,298 +754,269 @@ static inline void qec_init_once(struct sunqec *qecp, struct sbus_dev *qsdev)
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qecp->gregs + GLOB_RSIZE);
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}
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/* Four QE's per QEC card. */
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static int __init qec_ether_init(struct net_device *dev, struct sbus_dev *sdev)
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static u8 __init qec_get_burst(struct device_node *dp)
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{
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static unsigned version_printed;
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struct net_device *qe_devs[4];
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struct sunqe *qeps[4];
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struct sbus_dev *qesdevs[4];
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struct sbus_dev *child;
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struct sunqec *qecp = NULL;
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u8 bsizes, bsizes_more;
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int i, j, res = -ENOMEM;
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for (i = 0; i < 4; i++) {
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qe_devs[i] = alloc_etherdev(sizeof(struct sunqe));
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if (!qe_devs[i])
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goto out;
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}
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if (version_printed++ == 0)
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printk(KERN_INFO "%s", version);
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for (i = 0; i < 4; i++) {
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qeps[i] = (struct sunqe *) qe_devs[i]->priv;
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for (j = 0; j < 6; j++)
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qe_devs[i]->dev_addr[j] = idprom->id_ethaddr[j];
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qeps[i]->channel = i;
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spin_lock_init(&qeps[i]->lock);
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}
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qecp = kmalloc(sizeof(struct sunqec), GFP_KERNEL);
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if (qecp == NULL)
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goto out1;
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qecp->qec_sdev = sdev;
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for (i = 0; i < 4; i++) {
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qecp->qes[i] = qeps[i];
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qeps[i]->dev = qe_devs[i];
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qeps[i]->parent = qecp;
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}
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res = -ENODEV;
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for (i = 0, child = sdev->child; i < 4; i++, child = child->next) {
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/* Link in channel */
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j = prom_getintdefault(child->prom_node, "channel#", -1);
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if (j == -1)
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goto out2;
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qesdevs[j] = child;
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}
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for (i = 0; i < 4; i++)
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qeps[i]->qe_sdev = qesdevs[i];
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/* Now map in the registers, QEC globals first. */
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qecp->gregs = sbus_ioremap(&sdev->resource[0], 0,
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GLOB_REG_SIZE, "QEC Global Registers");
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if (!qecp->gregs) {
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printk(KERN_ERR "QuadEther: Cannot map QEC global registers.\n");
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goto out2;
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}
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/* Make sure the QEC is in MACE mode. */
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if ((sbus_readl(qecp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_MMODE) {
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printk(KERN_ERR "QuadEther: AIEEE, QEC is not in MACE mode!\n");
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goto out3;
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}
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/* Reset the QEC. */
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if (qec_global_reset(qecp->gregs))
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goto out3;
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/* Find and set the burst sizes for the QEC, since it does
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* the actual dma for all 4 channels.
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/* Find and set the burst sizes for the QEC, since it
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* does the actual dma for all 4 channels.
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*/
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bsizes = prom_getintdefault(sdev->prom_node, "burst-sizes", 0xff);
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bsizes = of_getintprop_default(dp, "burst-sizes", 0xff);
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bsizes &= 0xff;
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bsizes_more = prom_getintdefault(sdev->bus->prom_node, "burst-sizes", 0xff);
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bsizes_more = of_getintprop_default(dp->parent, "burst-sizes", 0xff);
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if (bsizes_more != 0xff)
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bsizes &= bsizes_more;
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if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
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(bsizes & DMA_BURST32)==0)
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(bsizes & DMA_BURST32)==0)
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bsizes = (DMA_BURST32 - 1);
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qecp->qec_bursts = bsizes;
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return bsizes;
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}
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/* Perform one time QEC initialization, we never touch the QEC
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* globals again after this.
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*/
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qec_init_once(qecp, sdev);
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static struct sunqec * __init get_qec(struct sbus_dev *child_sdev)
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{
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struct sbus_dev *qec_sdev = child_sdev->parent;
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struct sunqec *qecp;
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for (i = 0; i < 4; i++) {
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struct sunqe *qe = qeps[i];
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/* Map in QEC per-channel control registers. */
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qe->qcregs = sbus_ioremap(&qe->qe_sdev->resource[0], 0,
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CREG_REG_SIZE, "QEC Channel Registers");
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if (!qe->qcregs) {
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printk(KERN_ERR "QuadEther: Cannot map QE %d's channel registers.\n", i);
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goto out4;
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for (qecp = root_qec_dev; qecp; qecp = qecp->next_module) {
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if (qecp->qec_sdev == qec_sdev)
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break;
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}
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if (!qecp) {
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qecp = kzalloc(sizeof(struct sunqec), GFP_KERNEL);
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if (qecp) {
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u32 ctrl;
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qecp->qec_sdev = qec_sdev;
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qecp->gregs = sbus_ioremap(&qec_sdev->resource[0], 0,
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GLOB_REG_SIZE,
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"QEC Global Registers");
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if (!qecp->gregs)
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goto fail;
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/* Make sure the QEC is in MACE mode. */
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ctrl = sbus_readl(qecp->gregs + GLOB_CTRL);
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ctrl &= 0xf0000000;
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if (ctrl != GLOB_CTRL_MMODE) {
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printk(KERN_ERR "qec: Not in MACE mode!\n");
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goto fail;
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}
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if (qec_global_reset(qecp->gregs))
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goto fail;
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qecp->qec_bursts = qec_get_burst(qec_sdev->ofdev.node);
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qec_init_once(qecp, qec_sdev);
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if (request_irq(qec_sdev->irqs[0], &qec_interrupt,
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SA_SHIRQ, "qec", (void *) qecp)) {
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printk(KERN_ERR "qec: Can't register irq.\n");
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goto fail;
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}
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qecp->next_module = root_qec_dev;
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root_qec_dev = qecp;
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}
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}
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/* Map in per-channel AMD MACE registers. */
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qe->mregs = sbus_ioremap(&qe->qe_sdev->resource[1], 0,
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MREGS_REG_SIZE, "QE MACE Registers");
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if (!qe->mregs) {
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printk(KERN_ERR "QuadEther: Cannot map QE %d's MACE registers.\n", i);
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goto out4;
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return qecp;
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fail:
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if (qecp->gregs)
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sbus_iounmap(qecp->gregs, GLOB_REG_SIZE);
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kfree(qecp);
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return NULL;
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}
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static int __init qec_ether_init(struct sbus_dev *sdev)
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{
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static unsigned version_printed;
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struct net_device *dev;
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struct sunqe *qe;
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struct sunqec *qecp;
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int i, res;
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if (version_printed++ == 0)
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printk(KERN_INFO "%s", version);
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dev = alloc_etherdev(sizeof(struct sunqe));
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if (!dev)
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return -ENOMEM;
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qe = netdev_priv(dev);
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i = of_getintprop_default(sdev->ofdev.node, "channel#", -1);
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if (i == -1) {
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struct sbus_dev *td = sdev->parent->child;
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i = 0;
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while (td != sdev) {
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td = td->next;
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i++;
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}
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}
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qe->channel = i;
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spin_lock_init(&qe->lock);
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res = -ENODEV;
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qecp = get_qec(sdev);
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if (!qecp)
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goto fail;
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qe->qe_block = sbus_alloc_consistent(qe->qe_sdev,
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PAGE_SIZE,
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&qe->qblock_dvma);
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qe->buffers = sbus_alloc_consistent(qe->qe_sdev,
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sizeof(struct sunqe_buffers),
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&qe->buffers_dvma);
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if (qe->qe_block == NULL || qe->qblock_dvma == 0 ||
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qe->buffers == NULL || qe->buffers_dvma == 0) {
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goto out4;
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}
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qecp->qes[qe->channel] = qe;
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qe->dev = dev;
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qe->parent = qecp;
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qe->qe_sdev = sdev;
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/* Stop this QE. */
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qe_stop(qe);
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res = -ENOMEM;
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qe->qcregs = sbus_ioremap(&qe->qe_sdev->resource[0], 0,
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CREG_REG_SIZE, "QEC Channel Registers");
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if (!qe->qcregs) {
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printk(KERN_ERR "qe: Cannot map channel registers.\n");
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goto fail;
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}
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for (i = 0; i < 4; i++) {
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SET_MODULE_OWNER(qe_devs[i]);
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qe_devs[i]->open = qe_open;
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qe_devs[i]->stop = qe_close;
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qe_devs[i]->hard_start_xmit = qe_start_xmit;
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qe_devs[i]->get_stats = qe_get_stats;
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qe_devs[i]->set_multicast_list = qe_set_multicast;
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qe_devs[i]->tx_timeout = qe_tx_timeout;
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qe_devs[i]->watchdog_timeo = 5*HZ;
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qe_devs[i]->irq = sdev->irqs[0];
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qe_devs[i]->dma = 0;
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qe_devs[i]->ethtool_ops = &qe_ethtool_ops;
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qe->mregs = sbus_ioremap(&qe->qe_sdev->resource[1], 0,
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MREGS_REG_SIZE, "QE MACE Registers");
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if (!qe->mregs) {
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printk(KERN_ERR "qe: Cannot map MACE registers.\n");
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goto fail;
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}
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/* QEC receives interrupts from each QE, then it sends the actual
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* IRQ to the cpu itself. Since QEC is the single point of
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* interrupt for all QE channels we register the IRQ handler
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* for it now.
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*/
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if (request_irq(sdev->irqs[0], &qec_interrupt,
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SA_SHIRQ, "QuadEther", (void *) qecp)) {
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printk(KERN_ERR "QuadEther: Can't register QEC master irq handler.\n");
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res = -EAGAIN;
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goto out4;
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}
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qe->qe_block = sbus_alloc_consistent(qe->qe_sdev,
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PAGE_SIZE,
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&qe->qblock_dvma);
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qe->buffers = sbus_alloc_consistent(qe->qe_sdev,
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sizeof(struct sunqe_buffers),
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&qe->buffers_dvma);
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if (qe->qe_block == NULL || qe->qblock_dvma == 0 ||
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qe->buffers == NULL || qe->buffers_dvma == 0)
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goto fail;
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for (i = 0; i < 4; i++) {
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if (register_netdev(qe_devs[i]) != 0)
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goto out5;
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}
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/* Stop this QE. */
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qe_stop(qe);
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/* Report the QE channels. */
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for (i = 0; i < 4; i++) {
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printk(KERN_INFO "%s: QuadEthernet channel[%d] ", qe_devs[i]->name, i);
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for (j = 0; j < 6; j++)
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printk ("%2.2x%c",
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qe_devs[i]->dev_addr[j],
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j == 5 ? ' ': ':');
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printk("\n");
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}
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SET_MODULE_OWNER(dev);
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SET_NETDEV_DEV(dev, &sdev->ofdev.dev);
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dev->open = qe_open;
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dev->stop = qe_close;
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dev->hard_start_xmit = qe_start_xmit;
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dev->get_stats = qe_get_stats;
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dev->set_multicast_list = qe_set_multicast;
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dev->tx_timeout = qe_tx_timeout;
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dev->watchdog_timeo = 5*HZ;
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dev->irq = sdev->irqs[0];
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dev->dma = 0;
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dev->ethtool_ops = &qe_ethtool_ops;
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res = register_netdev(dev);
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if (res)
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goto fail;
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dev_set_drvdata(&sdev->ofdev.dev, qe);
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printk(KERN_INFO "%s: qe channel[%d] ", dev->name, qe->channel);
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for (i = 0; i < 6; i++)
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printk ("%2.2x%c",
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dev->dev_addr[i],
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i == 5 ? ' ': ':');
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printk("\n");
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/* We are home free at this point, link the qe's into
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* the master list for later driver exit.
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*/
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qecp->next_module = root_qec_dev;
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root_qec_dev = qecp;
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return 0;
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out5:
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while (i--)
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unregister_netdev(qe_devs[i]);
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free_irq(sdev->irqs[0], (void *)qecp);
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out4:
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for (i = 0; i < 4; i++) {
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struct sunqe *qe = (struct sunqe *)qe_devs[i]->priv;
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fail:
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if (qe->qcregs)
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sbus_iounmap(qe->qcregs, CREG_REG_SIZE);
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if (qe->mregs)
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sbus_iounmap(qe->mregs, MREGS_REG_SIZE);
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if (qe->qe_block)
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sbus_free_consistent(qe->qe_sdev,
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PAGE_SIZE,
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qe->qe_block,
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qe->qblock_dvma);
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if (qe->buffers)
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sbus_free_consistent(qe->qe_sdev,
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sizeof(struct sunqe_buffers),
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qe->buffers,
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qe->buffers_dvma);
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free_netdev(dev);
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if (qe->qcregs)
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sbus_iounmap(qe->qcregs, CREG_REG_SIZE);
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if (qe->mregs)
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sbus_iounmap(qe->mregs, MREGS_REG_SIZE);
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if (qe->qe_block)
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sbus_free_consistent(qe->qe_sdev,
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PAGE_SIZE,
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qe->qe_block,
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qe->qblock_dvma);
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if (qe->buffers)
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sbus_free_consistent(qe->qe_sdev,
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sizeof(struct sunqe_buffers),
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qe->buffers,
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qe->buffers_dvma);
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}
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out3:
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sbus_iounmap(qecp->gregs, GLOB_REG_SIZE);
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out2:
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kfree(qecp);
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out1:
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i = 4;
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out:
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while (i--)
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free_netdev(qe_devs[i]);
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return res;
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}
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static int __init qec_match(struct sbus_dev *sdev)
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static int __devinit qec_sbus_probe(struct of_device *dev, const struct of_device_id *match)
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{
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struct sbus_dev *sibling;
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int i;
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struct sbus_dev *sdev = to_sbus_device(&dev->dev);
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|
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if (strcmp(sdev->prom_name, "qec") != 0)
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return 0;
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|
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/* QEC can be parent of either QuadEthernet or BigMAC
|
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* children. Do not confuse this with qfe/SUNW,qfe
|
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* which is a quad-happymeal card and handled by
|
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* a different driver.
|
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*/
|
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sibling = sdev->child;
|
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for (i = 0; i < 4; i++) {
|
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if (sibling == NULL)
|
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return 0;
|
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if (strcmp(sibling->prom_name, "qe") != 0)
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return 0;
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sibling = sibling->next;
|
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}
|
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return 1;
|
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return qec_ether_init(sdev);
|
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}
|
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|
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static int __init qec_probe(void)
|
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static int __devexit qec_sbus_remove(struct of_device *dev)
|
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{
|
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struct net_device *dev = NULL;
|
||||
struct sbus_bus *bus;
|
||||
struct sbus_dev *sdev = NULL;
|
||||
static int called;
|
||||
int cards = 0, v;
|
||||
struct sunqe *qp = dev_get_drvdata(&dev->dev);
|
||||
struct net_device *net_dev = qp->dev;
|
||||
|
||||
root_qec_dev = NULL;
|
||||
unregister_netdevice(net_dev);
|
||||
|
||||
if (called)
|
||||
return -ENODEV;
|
||||
called++;
|
||||
sbus_iounmap(qp->qcregs, CREG_REG_SIZE);
|
||||
sbus_iounmap(qp->mregs, MREGS_REG_SIZE);
|
||||
sbus_free_consistent(qp->qe_sdev,
|
||||
PAGE_SIZE,
|
||||
qp->qe_block,
|
||||
qp->qblock_dvma);
|
||||
sbus_free_consistent(qp->qe_sdev,
|
||||
sizeof(struct sunqe_buffers),
|
||||
qp->buffers,
|
||||
qp->buffers_dvma);
|
||||
|
||||
for_each_sbus(bus) {
|
||||
for_each_sbusdev(sdev, bus) {
|
||||
if (cards)
|
||||
dev = NULL;
|
||||
free_netdev(net_dev);
|
||||
|
||||
dev_set_drvdata(&dev->dev, NULL);
|
||||
|
||||
if (qec_match(sdev)) {
|
||||
cards++;
|
||||
if ((v = qec_ether_init(dev, sdev)))
|
||||
return v;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (!cards)
|
||||
return -ENODEV;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit qec_cleanup(void)
|
||||
static struct of_device_id qec_sbus_match[] = {
|
||||
{
|
||||
.name = "qe",
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, qec_sbus_match);
|
||||
|
||||
static struct of_platform_driver qec_sbus_driver = {
|
||||
.name = "qec",
|
||||
.match_table = qec_sbus_match,
|
||||
.probe = qec_sbus_probe,
|
||||
.remove = __devexit_p(qec_sbus_remove),
|
||||
};
|
||||
|
||||
static int __init qec_init(void)
|
||||
{
|
||||
struct sunqec *next_qec;
|
||||
int i;
|
||||
return of_register_driver(&qec_sbus_driver, &sbus_bus_type);
|
||||
}
|
||||
|
||||
static void __exit qec_exit(void)
|
||||
{
|
||||
of_unregister_driver(&qec_sbus_driver);
|
||||
|
||||
while (root_qec_dev) {
|
||||
next_qec = root_qec_dev->next_module;
|
||||
struct sunqec *next = root_qec_dev->next_module;
|
||||
|
||||
/* Release all four QE channels, then the QEC itself. */
|
||||
for (i = 0; i < 4; i++) {
|
||||
unregister_netdev(root_qec_dev->qes[i]->dev);
|
||||
sbus_iounmap(root_qec_dev->qes[i]->qcregs, CREG_REG_SIZE);
|
||||
sbus_iounmap(root_qec_dev->qes[i]->mregs, MREGS_REG_SIZE);
|
||||
sbus_free_consistent(root_qec_dev->qes[i]->qe_sdev,
|
||||
PAGE_SIZE,
|
||||
root_qec_dev->qes[i]->qe_block,
|
||||
root_qec_dev->qes[i]->qblock_dvma);
|
||||
sbus_free_consistent(root_qec_dev->qes[i]->qe_sdev,
|
||||
sizeof(struct sunqe_buffers),
|
||||
root_qec_dev->qes[i]->buffers,
|
||||
root_qec_dev->qes[i]->buffers_dvma);
|
||||
free_netdev(root_qec_dev->qes[i]->dev);
|
||||
}
|
||||
free_irq(root_qec_dev->qec_sdev->irqs[0], (void *)root_qec_dev);
|
||||
free_irq(root_qec_dev->qec_sdev->irqs[0],
|
||||
(void *) root_qec_dev);
|
||||
sbus_iounmap(root_qec_dev->gregs, GLOB_REG_SIZE);
|
||||
|
||||
kfree(root_qec_dev);
|
||||
root_qec_dev = next_qec;
|
||||
|
||||
root_qec_dev = next;
|
||||
}
|
||||
}
|
||||
|
||||
module_init(qec_probe);
|
||||
module_exit(qec_cleanup);
|
||||
module_init(qec_init);
|
||||
module_exit(qec_exit);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user