forked from Minki/linux
mach-u300: config U300 PL180 PL011 PL022 for DMA
This will configure the platform data for the PL180, PL011 and PL022 PrimeCells found in the U300 to use DMA with the generic PrimeCell DMA engine for COH 901 318. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
1a721859f8
commit
ec8f12533b
@ -3,7 +3,7 @@
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* arch/arm/mach-u300/core.c
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*
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*
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* Copyright (C) 2007-2010 ST-Ericsson AB
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* Copyright (C) 2007-2010 ST-Ericsson SA
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* License terms: GNU General Public License (GPL) version 2
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* Core platform support, IRQ handling and device definitions.
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* Author: Linus Walleij <linus.walleij@stericsson.com>
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@ -16,7 +16,9 @@
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#include <linux/device.h>
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#include <linux/mm.h>
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#include <linux/termios.h>
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#include <linux/dmaengine.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/serial.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/clk.h>
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@ -96,10 +98,20 @@ void __init u300_map_io(void)
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* Declaration of devices found on the U300 board and
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* their respective memory locations.
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*/
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static struct amba_pl011_data uart0_plat_data = {
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#ifdef CONFIG_COH901318
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.dma_filter = coh901318_filter_id,
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.dma_rx_param = (void *) U300_DMA_UART0_RX,
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.dma_tx_param = (void *) U300_DMA_UART0_TX,
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#endif
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};
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static struct amba_device uart0_device = {
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.dev = {
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.coherent_dma_mask = ~0,
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.init_name = "uart0", /* Slow device at 0x3000 offset */
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.platform_data = NULL,
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.platform_data = &uart0_plat_data,
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},
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.res = {
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.start = U300_UART0_BASE,
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@ -111,10 +123,19 @@ static struct amba_device uart0_device = {
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/* The U335 have an additional UART1 on the APP CPU */
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#ifdef CONFIG_MACH_U300_BS335
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static struct amba_pl011_data uart1_plat_data = {
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#ifdef CONFIG_COH901318
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.dma_filter = coh901318_filter_id,
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.dma_rx_param = (void *) U300_DMA_UART1_RX,
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.dma_tx_param = (void *) U300_DMA_UART1_TX,
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#endif
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};
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static struct amba_device uart1_device = {
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.dev = {
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.coherent_dma_mask = ~0,
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.init_name = "uart1", /* Fast device at 0x7000 offset */
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.platform_data = NULL,
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.platform_data = &uart1_plat_data,
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},
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.res = {
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.start = U300_UART1_BASE,
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@ -960,42 +981,37 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.priority_high = 0,
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.dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
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},
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/*
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* Don't set up device address, burst count or size of src
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* or dst bus for this peripheral - handled by PrimeCell
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* DMA extension.
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*/
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{
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.number = U300_DMA_MMCSD_RX_TX,
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.name = "MMCSD RX TX",
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.priority_high = 0,
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.dev_addr = U300_MMCSD_BASE + 0x080,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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.param.ctrl_lli_chained = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_DISABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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.param.ctrl_lli = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_DISABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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.param.ctrl_lli_last = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
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COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_DISABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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@ -1014,15 +1030,76 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.name = "MSPRO RX",
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.priority_high = 0,
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},
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/*
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* Don't set up device address, burst count or size of src
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* or dst bus for this peripheral - handled by PrimeCell
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* DMA extension.
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*/
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{
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.number = U300_DMA_UART0_TX,
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.name = "UART0 TX",
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.priority_high = 0,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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.param.ctrl_lli_chained = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_DISABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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.param.ctrl_lli = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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.param.ctrl_lli_last = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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},
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{
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.number = U300_DMA_UART0_RX,
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.name = "UART0 RX",
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.priority_high = 0,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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.param.ctrl_lli_chained = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_DISABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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.param.ctrl_lli = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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.param.ctrl_lli_last = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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},
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{
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.number = U300_DMA_APEX_TX,
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@ -1080,7 +1157,7 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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COH901318_CX_CTRL_TC_IRQ_DISABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY |
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@ -1252,15 +1329,77 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
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.name = "XGAM PDI",
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.priority_high = 0,
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},
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/*
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* Don't set up device address, burst count or size of src
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* or dst bus for this peripheral - handled by PrimeCell
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* DMA extension.
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*/
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{
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.number = U300_DMA_SPI_TX,
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.name = "SPI TX",
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.priority_high = 0,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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.param.ctrl_lli_chained = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_DISABLE |
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COH901318_CX_CTRL_TC_IRQ_DISABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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.param.ctrl_lli = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_DISABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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.param.ctrl_lli_last = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_DISABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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},
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{
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.number = U300_DMA_SPI_RX,
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.name = "SPI RX",
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.priority_high = 0,
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.param.config = COH901318_CX_CFG_CH_DISABLE |
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COH901318_CX_CFG_LCR_DISABLE |
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COH901318_CX_CFG_TC_IRQ_ENABLE |
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COH901318_CX_CFG_BE_IRQ_ENABLE,
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.param.ctrl_lli_chained = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_DISABLE |
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COH901318_CX_CTRL_TC_IRQ_DISABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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.param.ctrl_lli = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_DISABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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.param.ctrl_lli_last = 0 |
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COH901318_CX_CTRL_TC_ENABLE |
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COH901318_CX_CTRL_MASTER_MODE_M1RW |
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COH901318_CX_CTRL_TCP_DISABLE |
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COH901318_CX_CTRL_TC_IRQ_ENABLE |
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COH901318_CX_CTRL_HSP_ENABLE |
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COH901318_CX_CTRL_HSS_DISABLE |
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COH901318_CX_CTRL_DDMA_LEGACY,
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},
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{
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.number = U300_DMA_GENERAL_PURPOSE_0,
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@ -1617,7 +1756,7 @@ static void __init u300_init_check_chip(void)
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#endif
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#ifdef CONFIG_MACH_U300_BS335
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if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
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printk(KERN_ERR "Platform configured for BS365 " \
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printk(KERN_ERR "Platform configured for BS335 " \
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" with DB3350 but %s detected, expect problems!",
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chipname);
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}
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@ -1692,12 +1831,12 @@ void __init u300_init_devices(void)
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/* Register subdevices on the I2C buses */
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u300_i2c_register_board_devices();
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/* Register subdevices on the SPI bus */
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u300_spi_register_board_devices();
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/* Register the platform devices */
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platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
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/* Register subdevices on the SPI bus */
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u300_spi_register_board_devices();
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#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
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/*
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* Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
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@ -3,19 +3,22 @@
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* arch/arm/mach-u300/mmc.c
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*
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*
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* Copyright (C) 2009 ST-Ericsson AB
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* Copyright (C) 2009 ST-Ericsson SA
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* License terms: GNU General Public License (GPL) version 2
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*
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* Author: Linus Walleij <linus.walleij@stericsson.com>
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* Author: Johan Lundin <johan.lundin@stericsson.com>
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* Author: Johan Lundin
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* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
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*/
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#include <linux/device.h>
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#include <linux/amba/bus.h>
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#include <linux/mmc/host.h>
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#include <linux/gpio.h>
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#include <linux/dmaengine.h>
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#include <linux/amba/mmci.h>
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#include <linux/slab.h>
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#include <mach/coh901318.h>
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#include <mach/dma_channels.h>
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#include "mmc.h"
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#include "padmux.h"
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@ -32,6 +35,11 @@ static struct mmci_platform_data mmc0_plat_data = {
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.cd_invert = true,
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.capabilities = MMC_CAP_MMC_HIGHSPEED |
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MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
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#ifdef CONFIG_COH901318
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.dma_filter = coh901318_filter_id,
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.dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
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/* Don't specify a TX channel, this RX channel is bidirectional */
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#endif
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};
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int __devinit mmc_init(struct amba_device *adev)
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@ -11,6 +11,9 @@
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#include <linux/spi/spi.h>
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#include <linux/amba/pl022.h>
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#include <linux/err.h>
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#include <mach/coh901318.h>
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#include <mach/dma_channels.h>
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#include "padmux.h"
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/*
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@ -30,11 +33,8 @@ static void select_dummy_chip(u32 chipselect)
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}
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struct pl022_config_chip dummy_chip_info = {
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/*
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* available POLLING_TRANSFER and INTERRUPT_TRANSFER,
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* DMA_TRANSFER does not work
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*/
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.com_mode = INTERRUPT_TRANSFER,
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/* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
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.com_mode = DMA_TRANSFER,
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.iface = SSP_INTERFACE_MOTOROLA_SPI,
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/* We can only act as master but SSP_SLAVE is possible in theory */
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.hierarchy = SSP_MASTER,
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@ -75,8 +75,6 @@ static struct spi_board_info u300_spi_devices[] = {
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static struct pl022_ssp_controller ssp_platform_data = {
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/* If you have several SPI buses this varies, we have only bus 0 */
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.bus_id = 0,
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/* Set this to 1 when we think we got DMA working */
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.enable_dma = 0,
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/*
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* On the APP CPU GPIO 4, 5 and 6 are connected as generic
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* chip selects for SPI. (Same on U330, U335 and U365.)
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@ -84,6 +82,14 @@ static struct pl022_ssp_controller ssp_platform_data = {
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* and do padmuxing accordingly too.
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*/
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.num_chipselect = 3,
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#ifdef CONFIG_COH901318
|
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.enable_dma = 1,
|
||||
.dma_filter = coh901318_filter_id,
|
||||
.dma_rx_param = (void *) U300_DMA_SPI_RX,
|
||||
.dma_tx_param = (void *) U300_DMA_SPI_TX,
|
||||
#else
|
||||
.enable_dma = 0,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
@ -109,6 +115,7 @@ void __init u300_spi_init(struct amba_device *adev)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void __init u300_spi_register_board_devices(void)
|
||||
{
|
||||
/* Register any SPI devices */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user