forked from Minki/linux
qedr: Add support for RoCE HW init
Allocate and setup RoCE resources, interrupts and completion queues. Adds device attributes. Signed-off-by: Rajesh Borundia <rajesh.borundia@cavium.com> Signed-off-by: Ram Amrani <Ram.Amrani@cavium.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
Ram Amrani
Doug Ledford
parent
2e0cbc4dd0
commit
ec72fce401
@ -36,6 +36,8 @@
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#include <linux/iommu.h>
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#include <net/addrconf.h>
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#include <linux/qed/qede_roce.h>
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#include <linux/qed/qed_chain.h>
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#include <linux/qed/qed_if.h>
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#include "qedr.h"
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MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
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@ -61,6 +63,17 @@ static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
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return IB_LINK_LAYER_ETHERNET;
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}
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static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str,
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size_t str_len)
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{
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struct qedr_dev *qedr = get_qedr_dev(ibdev);
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u32 fw_ver = (u32)qedr->attr.fw_ver;
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snprintf(str, str_len, "%d. %d. %d. %d",
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(fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
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(fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
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}
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static int qedr_register_device(struct qedr_dev *dev)
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{
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strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX);
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@ -69,10 +82,139 @@ static int qedr_register_device(struct qedr_dev *dev)
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dev->ibdev.owner = THIS_MODULE;
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dev->ibdev.get_link_layer = qedr_link_layer;
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dev->ibdev.get_dev_fw_str = qedr_get_dev_fw_str;
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return 0;
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}
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/* This function allocates fast-path status block memory */
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static int qedr_alloc_mem_sb(struct qedr_dev *dev,
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struct qed_sb_info *sb_info, u16 sb_id)
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{
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struct status_block *sb_virt;
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dma_addr_t sb_phys;
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int rc;
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sb_virt = dma_alloc_coherent(&dev->pdev->dev,
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sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
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if (!sb_virt)
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return -ENOMEM;
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rc = dev->ops->common->sb_init(dev->cdev, sb_info,
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sb_virt, sb_phys, sb_id,
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QED_SB_TYPE_CNQ);
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if (rc) {
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pr_err("Status block initialization failed\n");
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dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
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sb_virt, sb_phys);
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return rc;
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}
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return 0;
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}
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static void qedr_free_mem_sb(struct qedr_dev *dev,
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struct qed_sb_info *sb_info, int sb_id)
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{
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if (sb_info->sb_virt) {
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dev->ops->common->sb_release(dev->cdev, sb_info, sb_id);
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dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
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(void *)sb_info->sb_virt, sb_info->sb_phys);
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}
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}
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static void qedr_free_resources(struct qedr_dev *dev)
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{
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int i;
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for (i = 0; i < dev->num_cnq; i++) {
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qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
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dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
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}
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kfree(dev->cnq_array);
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kfree(dev->sb_array);
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kfree(dev->sgid_tbl);
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}
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static int qedr_alloc_resources(struct qedr_dev *dev)
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{
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struct qedr_cnq *cnq;
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__le16 *cons_pi;
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u16 n_entries;
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int i, rc;
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dev->sgid_tbl = kzalloc(sizeof(union ib_gid) *
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QEDR_MAX_SGID, GFP_KERNEL);
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if (!dev->sgid_tbl)
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return -ENOMEM;
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spin_lock_init(&dev->sgid_lock);
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/* Allocate Status blocks for CNQ */
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dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
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GFP_KERNEL);
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if (!dev->sb_array) {
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rc = -ENOMEM;
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goto err1;
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}
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dev->cnq_array = kcalloc(dev->num_cnq,
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sizeof(*dev->cnq_array), GFP_KERNEL);
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if (!dev->cnq_array) {
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rc = -ENOMEM;
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goto err2;
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}
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dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
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/* Allocate CNQ PBLs */
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n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE);
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for (i = 0; i < dev->num_cnq; i++) {
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cnq = &dev->cnq_array[i];
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rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
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dev->sb_start + i);
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if (rc)
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goto err3;
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rc = dev->ops->common->chain_alloc(dev->cdev,
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QED_CHAIN_USE_TO_CONSUME,
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QED_CHAIN_MODE_PBL,
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QED_CHAIN_CNT_TYPE_U16,
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n_entries,
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sizeof(struct regpair *),
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&cnq->pbl);
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if (rc)
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goto err4;
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cnq->dev = dev;
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cnq->sb = &dev->sb_array[i];
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cons_pi = dev->sb_array[i].sb_virt->pi_array;
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cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
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cnq->index = i;
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sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
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DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
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i, qed_chain_get_cons_idx(&cnq->pbl));
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}
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return 0;
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err4:
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qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
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err3:
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for (--i; i >= 0; i--) {
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dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
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qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
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}
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kfree(dev->cnq_array);
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err2:
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kfree(dev->sb_array);
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err1:
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kfree(dev->sgid_tbl);
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return rc;
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}
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/* QEDR sysfs interface */
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static ssize_t show_rev(struct device *device, struct device_attribute *attr,
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char *buf)
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@ -146,9 +288,240 @@ static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
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}
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}
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static const struct qed_rdma_ops *qed_ops;
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#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
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static irqreturn_t qedr_irq_handler(int irq, void *handle)
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{
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u16 hw_comp_cons, sw_comp_cons;
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struct qedr_cnq *cnq = handle;
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qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
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qed_sb_update_sb_idx(cnq->sb);
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hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
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sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
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/* Align protocol-index and chain reads */
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rmb();
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while (sw_comp_cons != hw_comp_cons) {
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sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
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cnq->n_comp++;
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}
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qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
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sw_comp_cons);
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qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
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return IRQ_HANDLED;
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}
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static void qedr_sync_free_irqs(struct qedr_dev *dev)
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{
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u32 vector;
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int i;
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for (i = 0; i < dev->int_info.used_cnt; i++) {
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if (dev->int_info.msix_cnt) {
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vector = dev->int_info.msix[i * dev->num_hwfns].vector;
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synchronize_irq(vector);
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free_irq(vector, &dev->cnq_array[i]);
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}
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}
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dev->int_info.used_cnt = 0;
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}
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static int qedr_req_msix_irqs(struct qedr_dev *dev)
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{
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int i, rc = 0;
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if (dev->num_cnq > dev->int_info.msix_cnt) {
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DP_ERR(dev,
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"Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
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dev->num_cnq, dev->int_info.msix_cnt);
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return -EINVAL;
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}
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for (i = 0; i < dev->num_cnq; i++) {
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rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector,
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qedr_irq_handler, 0, dev->cnq_array[i].name,
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&dev->cnq_array[i]);
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if (rc) {
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DP_ERR(dev, "Request cnq %d irq failed\n", i);
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qedr_sync_free_irqs(dev);
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} else {
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DP_DEBUG(dev, QEDR_MSG_INIT,
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"Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
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dev->cnq_array[i].name, i,
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&dev->cnq_array[i]);
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dev->int_info.used_cnt++;
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}
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}
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return rc;
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}
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static int qedr_setup_irqs(struct qedr_dev *dev)
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{
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int rc;
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DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
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/* Learn Interrupt configuration */
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rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
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if (rc < 0)
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return rc;
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rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
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if (rc) {
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DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
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return rc;
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}
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if (dev->int_info.msix_cnt) {
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DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
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dev->int_info.msix_cnt);
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rc = qedr_req_msix_irqs(dev);
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if (rc)
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return rc;
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}
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DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
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return 0;
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}
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static int qedr_set_device_attr(struct qedr_dev *dev)
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{
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struct qed_rdma_device *qed_attr;
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struct qedr_device_attr *attr;
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u32 page_size;
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/* Part 1 - query core capabilities */
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qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
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/* Part 2 - check capabilities */
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page_size = ~dev->attr.page_size_caps + 1;
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if (page_size > PAGE_SIZE) {
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DP_ERR(dev,
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"Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
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PAGE_SIZE, page_size);
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return -ENODEV;
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}
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/* Part 3 - copy and update capabilities */
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attr = &dev->attr;
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attr->vendor_id = qed_attr->vendor_id;
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attr->vendor_part_id = qed_attr->vendor_part_id;
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attr->hw_ver = qed_attr->hw_ver;
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attr->fw_ver = qed_attr->fw_ver;
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attr->node_guid = qed_attr->node_guid;
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attr->sys_image_guid = qed_attr->sys_image_guid;
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attr->max_cnq = qed_attr->max_cnq;
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attr->max_sge = qed_attr->max_sge;
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attr->max_inline = qed_attr->max_inline;
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attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
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attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
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attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
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attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
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attr->max_dev_resp_rd_atomic_resc =
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qed_attr->max_dev_resp_rd_atomic_resc;
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attr->max_cq = qed_attr->max_cq;
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attr->max_qp = qed_attr->max_qp;
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attr->max_mr = qed_attr->max_mr;
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attr->max_mr_size = qed_attr->max_mr_size;
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attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
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attr->max_mw = qed_attr->max_mw;
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attr->max_fmr = qed_attr->max_fmr;
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attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
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attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
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attr->max_pd = qed_attr->max_pd;
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attr->max_ah = qed_attr->max_ah;
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attr->max_pkey = qed_attr->max_pkey;
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attr->max_srq = qed_attr->max_srq;
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attr->max_srq_wr = qed_attr->max_srq_wr;
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attr->dev_caps = qed_attr->dev_caps;
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attr->page_size_caps = qed_attr->page_size_caps;
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attr->dev_ack_delay = qed_attr->dev_ack_delay;
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attr->reserved_lkey = qed_attr->reserved_lkey;
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attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
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attr->max_stats_queues = qed_attr->max_stats_queues;
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return 0;
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}
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static int qedr_init_hw(struct qedr_dev *dev)
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{
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struct qed_rdma_add_user_out_params out_params;
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struct qed_rdma_start_in_params *in_params;
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struct qed_rdma_cnq_params *cur_pbl;
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struct qed_rdma_events events;
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dma_addr_t p_phys_table;
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u32 page_cnt;
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int rc = 0;
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int i;
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in_params = kzalloc(sizeof(*in_params), GFP_KERNEL);
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if (!in_params) {
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rc = -ENOMEM;
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goto out;
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}
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in_params->desired_cnq = dev->num_cnq;
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for (i = 0; i < dev->num_cnq; i++) {
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cur_pbl = &in_params->cnq_pbl_list[i];
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page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
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cur_pbl->num_pbl_pages = page_cnt;
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p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
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cur_pbl->pbl_ptr = (u64)p_phys_table;
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}
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events.context = dev;
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in_params->events = &events;
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in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
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in_params->max_mtu = dev->ndev->mtu;
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ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
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rc = dev->ops->rdma_init(dev->cdev, in_params);
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if (rc)
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goto out;
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rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
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if (rc)
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goto out;
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dev->db_addr = (void *)(uintptr_t)out_params.dpi_addr;
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dev->db_phys_addr = out_params.dpi_phys_addr;
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dev->db_size = out_params.dpi_size;
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dev->dpi = out_params.dpi;
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rc = qedr_set_device_attr(dev);
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out:
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kfree(in_params);
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if (rc)
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DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
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return rc;
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}
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void qedr_stop_hw(struct qedr_dev *dev)
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{
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dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
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dev->ops->rdma_stop(dev->rdma_ctx);
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}
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static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
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struct net_device *ndev)
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{
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struct qed_dev_rdma_info dev_info;
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struct qedr_dev *dev;
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int rc = 0, i;
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@ -164,21 +537,59 @@ static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
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dev->ndev = ndev;
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dev->cdev = cdev;
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qed_ops = qed_get_rdma_ops();
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if (!qed_ops) {
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DP_ERR(dev, "Failed to get qed roce operations\n");
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goto init_err;
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}
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dev->ops = qed_ops;
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rc = qed_ops->fill_dev_info(cdev, &dev_info);
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if (rc)
|
||||
goto init_err;
|
||||
|
||||
dev->num_hwfns = dev_info.common.num_hwfns;
|
||||
dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
|
||||
|
||||
dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
|
||||
if (!dev->num_cnq) {
|
||||
DP_ERR(dev, "not enough CNQ resources.\n");
|
||||
goto init_err;
|
||||
}
|
||||
|
||||
qedr_pci_set_atomic(dev, pdev);
|
||||
|
||||
rc = qedr_alloc_resources(dev);
|
||||
if (rc)
|
||||
goto init_err;
|
||||
|
||||
rc = qedr_init_hw(dev);
|
||||
if (rc)
|
||||
goto alloc_err;
|
||||
|
||||
rc = qedr_setup_irqs(dev);
|
||||
if (rc)
|
||||
goto irq_err;
|
||||
|
||||
rc = qedr_register_device(dev);
|
||||
if (rc) {
|
||||
DP_ERR(dev, "Unable to allocate register device\n");
|
||||
goto init_err;
|
||||
goto reg_err;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
|
||||
if (device_create_file(&dev->ibdev.dev, qedr_attributes[i]))
|
||||
goto init_err;
|
||||
goto reg_err;
|
||||
|
||||
DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
|
||||
return dev;
|
||||
|
||||
reg_err:
|
||||
qedr_sync_free_irqs(dev);
|
||||
irq_err:
|
||||
qedr_stop_hw(dev);
|
||||
alloc_err:
|
||||
qedr_free_resources(dev);
|
||||
init_err:
|
||||
ib_dealloc_device(&dev->ibdev);
|
||||
DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
|
||||
@ -193,6 +604,9 @@ static void qedr_remove(struct qedr_dev *dev)
|
||||
*/
|
||||
qedr_remove_sysfiles(dev);
|
||||
|
||||
qedr_stop_hw(dev);
|
||||
qedr_sync_free_irqs(dev);
|
||||
qedr_free_resources(dev);
|
||||
ib_dealloc_device(&dev->ibdev);
|
||||
}
|
||||
|
||||
|
||||
@ -35,7 +35,10 @@
|
||||
#include <linux/pci.h>
|
||||
#include <rdma/ib_addr.h>
|
||||
#include <linux/qed/qed_if.h>
|
||||
#include <linux/qed/qed_chain.h>
|
||||
#include <linux/qed/qed_roce_if.h>
|
||||
#include <linux/qed/qede_roce.h>
|
||||
#include "qedr_hsi.h"
|
||||
|
||||
#define QEDR_MODULE_VERSION "8.10.10.0"
|
||||
#define QEDR_NODE_DESC "QLogic 579xx RoCE HCA"
|
||||
@ -47,6 +50,60 @@
|
||||
|
||||
#define QEDR_MSG_INIT "INIT"
|
||||
|
||||
struct qedr_dev;
|
||||
|
||||
struct qedr_cnq {
|
||||
struct qedr_dev *dev;
|
||||
struct qed_chain pbl;
|
||||
struct qed_sb_info *sb;
|
||||
char name[32];
|
||||
u64 n_comp;
|
||||
__le16 *hw_cons_ptr;
|
||||
u8 index;
|
||||
};
|
||||
|
||||
#define QEDR_MAX_SGID 128
|
||||
|
||||
struct qedr_device_attr {
|
||||
u32 vendor_id;
|
||||
u32 vendor_part_id;
|
||||
u32 hw_ver;
|
||||
u64 fw_ver;
|
||||
u64 node_guid;
|
||||
u64 sys_image_guid;
|
||||
u8 max_cnq;
|
||||
u8 max_sge;
|
||||
u16 max_inline;
|
||||
u32 max_sqe;
|
||||
u32 max_rqe;
|
||||
u8 max_qp_resp_rd_atomic_resc;
|
||||
u8 max_qp_req_rd_atomic_resc;
|
||||
u64 max_dev_resp_rd_atomic_resc;
|
||||
u32 max_cq;
|
||||
u32 max_qp;
|
||||
u32 max_mr;
|
||||
u64 max_mr_size;
|
||||
u32 max_cqe;
|
||||
u32 max_mw;
|
||||
u32 max_fmr;
|
||||
u32 max_mr_mw_fmr_pbl;
|
||||
u64 max_mr_mw_fmr_size;
|
||||
u32 max_pd;
|
||||
u32 max_ah;
|
||||
u8 max_pkey;
|
||||
u32 max_srq;
|
||||
u32 max_srq_wr;
|
||||
u8 max_srq_sge;
|
||||
u8 max_stats_queues;
|
||||
u32 dev_caps;
|
||||
|
||||
u64 page_size_caps;
|
||||
u8 dev_ack_delay;
|
||||
u32 reserved_lkey;
|
||||
u32 bad_pkey_counter;
|
||||
struct qed_rdma_events events;
|
||||
};
|
||||
|
||||
struct qedr_dev {
|
||||
struct ib_device ibdev;
|
||||
struct qed_dev *cdev;
|
||||
@ -55,7 +112,73 @@ struct qedr_dev {
|
||||
|
||||
enum ib_atomic_cap atomic_cap;
|
||||
|
||||
void *rdma_ctx;
|
||||
struct qedr_device_attr attr;
|
||||
|
||||
const struct qed_rdma_ops *ops;
|
||||
struct qed_int_info int_info;
|
||||
|
||||
struct qed_sb_info *sb_array;
|
||||
struct qedr_cnq *cnq_array;
|
||||
int num_cnq;
|
||||
int sb_start;
|
||||
|
||||
void __iomem *db_addr;
|
||||
u64 db_phys_addr;
|
||||
u32 db_size;
|
||||
u16 dpi;
|
||||
|
||||
union ib_gid *sgid_tbl;
|
||||
|
||||
/* Lock for sgid table */
|
||||
spinlock_t sgid_lock;
|
||||
|
||||
u64 guid;
|
||||
|
||||
u32 dp_module;
|
||||
u8 dp_level;
|
||||
u8 num_hwfns;
|
||||
};
|
||||
|
||||
#define QEDR_MAX_SQ_PBL (0x8000)
|
||||
#define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *))
|
||||
#define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge))
|
||||
#define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \
|
||||
QEDR_SQE_ELEMENT_SIZE)
|
||||
#define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
|
||||
QEDR_SQE_ELEMENT_SIZE)
|
||||
#define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\
|
||||
(RDMA_RING_PAGE_SIZE) / \
|
||||
(QEDR_SQE_ELEMENT_SIZE) /\
|
||||
(QEDR_MAX_SQE_ELEMENTS_PER_SQE))
|
||||
/* RQ */
|
||||
#define QEDR_MAX_RQ_PBL (0x2000)
|
||||
#define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *))
|
||||
#define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge))
|
||||
#define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE)
|
||||
#define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
|
||||
QEDR_RQE_ELEMENT_SIZE)
|
||||
#define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\
|
||||
(RDMA_RING_PAGE_SIZE) / \
|
||||
(QEDR_RQE_ELEMENT_SIZE) /\
|
||||
(QEDR_MAX_RQE_ELEMENTS_PER_RQE))
|
||||
|
||||
#define QEDR_CQE_SIZE (sizeof(union rdma_cqe))
|
||||
#define QEDR_MAX_CQE_PBL_SIZE (512 * 1024)
|
||||
#define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \
|
||||
sizeof(u64)) - 1)
|
||||
#define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \
|
||||
(QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE))
|
||||
|
||||
#define QEDR_ROCE_MAX_CNQ_SIZE (0x4000)
|
||||
|
||||
#define QEDR_MAX_PORT (1)
|
||||
|
||||
#define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
|
||||
|
||||
static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev)
|
||||
{
|
||||
return container_of(ibdev, struct qedr_dev, ibdev);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
56
drivers/infiniband/hw/qedr/qedr_hsi.h
Normal file
56
drivers/infiniband/hw/qedr/qedr_hsi.h
Normal file
@ -0,0 +1,56 @@
|
||||
/* QLogic qedr NIC Driver
|
||||
* Copyright (c) 2015-2016 QLogic Corporation
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the
|
||||
* OpenIB.org BSD license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
||||
* conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer.
|
||||
*
|
||||
* - Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and /or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
#ifndef __QED_HSI_ROCE__
|
||||
#define __QED_HSI_ROCE__
|
||||
|
||||
#include <linux/qed/common_hsi.h>
|
||||
#include <linux/qed/roce_common.h>
|
||||
#include "qedr_hsi_rdma.h"
|
||||
|
||||
/* Affiliated asynchronous events / errors enumeration */
|
||||
enum roce_async_events_type {
|
||||
ROCE_ASYNC_EVENT_NONE = 0,
|
||||
ROCE_ASYNC_EVENT_COMM_EST = 1,
|
||||
ROCE_ASYNC_EVENT_SQ_DRAINED,
|
||||
ROCE_ASYNC_EVENT_SRQ_LIMIT,
|
||||
ROCE_ASYNC_EVENT_LAST_WQE_REACHED,
|
||||
ROCE_ASYNC_EVENT_CQ_ERR,
|
||||
ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR,
|
||||
ROCE_ASYNC_EVENT_LOCAL_CATASTROPHIC_ERR,
|
||||
ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR,
|
||||
ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR,
|
||||
ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR,
|
||||
ROCE_ASYNC_EVENT_SRQ_EMPTY,
|
||||
MAX_ROCE_ASYNC_EVENTS_TYPE
|
||||
};
|
||||
|
||||
#endif /* __QED_HSI_ROCE__ */
|
||||
96
drivers/infiniband/hw/qedr/qedr_hsi_rdma.h
Normal file
96
drivers/infiniband/hw/qedr/qedr_hsi_rdma.h
Normal file
@ -0,0 +1,96 @@
|
||||
/* QLogic qedr NIC Driver
|
||||
* Copyright (c) 2015-2016 QLogic Corporation
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the
|
||||
* OpenIB.org BSD license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or
|
||||
* without modification, are permitted provided that the following
|
||||
* conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer.
|
||||
*
|
||||
* - Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and /or other materials
|
||||
* provided with the distribution.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
#ifndef __QED_HSI_RDMA__
|
||||
#define __QED_HSI_RDMA__
|
||||
|
||||
#include <linux/qed/rdma_common.h>
|
||||
|
||||
/* rdma completion notification queue element */
|
||||
struct rdma_cnqe {
|
||||
struct regpair cq_handle;
|
||||
};
|
||||
|
||||
struct rdma_cqe_responder {
|
||||
struct regpair srq_wr_id;
|
||||
struct regpair qp_handle;
|
||||
__le32 imm_data_or_inv_r_Key;
|
||||
__le32 length;
|
||||
__le32 imm_data_hi;
|
||||
__le16 rq_cons;
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
struct rdma_cqe_requester {
|
||||
__le16 sq_cons;
|
||||
__le16 reserved0;
|
||||
__le32 reserved1;
|
||||
struct regpair qp_handle;
|
||||
struct regpair reserved2;
|
||||
__le32 reserved3;
|
||||
__le16 reserved4;
|
||||
u8 flags;
|
||||
u8 status;
|
||||
};
|
||||
|
||||
struct rdma_cqe_common {
|
||||
struct regpair reserved0;
|
||||
struct regpair qp_handle;
|
||||
__le16 reserved1[7];
|
||||
u8 flags;
|
||||
u8 status;
|
||||
};
|
||||
|
||||
/* rdma completion queue element */
|
||||
union rdma_cqe {
|
||||
struct rdma_cqe_responder resp;
|
||||
struct rdma_cqe_requester req;
|
||||
struct rdma_cqe_common cmn;
|
||||
};
|
||||
|
||||
struct rdma_sq_sge {
|
||||
__le32 length;
|
||||
struct regpair addr;
|
||||
__le32 l_key;
|
||||
};
|
||||
|
||||
struct rdma_rq_sge {
|
||||
struct regpair addr;
|
||||
__le32 length;
|
||||
__le32 flags;
|
||||
};
|
||||
|
||||
struct rdma_srq_sge {
|
||||
struct regpair addr;
|
||||
__le32 length;
|
||||
__le32 l_key;
|
||||
};
|
||||
#endif /* __QED_HSI_RDMA__ */
|
||||
Loading…
Reference in New Issue
Block a user