Last minute fixes for ARC
- Build error in Mellanox nps platform - addressing lack of saving FPU regs in releavnt configs -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIbBAABAgAGBQJY/7Y9AAoJEGnX8d3iisJerOIP+OIw4iInJEycs2A1lQxMTUAa DFny0uv1EuWD5cC7g1O3m/SGIeN14zt6WBo40VHgxiOw/VFDsk4fze/QyfA+FFj0 Qr7c5UDQKsWCNUNwkAfUYqp5/HWM9cO+WlUr3JbKL5sThh0SOBhb09T+Z9BEh+Ns jMu4VKa1Jh8RuXPd0Wb86CEhkRalTySTbY3og6g4F+HYRPvvqHvigdJ3yPI/mh0E ToPbZcqCNqgpJ0vyHak+QXb1gSbMjlevmjmokJR9O49Ypb8jEvQjwkZE0I81N793 ayEftdCL9zVQ3WCcGVrhviXOMuxvDcimNUrAQiDJBqBSGEjq9AVaejEi1DIOyT3X InN1SmZPKno64OuZSFVDF2IuwTAumNXjp886of7LNy76lnznov2VvTXiiJSG/2ZE QEyhIq++DWFns+1IerJfU7QjzHEmx3StibBgPYur6K1dN49iHsFBTgRGgKzEhd0L iUOQQajg0RoYBhrcS/HQXBQgJhu0Fpkx6csDTtmW66hgw95I6ZoPJshk8SvouRTg Lif/U/qOd86Bghwj0V5pw/504LQ9i8xfSZzidM+St8XvhEa/DwuTggVuoIzOB8AH 6qOExsN75jwExjAR71JsI33jNNTdTQ7HaHaqB1DQJ+2y12QmttNXaPy/iLYqQNsN iLeZ6MKdCrXKr73t2Js= =wA0V -----END PGP SIGNATURE----- Merge tag 'arc-4.11-final' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC fix from Vineet Gupta: "Last minute fixes for ARC: - build error in Mellanox nps platform - addressing lack of saving FPU regs in releavnt configs" * tag 'arc-4.11-final' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARCv2: entry: save Accumulator register pair (r58:59) if present ARC: [plat-eznps] Fix build error
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commit
ea839b4174
arch/arc
@ -406,6 +406,14 @@ config ARC_HAS_DIV_REM
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bool "Insn: div, divu, rem, remu"
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default y
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config ARC_HAS_ACCL_REGS
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bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
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default n
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help
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Depending on the configuration, CPU can contain accumulator reg-pair
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(also referred to as r58:r59). These can also be used by gcc as GPR so
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kernel needs to save/restore per process
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endif # ISA_ARCV2
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endmenu # "ARC CPU Configuration"
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@ -17,10 +17,11 @@
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#include <asm/barrier.h>
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#include <asm/smp.h>
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#define ATOMIC_INIT(i) { (i) }
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#ifndef CONFIG_ARC_PLAT_EZNPS
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#define atomic_read(v) READ_ONCE((v)->counter)
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#define ATOMIC_INIT(i) { (i) }
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#ifdef CONFIG_ARC_HAS_LLSC
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@ -16,6 +16,11 @@
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;
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; Now manually save: r12, sp, fp, gp, r25
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#ifdef CONFIG_ARC_HAS_ACCL_REGS
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PUSH r59
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PUSH r58
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#endif
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PUSH r30
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PUSH r12
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@ -75,6 +80,11 @@
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POP r12
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POP r30
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#ifdef CONFIG_ARC_HAS_ACCL_REGS
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POP r58
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POP r59
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#endif
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.endm
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/*------------------------------------------------------------------------*/
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@ -86,6 +86,10 @@ struct pt_regs {
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unsigned long r12, r30;
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#ifdef CONFIG_ARC_HAS_ACCL_REGS
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unsigned long r58, r59; /* ACCL/ACCH used by FPU / DSP MPY */
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#endif
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/*------- Below list auto saved by h/w -----------*/
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unsigned long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11;
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@ -319,7 +319,8 @@ static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
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static void arc_chk_core_config(void)
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{
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struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
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int fpu_enabled;
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int saved = 0, present = 0;
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char *opt_nm = NULL;;
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if (!cpu->extn.timer0)
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panic("Timer0 is not present!\n");
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@ -346,17 +347,28 @@ static void arc_chk_core_config(void)
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/*
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* FP hardware/software config sanity
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* -If hardware contains DPFP, kernel needs to save/restore FPU state
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* -If hardware present, kernel needs to save/restore FPU state
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* -If not, it will crash trying to save/restore the non-existant regs
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*
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* (only DPDP checked since SP has no arch visible regs)
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*/
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fpu_enabled = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE);
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if (cpu->extn.fpu_dp && !fpu_enabled)
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pr_warn("CONFIG_ARC_FPU_SAVE_RESTORE needed for working apps\n");
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else if (!cpu->extn.fpu_dp && fpu_enabled)
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panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n");
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if (is_isa_arcompact()) {
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opt_nm = "CONFIG_ARC_FPU_SAVE_RESTORE";
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saved = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE);
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/* only DPDP checked since SP has no arch visible regs */
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present = cpu->extn.fpu_dp;
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} else {
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opt_nm = "CONFIG_ARC_HAS_ACCL_REGS";
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saved = IS_ENABLED(CONFIG_ARC_HAS_ACCL_REGS);
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/* Accumulator Low:High pair (r58:59) present if DSP MPY or FPU */
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present = cpu->extn_mpy.dsp | cpu->extn.fpu_sp | cpu->extn.fpu_dp;
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}
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if (present && !saved)
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pr_warn("Enable %s for working apps\n", opt_nm);
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else if (!present && saved)
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panic("Disable %s, hardware NOT present\n", opt_nm);
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}
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/*
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