forked from Minki/linux
IB/mlx4: Use multiple WQ blocks to post smaller send WQEs
ConnectX HCA supports shrinking WQEs, so that a single work request can be made of multiple units of wqe_shift. This way, WRs can differ in size, and do not have to be a power of 2 in size, saving memory and speeding up send WR posting. Unfortunately, if we do this then the wqe_index field in CQEs can't be used to look up the WR ID anymore, so our implementation does this only if selective signaling is off. Further, on 32-bit platforms, we can't use vmap() to make the QP buffer virtually contigious. Thus we have to use constant-sized WRs to make sure a WR is always fully within a single page-sized chunk. Finally, we use WRs with the NOP opcode to avoid wrapping around the queue buffer in the middle of posting a WR, and we set the NoErrorCompletion bit to avoid getting completions with error for NOP WRs. However, NEC is only supported starting with firmware 2.2.232, so we use constant-sized WRs for older firmware. And, since MLX QPs only support SEND, we use constant-sized WRs in this case. When stamping during NOP posting, do stamping following setting of the NOP WQE valid bit. Signed-off-by: Michael S. Tsirkin <mst@dev.mellanox.co.il> Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
This commit is contained in:
Jack Morgenstein
Roland Dreier
parent
b57aacfa7a
commit
ea54b10c77
@ -326,6 +326,12 @@ static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
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is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
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MLX4_CQE_OPCODE_ERROR;
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if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP &&
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is_send)) {
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printk(KERN_WARNING "Completion for NOP opcode detected!\n");
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return -EINVAL;
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}
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if (!*cur_qp ||
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(be32_to_cpu(cqe->my_qpn) & 0xffffff) != (*cur_qp)->mqp.qpn) {
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/*
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@ -348,8 +354,10 @@ static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
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if (is_send) {
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wq = &(*cur_qp)->sq;
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wqe_ctr = be16_to_cpu(cqe->wqe_index);
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wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
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if (!(*cur_qp)->sq_signal_bits) {
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wqe_ctr = be16_to_cpu(cqe->wqe_index);
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wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
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}
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wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
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++wq->tail;
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} else if ((*cur_qp)->ibqp.srq) {
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@ -120,6 +120,8 @@ struct mlx4_ib_qp {
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u32 doorbell_qpn;
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__be32 sq_signal_bits;
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unsigned sq_next_wqe;
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int sq_max_wqes_per_wr;
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int sq_spare_wqes;
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struct mlx4_ib_wq sq;
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@ -30,6 +30,8 @@
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* SOFTWARE.
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*/
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#include <linux/log2.h>
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#include <rdma/ib_cache.h>
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#include <rdma/ib_pack.h>
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@ -111,16 +113,87 @@ static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
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/*
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* Stamp a SQ WQE so that it is invalid if prefetched by marking the
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* first four bytes of every 64 byte chunk with 0xffffffff, except for
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* the very first chunk of the WQE.
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* first four bytes of every 64 byte chunk with
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* 0x7FFFFFF | (invalid_ownership_value << 31).
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*
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* When the max work request size is less than or equal to the WQE
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* basic block size, as an optimization, we can stamp all WQEs with
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* 0xffffffff, and skip the very first chunk of each WQE.
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*/
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static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
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static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
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{
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u32 *wqe = get_send_wqe(qp, n);
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u32 *wqe;
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int i;
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int s;
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int ind;
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void *buf;
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__be32 stamp;
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for (i = 16; i < 1 << (qp->sq.wqe_shift - 2); i += 16)
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wqe[i] = 0xffffffff;
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s = roundup(size, 1U << qp->sq.wqe_shift);
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if (qp->sq_max_wqes_per_wr > 1) {
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for (i = 0; i < s; i += 64) {
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ind = (i >> qp->sq.wqe_shift) + n;
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stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
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cpu_to_be32(0xffffffff);
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buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
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wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
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*wqe = stamp;
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}
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} else {
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buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
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for (i = 64; i < s; i += 64) {
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wqe = buf + i;
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*wqe = 0xffffffff;
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}
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}
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}
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static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
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{
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struct mlx4_wqe_ctrl_seg *ctrl;
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struct mlx4_wqe_inline_seg *inl;
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void *wqe;
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int s;
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ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
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s = sizeof(struct mlx4_wqe_ctrl_seg);
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if (qp->ibqp.qp_type == IB_QPT_UD) {
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struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
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struct mlx4_av *av = (struct mlx4_av *)dgram->av;
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memset(dgram, 0, sizeof *dgram);
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av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
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s += sizeof(struct mlx4_wqe_datagram_seg);
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}
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/* Pad the remainder of the WQE with an inline data segment. */
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if (size > s) {
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inl = wqe + s;
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inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
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}
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ctrl->srcrb_flags = 0;
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ctrl->fence_size = size / 16;
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/*
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* Make sure descriptor is fully written before setting ownership bit
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* (because HW can start executing as soon as we do).
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*/
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wmb();
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ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
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(n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
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stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
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}
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/* Post NOP WQE to prevent wrap-around in the middle of WR */
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static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
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{
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unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
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if (unlikely(s < qp->sq_max_wqes_per_wr)) {
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post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
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ind += s;
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}
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return ind;
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}
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static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
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@ -237,6 +310,8 @@ static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
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static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
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enum ib_qp_type type, struct mlx4_ib_qp *qp)
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{
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int s;
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/* Sanity check SQ size before proceeding */
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if (cap->max_send_wr > dev->dev->caps.max_wqes ||
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cap->max_send_sge > dev->dev->caps.max_sq_sg ||
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@ -252,20 +327,74 @@ static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
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cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
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return -EINVAL;
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qp->sq.wqe_shift = ilog2(roundup_pow_of_two(max(cap->max_send_sge *
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sizeof (struct mlx4_wqe_data_seg),
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cap->max_inline_data +
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sizeof (struct mlx4_wqe_inline_seg)) +
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send_wqe_overhead(type)));
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qp->sq.max_gs = ((1 << qp->sq.wqe_shift) - send_wqe_overhead(type)) /
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sizeof (struct mlx4_wqe_data_seg);
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s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
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cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
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send_wqe_overhead(type);
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/*
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* We need to leave 2 KB + 1 WQE of headroom in the SQ to
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* allow HW to prefetch.
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* Hermon supports shrinking WQEs, such that a single work
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* request can include multiple units of 1 << wqe_shift. This
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* way, work requests can differ in size, and do not have to
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* be a power of 2 in size, saving memory and speeding up send
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* WR posting. Unfortunately, if we do this then the
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* wqe_index field in CQEs can't be used to look up the WR ID
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* anymore, so we do this only if selective signaling is off.
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*
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* Further, on 32-bit platforms, we can't use vmap() to make
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* the QP buffer virtually contigious. Thus we have to use
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* constant-sized WRs to make sure a WR is always fully within
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* a single page-sized chunk.
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*
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* Finally, we use NOP work requests to pad the end of the
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* work queue, to avoid wrap-around in the middle of WR. We
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* set NEC bit to avoid getting completions with error for
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* these NOP WRs, but since NEC is only supported starting
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* with firmware 2.2.232, we use constant-sized WRs for older
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* firmware.
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*
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* And, since MLX QPs only support SEND, we use constant-sized
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* WRs in this case.
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*
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* We look for the smallest value of wqe_shift such that the
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* resulting number of wqes does not exceed device
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* capabilities.
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*
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* We set WQE size to at least 64 bytes, this way stamping
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* invalidates each WQE.
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*/
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qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + 1;
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qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr + qp->sq_spare_wqes);
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if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
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qp->sq_signal_bits && BITS_PER_LONG == 64 &&
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type != IB_QPT_SMI && type != IB_QPT_GSI)
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qp->sq.wqe_shift = ilog2(64);
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else
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qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
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for (;;) {
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if (1 << qp->sq.wqe_shift > dev->dev->caps.max_sq_desc_sz)
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return -EINVAL;
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qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
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/*
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* We need to leave 2 KB + 1 WR of headroom in the SQ to
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* allow HW to prefetch.
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*/
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qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
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qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
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qp->sq_max_wqes_per_wr +
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qp->sq_spare_wqes);
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if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
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break;
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if (qp->sq_max_wqes_per_wr <= 1)
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return -EINVAL;
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++qp->sq.wqe_shift;
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}
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qp->sq.max_gs = ((qp->sq_max_wqes_per_wr << qp->sq.wqe_shift) -
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send_wqe_overhead(type)) / sizeof (struct mlx4_wqe_data_seg);
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qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
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(qp->sq.wqe_cnt << qp->sq.wqe_shift);
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@ -277,7 +406,8 @@ static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
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qp->sq.offset = 0;
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}
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cap->max_send_wr = qp->sq.max_post = qp->sq.wqe_cnt - qp->sq_spare_wqes;
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cap->max_send_wr = qp->sq.max_post =
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(qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
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cap->max_send_sge = qp->sq.max_gs;
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/* We don't support inline sends for kernel QPs (yet) */
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cap->max_inline_data = 0;
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@ -323,6 +453,12 @@ static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
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qp->rq.tail = 0;
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qp->sq.head = 0;
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qp->sq.tail = 0;
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qp->sq_next_wqe = 0;
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if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
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qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
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else
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qp->sq_signal_bits = 0;
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err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
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if (err)
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@ -413,11 +549,6 @@ static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
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*/
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qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
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if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
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qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
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else
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qp->sq_signal_bits = 0;
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qp->mqp.event = mlx4_ib_qp_event;
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return 0;
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@ -912,7 +1043,7 @@ static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
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ctrl = get_send_wqe(qp, i);
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ctrl->owner_opcode = cpu_to_be32(1 << 31);
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stamp_send_wqe(qp, i);
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stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
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}
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}
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@ -965,6 +1096,7 @@ static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
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qp->rq.tail = 0;
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qp->sq.head = 0;
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qp->sq.tail = 0;
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qp->sq_next_wqe = 0;
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if (!ibqp->srq)
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*qp->db.db = 0;
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}
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@ -1274,13 +1406,14 @@ int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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unsigned long flags;
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int nreq;
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int err = 0;
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int ind;
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int size;
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unsigned ind;
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int uninitialized_var(stamp);
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int uninitialized_var(size);
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int i;
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spin_lock_irqsave(&qp->sq.lock, flags);
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ind = qp->sq.head;
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ind = qp->sq_next_wqe;
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for (nreq = 0; wr; ++nreq, wr = wr->next) {
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if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
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@ -1296,7 +1429,7 @@ int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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}
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ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
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qp->sq.wrid[ind & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
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qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
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ctrl->srcrb_flags =
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(wr->send_flags & IB_SEND_SIGNALED ?
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@ -1409,16 +1542,23 @@ int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
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(ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
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stamp = ind + qp->sq_spare_wqes;
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ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
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/*
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* We can improve latency by not stamping the last
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* send queue WQE until after ringing the doorbell, so
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* only stamp here if there are still more WQEs to post.
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*
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* Same optimization applies to padding with NOP wqe
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* in case of WQE shrinking (used to prevent wrap-around
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* in the middle of WR).
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*/
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if (wr->next)
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stamp_send_wqe(qp, (ind + qp->sq_spare_wqes) &
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(qp->sq.wqe_cnt - 1));
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if (wr->next) {
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stamp_send_wqe(qp, stamp, size * 16);
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ind = pad_wraparound(qp, ind);
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}
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++ind;
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}
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out:
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@ -1440,8 +1580,10 @@ out:
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*/
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mmiowb();
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stamp_send_wqe(qp, (ind + qp->sq_spare_wqes - 1) &
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(qp->sq.wqe_cnt - 1));
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stamp_send_wqe(qp, stamp, size * 16);
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ind = pad_wraparound(qp, ind);
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qp->sq_next_wqe = ind;
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}
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spin_unlock_irqrestore(&qp->sq.lock, flags);
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@ -133,6 +133,11 @@ enum {
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MLX4_STAT_RATE_OFFSET = 5
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};
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static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
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{
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return (major << 32) | (minor << 16) | subminor;
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}
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struct mlx4_caps {
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u64 fw_ver;
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int num_ports;
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@ -154,7 +154,11 @@ struct mlx4_qp_context {
|
||||
u32 reserved5[10];
|
||||
};
|
||||
|
||||
/* Which firmware version adds support for NEC (NoErrorCompletion) bit */
|
||||
#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
|
||||
|
||||
enum {
|
||||
MLX4_WQE_CTRL_NEC = 1 << 29,
|
||||
MLX4_WQE_CTRL_FENCE = 1 << 6,
|
||||
MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
|
||||
MLX4_WQE_CTRL_SOLICITED = 1 << 1,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user