leandrof/linux
1
0
Fork 0
forked from Minki/linux
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ARM: SoC cleanups for v4.6

Browse Source 
A few simple cleanups across multiple platforms, not much standing out:
 
 - lpc32xx removes its private implementation of the clk API, after
   generic code was merged in 4.5
 - all unused Makefile.boot files get removed
 - a number of simplifications for shmobile
 - asm/clkdev.h gets replaced with the asm-generic version after
   all mach/clkdev.h implementations are gone
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIVAwUAVu67NGCrR//JCVInAQJoQw/+Mvbsb57ueA6Ao7l4/UpsNayKIuYZlrrQ
 afa6KMYzqPuQ9hWYAFMNM9amIHMX8aqoZTL29soezLYlcpGxeN49AJ1bXX+Qci8r
 DAiU2Z6SX3qXo396Fg8VTDNSfn3SvEPnp6X2GcaxrB349jeGJqFeABEnPcVkBBtE
 18wxO1AbtsbOpwaGDCnndJOc0vYuRfkUAW0+3379jI7IGrZzq38sTGdmFmZ0HYCv
 DWFkUU/DPKVPnRIkZUCljUQXYYYiuvpZUXyZZPRUT/k6ujXmtjZJij9CAJkm9f0e
 dyv3aYIlp8+jSdWoT+58eSAsihyGPEwfgDE3xYxKm2ENxGgS1HQJYNDAm/j3Kj4J
 iX98bdBxKzZsHb64jNOeOVxs0xVvHSolo0oFM9sSIMgZ2hQZScXAj24Wd1sHyF0Y
 K+ru5g7oHQoaHLsyRn8buN8F+0ATv1A8Wecy6avAYvKYHhMV7WrgbiJlRGmS3PUH
 8XiTNsQbiUJIvFafj38yStpPLc8jpf8LcAdql0T+JyMCd8+Ee+bpaswvJysmWKg7
 12G7xaUyLhUP5DZn3mMM8UyI1/yoUk63igsT7eUsGLfLzSL25X1ATh24Cb8Gwf4f
 +HIv21zbUbgRrN3u+N2QRU46BESlfSp68Gjrth3p+1nvHISZpnEJ9ujcpRtCY7Ik
 uBSxUT21VN8=
 =ZTl9
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Arnd Bergmann:
 "A few simple cleanups across multiple platforms, not much standing
  out:

   - lpc32xx removes its private implementation of the clk API, after
     generic code was merged in 4.5
   - all unused Makefile.boot files get removed
   - a number of simplifications for shmobile
   - asm/clkdev.h gets replaced with the asm-generic version after all
     mach/clkdev.h implementations are gone"

* tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: shmobile: Kconfig: Get rid of old comment
  ARM: shmobile: Consolidate SCU mapping code
  arm: lpc32xx: remove direct control of GPIOs from shared mach file
  arm: lpc32xx: remove selected HAVE_IDE
  arm: lpc32xx: switch to common clock framework
  ARM: Use generic clkdev.h header
  ARM: plat-versatile: Remove unused clock.c file
  ARM: netx: remove redundant "depends on ARCH_NETX"
  ARM: integrator: remove redundant select in Kconfig
  ARM: drop unused Makefile.boot of Multiplatform SoCs
  ARM: mvebu: add missing of_node_put()
  ARM: shmobile: r8a7779: Remove remainings of removed SCU boot setup code
  ARM: shmobile: Typo s/MIPDR/MPIDR/
  ARM: shmobile: Add includes providing forward declarations
  ARM: shmobile: rcar-gen2: Make rcar_gen2_dma_contiguous static
  ARM: mv78xx0: use "depends on" instead of "if" after prompt
This commit is contained in:
Linus Torvalds 2016-03-20 14:37:22 -07:00
commit e88fa1b8b0
42 changed files with 30 additions and 1672 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/Kconfig
View File

@ -527,10 +527,10 @@ config ARCH_LPC32XX
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_LPC32XX
select COMMON_CLK
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select HAVE_IDE
select USE_OF
help
Support for the NXP LPC32XX family of processors

1
arch/arm/include/asm/Kbuild
View File

@ -1,6 +1,7 @@
generic-y += bitsperlong.h
generic-y += clkdev.h
generic-y += cputime.h
generic-y += current.h
generic-y += early_ioremap.h

31
arch/arm/include/asm/clkdev.h
View File

@ -1,31 +0,0 @@
/*
* arch/arm/include/asm/clkdev.h
*
* Copyright (C) 2008 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Helper for the clk API to assist looking up a struct clk.
*/
#ifndef __ASM_CLKDEV_H
#define __ASM_CLKDEV_H
#include <linux/slab.h>
#ifndef CONFIG_COMMON_CLK
#ifdef CONFIG_HAVE_MACH_CLKDEV
#include <mach/clkdev.h>
#else
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif
#endif
static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
{
return kzalloc(size, GFP_KERNEL);
}
#endif

3
arch/arm/mach-cns3xxx/Makefile.boot
View File

@ -1,3 +0,0 @@
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00C00000

2
arch/arm/mach-exynos/Makefile.boot
View File

@ -1,2 +0,0 @@
zreladdr-y += 0x40008000
params_phys-y := 0x40000100

6
arch/arm/mach-integrator/Kconfig
View File

@ -2,22 +2,16 @@ menuconfig ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"
depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V6
select ARM_AMBA
select ARM_PATCH_PHYS_VIRT if MMU
select AUTO_ZRELADDR
select COMMON_CLK
select COMMON_CLK_VERSATILE
select GENERIC_CLOCKEVENTS
select HAVE_TCM
select ICST
select MFD_SYSCON
select MULTI_IRQ_HANDLER
select PLAT_VERSATILE
select POWER_RESET
select POWER_RESET_VERSATILE
select POWER_SUPPLY
select SOC_INTEGRATOR_CM
select SPARSE_IRQ
select USE_OF
select VERSATILE_FPGA_IRQ
help
Support for ARM's Integrator platform.

4
arch/arm/mach-integrator/Makefile.boot
View File

@ -1,4 +0,0 @@
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

1
arch/arm/mach-keystone/Makefile.boot
View File

@ -1 +0,0 @@
zreladdr-y := 0x80008000

3
arch/arm/mach-lpc32xx/Makefile
View File

@ -2,7 +2,6 @@
# Makefile for the linux kernel.
#
obj-y := timer.o irq.o common.o serial.o clock.o
obj-y := irq.o common.o serial.o
obj-y += pm.o suspend.o
obj-y += phy3250.o

1284
arch/arm/mach-lpc32xx/clock.c
View File

File diff suppressed because it is too large Load Diff

53
arch/arm/mach-lpc32xx/phy3250.c
View File

@ -36,7 +36,6 @@
#include <linux/clk.h>
#include <linux/mtd/lpc32xx_slc.h>
#include <linux/mtd/lpc32xx_mlc.h>
#include <linux/platform_data/gpio-lpc32xx.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
@ -47,13 +46,6 @@
#include <mach/board.h>
#include "common.h"
/*
* Mapped GPIOLIB GPIOs
*/
#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
#define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
/*
* AMBA LCD controller
*/
@ -97,20 +89,6 @@ static int lpc32xx_clcd_setup(struct clcd_fb *fb)
fb->fb.fix.smem_len = PANEL_SIZE;
fb->panel = &conn_lcd_panel;
if (gpio_request(LCD_POWER_GPIO, "LCD power"))
printk(KERN_ERR "Error requesting gpio %u",
LCD_POWER_GPIO);
else if (gpio_direction_output(LCD_POWER_GPIO, 1))
printk(KERN_ERR "Error setting gpio %u to output",
LCD_POWER_GPIO);
if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
printk(KERN_ERR "Error requesting gpio %u",
BKL_POWER_GPIO);
else if (gpio_direction_output(BKL_POWER_GPIO, 1))
printk(KERN_ERR "Error setting gpio %u to output",
BKL_POWER_GPIO);
return 0;
}
@ -126,29 +104,10 @@ static void lpc32xx_clcd_remove(struct clcd_fb *fb)
fb->fb.fix.smem_start);
}
/*
* On some early LCD modules (1307.0), the backlight logic is inverted.
* For those board variants, swap the disable and enable states for
* BKL_POWER_GPIO.
*/
static void clcd_disable(struct clcd_fb *fb)
{
gpio_set_value(BKL_POWER_GPIO, 0);
gpio_set_value(LCD_POWER_GPIO, 0);
}
static void clcd_enable(struct clcd_fb *fb)
{
gpio_set_value(BKL_POWER_GPIO, 1);
gpio_set_value(LCD_POWER_GPIO, 1);
}
static struct clcd_board lpc32xx_clcd_data = {
.name = "Phytec LCD",
.check = clcdfb_check,
.decode = clcdfb_decode,
.disable = clcd_disable,
.enable = clcd_enable,
.setup = lpc32xx_clcd_setup,
.mmap = lpc32xx_clcd_mmap,
.remove = lpc32xx_clcd_remove,
@ -187,20 +146,9 @@ static struct pl08x_platform_data pl08x_pd = {
.mem_buses = PL08X_AHB1,
};
static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios)
{
/* Only on and off are supported */
if (ios->power_mode == MMC_POWER_OFF)
gpio_set_value(MMC_PWR_ENABLE_GPIO, 0);
else
gpio_set_value(MMC_PWR_ENABLE_GPIO, 1);
return 0;
}
static struct mmci_platform_data lpc32xx_mmci_data = {
.ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 |
MMC_VDD_32_33 | MMC_VDD_33_34,
.ios_handler = mmc_handle_ios,
};
static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
@ -259,7 +207,6 @@ DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
.atag_offset = 0x100,
.map_io = lpc32xx_map_io,
.init_irq = lpc32xx_init_irq,
.init_time = lpc32xx_timer_init,
.init_machine = lpc3250_machine_init,
.dt_compat = lpc32xx_dt_compat,
MACHINE_END

3
arch/arm/mach-lpc32xx/serial.c
View File

@ -76,9 +76,6 @@ void __init lpc32xx_serial_init(void)
unsigned int puart;
int i, j;
/* UART clocks are off, let clock driver manage them */
__raw_writel(0, LPC32XX_CLKPWR_UART_CLK_CTRL);
for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
if (!IS_ERR(clk)) {

144
arch/arm/mach-lpc32xx/timer.c
View File

@ -1,144 +0,0 @@
/*
* arch/arm/mach-lpc32xx/timer.c
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2009 - 2010 NXP Semiconductors
* Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven
* Ed Schouten <e.schouten@fontys.nl>
* Laurens Timmermans <l.timmermans@fontys.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/time.h>
#include <linux/err.h>
#include <linux/clockchips.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/platform.h>
#include "common.h"
static int lpc32xx_clkevt_next_event(unsigned long delta,
struct clock_event_device *dev)
{
__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
return 0;
}
static int lpc32xx_shutdown(struct clock_event_device *evt)
{
/*
* Disable the timer. When using oneshot, we must also
* disable the timer to wait for the first call to
* set_next_event().
*/
__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
return 0;
}
static struct clock_event_device lpc32xx_clkevt = {
.name = "lpc32xx_clkevt",
.features = CLOCK_EVT_FEAT_ONESHOT,
.rating = 300,
.set_next_event = lpc32xx_clkevt_next_event,
.set_state_shutdown = lpc32xx_shutdown,
.set_state_oneshot = lpc32xx_shutdown,
};
static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = &lpc32xx_clkevt;
/* Clear match */
__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction lpc32xx_timer_irq = {
.name = "LPC32XX Timer Tick",
.flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = lpc32xx_timer_interrupt,
};
/*
* The clock management driver isn't initialized at this point, so the
* clocks need to be enabled here manually and then tagged as used in
* the clock driver initialization
*/
void __init lpc32xx_timer_init(void)
{
u32 clkrate, pllreg;
/* Enable timer clock */
__raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN |
LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1);
/*
* The clock driver isn't initialized at this point. So determine if
* the SYSCLK is driven from the PLL397 or main oscillator and then use
* it to compute the PLL frequency and the PCLK divider to get the base
* timer rates. This rate is needed to compute the tick rate.
*/
if (clk_is_sysclk_mainosc() != 0)
clkrate = LPC32XX_MAIN_OSC_FREQ;
else
clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
/* Get ARM HCLKPLL register and convert it into a frequency */
pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
clkrate = clk_get_pllrate_from_reg(clkrate, pllreg);
/* Get PCLK divider and divide ARM PLL clock by it to get timer rate */
clkrate = clkrate / clk_get_pclk_div();
/* Initial timer setup */
__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
__raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) |
LPC32XX_TIMER_CNTR_MCR_STOP(0) |
LPC32XX_TIMER_CNTR_MCR_RESET(0),
LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
/* Setup tick interrupt */
setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
/* Setup the clockevent structure. */
lpc32xx_clkevt.cpumask = cpumask_of(0);
clockevents_config_and_register(&lpc32xx_clkevt, clkrate, 1, -1);
/* Use timer1 as clock source. */
__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
__raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
__raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
"lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
}

1
arch/arm/mach-mmp/Makefile.boot
View File

@ -1 +0,0 @@
zreladdr-y += 0x00008000

3
arch/arm/mach-mv78xx0/Kconfig
View File

@ -1,5 +1,6 @@
menuconfig ARCH_MV78XX0
bool "Marvell MV78xx0" if ARCH_MULTI_V5
bool "Marvell MV78xx0"
depends on ARCH_MULTI_V5
select ARCH_REQUIRE_GPIOLIB
select CPU_FEROCEON
select MVEBU_MBUS

3
arch/arm/mach-mv78xx0/Makefile.boot
View File

@ -1,3 +0,0 @@
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

1
arch/arm/mach-mvebu/platsmp.c
View File

@ -140,6 +140,7 @@ static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
panic("Cannot find 'marvell,bootrom' compatible node");
err = of_address_to_resource(node, 0, &res);
of_node_put(node);
if (err < 0)
panic("Cannot get 'bootrom' node address");

3
arch/arm/mach-netx/Kconfig
View File

@ -3,20 +3,17 @@ menu "NetX Implementations"
config MACH_NXDKN
bool "Enable Hilscher nxdkn Eval Board support"
depends on ARCH_NETX
help
Board support for the Hilscher NetX Eval Board
config MACH_NXDB500
bool "Enable Hilscher nxdb500 Eval Board support"
depends on ARCH_NETX
select ARM_AMBA
help
Board support for the Hilscher nxdb500 Eval Board
config MACH_NXEB500HMI
bool "Enable Hilscher nxeb500hmi Eval Board support"
depends on ARCH_NETX
select ARM_AMBA
help
Board support for the Hilscher nxeb500hmi Eval Board

0
arch/arm/mach-nspire/Makefile.boot
View File

3
arch/arm/mach-omap2/Makefile.boot
View File

@ -1,3 +0,0 @@
zreladdr-y += 0x80008000
params_phys-y := 0x80000100
initrd_phys-y := 0x80800000

3
arch/arm/mach-orion5x/Makefile.boot
View File

@ -1,3 +0,0 @@
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

3
arch/arm/mach-prima2/Makefile.boot
View File

@ -1,3 +0,0 @@
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

9
arch/arm/mach-realview/Makefile.boot
View File

@ -1,9 +0,0 @@
ifeq ($(CONFIG_REALVIEW_HIGH_PHYS_OFFSET),y)
zreladdr-y += 0x70008000
params_phys-y := 0x70000100
initrd_phys-y := 0x70800000
else
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000
endif

2
arch/arm/mach-s3c64xx/Makefile.boot
View File

@ -1,2 +0,0 @@
zreladdr-y += 0x50008000
params_phys-y := 0x50000100

2
arch/arm/mach-shmobile/Kconfig
View File

@ -99,6 +99,4 @@ config ARCH_SH73A0
bool "SH-Mobile AG5 (R8A73A00)"
select ARCH_RMOBILE
select RENESAS_INTC_IRQPIN
comment "Renesas ARM SoCs System Configuration"
endif

5
arch/arm/mach-shmobile/common.h
View File

@ -11,7 +11,8 @@ extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
unsigned long arg);
extern bool shmobile_smp_cpu_can_disable(unsigned int cpu);
extern void shmobile_boot_scu(void);
extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
extern void shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys,
unsigned int max_cpus);
extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
extern int shmobile_smp_scu_cpu_kill(unsigned int cpu);
extern struct platform_suspend_ops shmobile_suspend_ops;
@ -30,8 +31,6 @@ int shmobile_cpufreq_init(void);
static inline int shmobile_cpufreq_init(void) { return 0; }
#endif
extern void __iomem *shmobile_scu_base;
static inline void __init shmobile_init_late(void)
{
shmobile_suspend_init();

2
arch/arm/mach-shmobile/cpufreq.c
View File

@ -10,6 +10,8 @@
#include <linux/platform_device.h>
#include "common.h"
int __init shmobile_cpufreq_init(void)
{
platform_device_register_simple("cpufreq-dt", -1, NULL, 0);

2
arch/arm/mach-shmobile/headsmp-scu.S
View File

@ -27,7 +27,7 @@
*/
ENTRY(shmobile_boot_scu)
@ r0 = SCU base address
mrc p15, 0, r1, c0, c0, 5 @ read MIPDR
mrc p15, 0, r1, c0, c0, 5 @ read MPIDR
and r1, r1, #3 @ mask out cpu ID
lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
ldr r2, [r0, #8] @ SCU Power Status Register

10
arch/arm/mach-shmobile/platsmp-scu.c
View File

@ -18,7 +18,8 @@
#include "common.h"
void __iomem *shmobile_scu_base;
static phys_addr_t shmobile_scu_base_phys;
static void __iomem *shmobile_scu_base;
static int shmobile_smp_scu_notifier_call(struct notifier_block *nfb,
unsigned long action, void *hcpu)
@ -29,7 +30,7 @@ static int shmobile_smp_scu_notifier_call(struct notifier_block *nfb,
case CPU_UP_PREPARE:
/* For this particular CPU register SCU SMP boot vector */
shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu),
(unsigned long)shmobile_scu_base);
shmobile_scu_base_phys);
break;
};
@ -40,12 +41,15 @@ static struct notifier_block shmobile_smp_scu_notifier = {
.notifier_call = shmobile_smp_scu_notifier_call,
};
void __init shmobile_smp_scu_prepare_cpus(unsigned int max_cpus)
void __init shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys,
unsigned int max_cpus)
{
/* install boot code shared by all CPUs */
shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
/* enable SCU and cache coherency on booting CPU */
shmobile_scu_base_phys = scu_base_phys;
shmobile_scu_base = ioremap(scu_base_phys, PAGE_SIZE);
scu_enable(shmobile_scu_base);
scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);

7
arch/arm/mach-shmobile/setup-rcar-gen2.c
View File

@ -182,8 +182,6 @@ static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname,
return 0;
}
struct cma *rcar_gen2_dma_contiguous;
void __init rcar_gen2_reserve(void)
{
struct memory_reserve_config mrc;
@ -194,8 +192,11 @@ void __init rcar_gen2_reserve(void)
of_scan_flat_dt(rcar_gen2_scan_mem, &mrc);
#ifdef CONFIG_DMA_CMA
if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size))
if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size)) {
static struct cma *rcar_gen2_dma_contiguous;
dma_contiguous_reserve_area(mrc.size, mrc.base, 0,
&rcar_gen2_dma_contiguous, true);
}
#endif
}

3
arch/arm/mach-shmobile/smp-emev2.c
View File

@ -45,8 +45,7 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
}
/* setup EMEV2 specific SCU bits */
shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
shmobile_smp_scu_prepare_cpus(max_cpus);
shmobile_smp_scu_prepare_cpus(EMEV2_SCU_BASE, max_cpus);
}
const struct smp_operations emev2_smp_ops __initconst = {

3
arch/arm/mach-shmobile/smp-r8a7779.c
View File

@ -94,8 +94,7 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
__raw_writel(__pa(shmobile_boot_vector), AVECR);
/* setup r8a7779 specific SCU bits */
shmobile_scu_base = IOMEM(R8A7779_SCU_BASE);
shmobile_smp_scu_prepare_cpus(max_cpus);
shmobile_smp_scu_prepare_cpus(R8A7779_SCU_BASE, max_cpus);
r8a7779_pm_init();

3
arch/arm/mach-shmobile/smp-sh73a0.c
View File

@ -52,8 +52,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
__raw_writel(__pa(shmobile_boot_vector), SBAR);
/* setup sh73a0 specific SCU bits */
shmobile_scu_base = IOMEM(SH73A0_SCU_BASE);
shmobile_smp_scu_prepare_cpus(max_cpus);
shmobile_smp_scu_prepare_cpus(SH73A0_SCU_BASE, max_cpus);
}
const struct smp_operations sh73a0_smp_ops __initconst = {

2
arch/arm/mach-shmobile/suspend.c
View File

@ -17,6 +17,8 @@
#include <asm/io.h>
#include <asm/system_misc.h>
#include "common.h"
static int shmobile_suspend_default_enter(suspend_state_t suspend_state)
{
cpu_do_idle();

2
arch/arm/mach-shmobile/timer.c
View File

@ -18,6 +18,8 @@
#include <linux/delay.h>
#include <linux/of_address.h>
#include "common.h"
static void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
unsigned int mult, unsigned int div)
{

3
arch/arm/mach-spear/Makefile.boot
View File

@ -1,3 +0,0 @@
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

4
arch/arm/mach-u300/Makefile.boot
View File

@ -1,4 +0,0 @@
zreladdr-y += 0x48008000
params_phys-y := 0x48000100
# This isn't used.
#initrd_phys-y := 0x48800000

3
arch/arm/mach-ux500/Makefile.boot
View File

@ -1,3 +0,0 @@
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

3
arch/arm/mach-zynq/Makefile.boot
View File

@ -1,3 +0,0 @@
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

3
arch/arm/plat-versatile/Kconfig
View File

@ -1,8 +1,5 @@
if PLAT_VERSATILE
config PLAT_VERSATILE_CLOCK
bool
config PLAT_VERSATILE_SCHED_CLOCK
bool

1
arch/arm/plat-versatile/Makefile
View File

@ -1,5 +1,4 @@
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o
obj-$(CONFIG_SMP) += headsmp.o platsmp.o

74
arch/arm/plat-versatile/clock.c
View File

@ -1,74 +0,0 @@
/*
* linux/arch/arm/plat-versatile/clock.c
*
* Copyright (C) 2004 ARM Limited.
* Written by Deep Blue Solutions Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/mutex.h>
#include <asm/hardware/icst.h>
#include <mach/clkdev.h>
int clk_enable(struct clk *clk)
{
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);
long clk_round_rate(struct clk *clk, unsigned long rate)
{
long ret = -EIO;
if (clk->ops && clk->ops->round)
ret = clk->ops->round(clk, rate);
return ret;
}
EXPORT_SYMBOL(clk_round_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
int ret = -EIO;
if (clk->ops && clk->ops->set)
ret = clk->ops->set(clk, rate);
return ret;
}
EXPORT_SYMBOL(clk_set_rate);
long icst_clk_round(struct clk *clk, unsigned long rate)
{
struct icst_vco vco;
vco = icst_hz_to_vco(clk->params, rate);
return icst_hz(clk->params, vco);
}
EXPORT_SYMBOL(icst_clk_round);
int icst_clk_set(struct clk *clk, unsigned long rate)
{
struct icst_vco vco;
vco = icst_hz_to_vco(clk->params, rate);
clk->rate = icst_hz(clk->params, vco);
clk->ops->setvco(clk, vco);
return 0;
}
EXPORT_SYMBOL(icst_clk_set);