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ixgbe: Enable support for recognizing PCI-e Gen3 link speed

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This patch adds support for displaying PCIe Gen3 link speed, which was
previously missing from the driver.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Jacob Keller 2013-02-15 09:18:10 +00:00 committed by Jeff Kirsher
parent 7f66162b62
commit e8710a5fbf
3 changed files with 7 additions and 1 deletions
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3
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
View File

@ -635,6 +635,9 @@ s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
case IXGBE_PCI_LINK_SPEED_5000:
hw->bus.speed = ixgbe_bus_speed_5000;
break;
case IXGBE_PCI_LINK_SPEED_8000:
hw->bus.speed = ixgbe_bus_speed_8000;
break;
default:
hw->bus.speed = ixgbe_bus_speed_unknown;
break;

3
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
View File

@ -7490,7 +7490,8 @@ skip_sriov:
/* print bus type/speed/width info */
e_dev_info("(PCI Express:%s:%s) %pM\n",
(hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
(hw->bus.speed == ixgbe_bus_speed_8000 ? "8.0GT/s" :
hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
"Unknown"),
(hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :

2
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
View File

@ -1827,6 +1827,7 @@ enum {
#define IXGBE_PCI_LINK_SPEED 0xF
#define IXGBE_PCI_LINK_SPEED_2500 0x1
#define IXGBE_PCI_LINK_SPEED_5000 0x2
#define IXGBE_PCI_LINK_SPEED_8000 0x3
#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
@ -2650,6 +2651,7 @@ enum ixgbe_bus_speed {
ixgbe_bus_speed_133 = 133,
ixgbe_bus_speed_2500 = 2500,
ixgbe_bus_speed_5000 = 5000,
ixgbe_bus_speed_8000 = 8000,
ixgbe_bus_speed_reserved
};