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drm/i915/display: Rename pipe_timings to transcoder_timings

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No functional changes in this patch.

With Bigjoiner, there are 2 pipes driving 2 halfs of 1
transcoder. The transcoder_mode has the full timings, and is used
for configuring the transcoder with the intended mode after
joining the 2 halves.
To clear the confusion, we rename intel_set_pipe_timings to
intel_set_transcoder_timings

v2:
* Split the renaming into separate patch (Ville)

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201008214535.22942-2-manasi.d.navare@intel.com
This commit is contained in:
Manasi Navare
2020-10-08 14:45:26 -07:00
parent 605f9c290c
commit e7fc3f902d
1 changed files with 11 additions and 11 deletions
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20
drivers/gpu/drm/i915/display/intel_display.c
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@@ -154,7 +154,7 @@ static void ilk_pch_clock_get(struct intel_crtc *crtc,
static int intel_framebuffer_init(struct intel_framebuffer *ifb, static int intel_framebuffer_init(struct intel_framebuffer *ifb,
struct drm_i915_gem_object *obj, struct drm_i915_gem_object *obj,
struct drm_mode_fb_cmd2 *mode_cmd); struct drm_mode_fb_cmd2 *mode_cmd);
static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state); static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
const struct intel_link_m_n *m_n, const struct intel_link_m_n *m_n,
@@ -7004,7 +7004,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
if (intel_crtc_has_dp_encoder(new_crtc_state)) if (intel_crtc_has_dp_encoder(new_crtc_state))
intel_dp_set_m_n(new_crtc_state, M1_N1); intel_dp_set_m_n(new_crtc_state, M1_N1);
intel_set_pipe_timings(new_crtc_state); intel_set_transcoder_timings(new_crtc_state);
intel_set_pipe_src_size(new_crtc_state); intel_set_pipe_src_size(new_crtc_state);
if (new_crtc_state->has_pch_encoder) if (new_crtc_state->has_pch_encoder)
@@ -7149,7 +7149,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
intel_encoders_pre_enable(state, crtc); intel_encoders_pre_enable(state, crtc);
if (!transcoder_is_dsi(cpu_transcoder)) if (!transcoder_is_dsi(cpu_transcoder))
intel_set_pipe_timings(new_crtc_state); intel_set_transcoder_timings(new_crtc_state);
intel_set_pipe_src_size(new_crtc_state); intel_set_pipe_src_size(new_crtc_state);
@@ -7544,7 +7544,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
if (intel_crtc_has_dp_encoder(new_crtc_state)) if (intel_crtc_has_dp_encoder(new_crtc_state))
intel_dp_set_m_n(new_crtc_state, M1_N1); intel_dp_set_m_n(new_crtc_state, M1_N1);
intel_set_pipe_timings(new_crtc_state); intel_set_transcoder_timings(new_crtc_state);
intel_set_pipe_src_size(new_crtc_state); intel_set_pipe_src_size(new_crtc_state);
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
@@ -7612,7 +7612,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
if (intel_crtc_has_dp_encoder(new_crtc_state)) if (intel_crtc_has_dp_encoder(new_crtc_state))
intel_dp_set_m_n(new_crtc_state, M1_N1); intel_dp_set_m_n(new_crtc_state, M1_N1);
intel_set_pipe_timings(new_crtc_state); intel_set_transcoder_timings(new_crtc_state);
intel_set_pipe_src_size(new_crtc_state); intel_set_pipe_src_size(new_crtc_state);
i9xx_set_pipeconf(new_crtc_state); i9xx_set_pipeconf(new_crtc_state);
@@ -8866,7 +8866,7 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
crtc_state->dpll_hw_state.dpll = dpll; crtc_state->dpll_hw_state.dpll = dpll;
} }
static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state) static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
{ {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -8952,7 +8952,7 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
} }
static void intel_get_pipe_timings(struct intel_crtc *crtc, static void intel_get_transcoder_timings(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config) struct intel_crtc_state *pipe_config)
{ {
struct drm_device *dev = crtc->base.dev; struct drm_device *dev = crtc->base.dev;
@@ -9576,7 +9576,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
if (INTEL_GEN(dev_priv) < 4) if (INTEL_GEN(dev_priv) < 4)
pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
intel_get_pipe_timings(crtc, pipe_config); intel_get_transcoder_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config); intel_get_pipe_src_size(crtc, pipe_config);
i9xx_get_pfit_config(pipe_config); i9xx_get_pfit_config(pipe_config);
@@ -10857,7 +10857,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
pipe_config->pixel_multiplier = 1; pipe_config->pixel_multiplier = 1;
} }
intel_get_pipe_timings(crtc, pipe_config); intel_get_transcoder_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config); intel_get_pipe_src_size(crtc, pipe_config);
ilk_get_pfit_config(pipe_config); ilk_get_pfit_config(pipe_config);
@@ -11274,7 +11274,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
INTEL_GEN(dev_priv) >= 11) { INTEL_GEN(dev_priv) >= 11) {
hsw_get_ddi_port_state(crtc, pipe_config); hsw_get_ddi_port_state(crtc, pipe_config);
intel_get_pipe_timings(crtc, pipe_config); intel_get_transcoder_timings(crtc, pipe_config);
} }
intel_get_pipe_src_size(crtc, pipe_config); intel_get_pipe_src_size(crtc, pipe_config);