drm/amdgpu/gmc8: SRIOV need to program fb location
SRIOV won't do vbios post in guest OS, and the mmMC_VM_FB_LOCATION is pf and vf copy, so still need to program fb location for SRIOV. v2: No need to stop mc, and update gmc_v8_0_vram_gtt_location as well. v3: New line after the stack variables BUG: SWDEV-126629 Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -396,7 +396,10 @@ static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
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static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
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struct amdgpu_mc *mc)
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{
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u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
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u64 base = 0;
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if (!amdgpu_sriov_vf(adev))
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base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
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base <<= 24;
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if (mc->mc_vram_size > 0xFFC0000000ULL) {
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@ -442,6 +445,17 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
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adev->mc.vram_end >> 12);
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WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
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adev->vram_scratch.gpu_addr >> 12);
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if (amdgpu_sriov_vf(adev)) {
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tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
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tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
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WREG32(mmMC_VM_FB_LOCATION, tmp);
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/* XXX double check these! */
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WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
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WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
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WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
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}
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WREG32(mmMC_VM_AGP_BASE, 0);
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WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
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WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
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