dt-bindings: serial: Convert 8250 to json-schema
Some fixes were done during the conversion: Slightly better examples. The original example was for an OMAP serial port, which is not even described by this binding, but by omap_serial.txt instead. Added compatible strings, that were used, byt not documented: andestech,uart16550, cavium,octeon-3860-uart, fsl,16550-FIFO64, nvidia,tegra186-uart, nvidia,tegra194-uart, nxp,lpc1850-uart, opencores,uart16550-rtlsvn105, ralink,mt7620a-uart, ralink,rt3052-uart, ralink,rt3883-uart and xlnx,xps-uart16550-2.00.b. Removed "serial" compatible string. It's redundant with the node name (which, in OFW, serves the same purpose as the compatible string). Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> [robh: allow additional properties. clocks/clock-frequency can be optional on original 8250 series with standard clocks] Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Lubomir Rintel
Rob Herring
parent
e5651e8398
commit
e69f5dc623
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* UART (Universal Asynchronous Receiver/Transmitter)
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Required properties:
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- compatible : one of:
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- "ns8250"
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- "ns16450"
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- "ns16550a"
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- "ns16550"
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- "ns16750"
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- "ns16850"
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- For Tegra20, must contain "nvidia,tegra20-uart"
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- For other Tegra, must contain '"nvidia,<chip>-uart",
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"nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
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tegra132, or tegra210.
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- "nxp,lpc3220-uart"
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- "ralink,rt2880-uart"
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- For MediaTek BTIF, must contain '"mediatek,<chip>-btif",
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"mediatek,mtk-btif"' where <chip> is mt7622, mt7623.
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- "altr,16550-FIFO32"
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- "altr,16550-FIFO64"
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- "altr,16550-FIFO128"
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- "fsl,16550-FIFO64"
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- "fsl,ns16550"
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- "intel,xscale-uart"
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- "ti,da830-uart"
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- "aspeed,ast2400-vuart"
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- "aspeed,ast2500-vuart"
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- "nuvoton,npcm750-uart"
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- "mrvl,mmp-uart"
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- "mrvl,pxa-uart"
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- "serial" if the port type is unknown.
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- reg : offset and length of the register set for the device.
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- interrupts : should contain uart interrupt.
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- clock-frequency : the input clock frequency for the UART
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or
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clocks phandle to refer to the clk used as per Documentation/devicetree
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/bindings/clock/clock-bindings.txt
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Optional properties:
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- current-speed : the current active speed of the UART.
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- reg-offset : offset to apply to the mapbase from the start of the registers.
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- reg-shift : quantity to shift the register offsets by.
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- reg-io-width : the size (in bytes) of the IO accesses that should be
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performed on the device. There are some systems that require 32-bit
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accesses to the UART (e.g. TI davinci).
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- used-by-rtas : set to indicate that the port is in use by the OpenFirmware
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RTAS and should not be registered.
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- no-loopback-test: set to indicate that the port does not implements loopback
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test mode
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- fifo-size: the fifo size of the UART.
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- auto-flow-control: one way to enable automatic flow control support. The
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driver is allowed to detect support for the capability even without this
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property.
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- tx-threshold: Specify the TX FIFO low water indication for parts with
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programmable TX FIFO thresholds.
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- resets : phandle + reset specifier pairs
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- overrun-throttle-ms : how long to pause uart rx when input overrun is encountered.
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- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
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line respectively. It will use specified GPIO instead of the peripheral
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function pin for the UART feature. If unsure, don't specify this property.
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- aspeed,sirq-polarity-sense: Only applicable to aspeed,ast2500-vuart.
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phandle to aspeed,ast2500-scu compatible syscon alongside register offset
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and bit number to identify how the SIRQ polarity should be configured.
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One possible data source is the LPC/eSPI mode bit.
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Example: aspeed,sirq-polarity-sense = <&syscon 0x70 25>
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Note:
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* fsl,ns16550:
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------------
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Freescale DUART is very similar to the PC16552D (and to a
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pair of NS16550A), albeit with some nonstandard behavior such as
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erratum A-004737 (relating to incorrect BRK handling).
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Represents a single port that is compatible with the DUART found
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on many Freescale chips (examples include mpc8349, mpc8548,
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mpc8641d, p4080 and ls2085a).
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Example:
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uart@80230000 {
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compatible = "ns8250";
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reg = <0x80230000 0x100>;
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clock-frequency = <3686400>;
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interrupts = <10>;
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reg-shift = <2>;
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};
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Example for OMAP UART using GPIO-based modem control signals:
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uart4: serial@49042000 {
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compatible = "ti,omap3-uart";
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reg = <0x49042000 0x400>;
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interrupts = <80>;
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ti,hwmods = "uart4";
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clock-frequency = <48000000>;
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cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
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rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
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dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
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dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
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dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
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rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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};
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233
Documentation/devicetree/bindings/serial/8250.yaml
Normal file
233
Documentation/devicetree/bindings/serial/8250.yaml
Normal file
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# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/serial/8250.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: UART (Universal Asynchronous Receiver/Transmitter) bindings
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maintainers:
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- devicetree@vger.kernel.org
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allOf:
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- $ref: /schemas/serial.yaml#
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- if:
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required:
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- aspeed,sirq-polarity-sense
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then:
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properties:
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compatible:
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const: aspeed,ast2500-vuart
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- if:
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properties:
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compatible:
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const: mrvl,mmp-uart
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then:
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properties:
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reg-shift:
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const: 2
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required:
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- reg-shift
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- if:
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not:
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properties:
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compatible:
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items:
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- enum:
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- ns8250
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- ns16450
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- ns16550
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- ns16550a
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then:
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anyOf:
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- required: [ clock-frequency ]
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- required: [ clocks ]
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properties:
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compatible:
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oneOf:
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- const: ns8250
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- const: ns16450
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- const: ns16550
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- const: ns16550a
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- const: ns16850
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- const: aspeed,ast2400-vuart
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- const: aspeed,ast2500-vuart
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- const: intel,xscale-uart
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- const: mrvl,pxa-uart
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- const: nuvoton,npcm750-uart
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- const: nvidia,tegra20-uart
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- const: nxp,lpc3220-uart
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- items:
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- enum:
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- altr,16550-FIFO32
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- altr,16550-FIFO64
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- altr,16550-FIFO128
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- fsl,16550-FIFO64
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- fsl,ns16550
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- andestech,uart16550
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- nxp,lpc1850-uart
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- opencores,uart16550-rtlsvn105
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- ti,da830-uart
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- const: ns16550a
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- items:
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- enum:
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- ns16750
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- cavium,octeon-3860-uart
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- xlnx,xps-uart16550-2.00.b
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- ralink,rt2880-uart
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- enum:
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- ns16550 # Deprecated, unless the FIFO really is broken
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- ns16550a
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- items:
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- enum:
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- ralink,mt7620a-uart
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- ralink,rt3052-uart
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- ralink,rt3883-uart
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- const: ralink,rt2880-uart
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- enum:
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- ns16550 # Deprecated, unless the FIFO really is broken
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- ns16550a
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- items:
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- enum:
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- mediatek,mt7622-btif
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- mediatek,mt7623-btif
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- const: mediatek,mtk-btif
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- items:
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- enum:
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- mediatek,mt7622-btif
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- mediatek,mt7623-btif
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- const: mediatek,mtk-btif
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- items:
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- const: mrvl,mmp-uart
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- const: intel,xscale-uart
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- items:
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- enum:
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- nvidia,tegra30-uart
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- nvidia,tegra114-uart
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- nvidia,tegra124-uart
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- nvidia,tegra186-uart
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- nvidia,tegra194-uart
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- nvidia,tegra210-uart
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- const: nvidia,tegra20-uart
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clock-frequency: true
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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current-speed:
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$ref: /schemas/types.yaml#definitions/uint32
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description: The current active speed of the UART.
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reg-offset:
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description: |
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Offset to apply to the mapbase from the start of the registers.
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reg-shift:
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description: Quantity to shift the register offsets by.
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reg-io-width:
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description: |
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The size (in bytes) of the IO accesses that should be performed on the
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device. There are some systems that require 32-bit accesses to the
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UART (e.g. TI davinci).
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used-by-rtas:
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type: boolean
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description: |
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Set to indicate that the port is in use by the OpenFirmware RTAS and
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should not be registered.
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no-loopback-test:
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type: boolean
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description: |
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Set to indicate that the port does not implement loopback test mode.
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fifo-size:
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$ref: /schemas/types.yaml#definitions/uint32
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description: The fifo size of the UART.
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auto-flow-control:
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type: boolean
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description: |
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One way to enable automatic flow control support. The driver is
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allowed to detect support for the capability even without this
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property.
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tx-threshold:
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$ref: /schemas/types.yaml#definitions/uint32
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description: |
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Specify the TX FIFO low water indication for parts with programmable
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TX FIFO thresholds.
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overrun-throttle-ms:
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description: |
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How long to pause uart rx when input overrun is encountered.
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rts-gpios: true
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cts-gpios: true
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dtr-gpios: true
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dsr-gpios: true
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rng-gpios: true
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dcd-gpios: true
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aspeed,sirq-polarity-sense:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: |
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Phandle to aspeed,ast2500-scu compatible syscon alongside register
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offset and bit number to identify how the SIRQ polarity should be
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configured. One possible data source is the LPC/eSPI mode bit. Only
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applicable to aspeed,ast2500-vuart.
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required:
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- reg
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- interrupts
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unevaluatedProperties: false
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examples:
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- |
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serial@80230000 {
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compatible = "ns8250";
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reg = <0x80230000 0x100>;
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interrupts = <10>;
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reg-shift = <2>;
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clock-frequency = <48000000>;
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};
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- |
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#include <dt-bindings/gpio/gpio.h>
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serial@49042000 {
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compatible = "andestech,uart16550", "ns16550a";
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reg = <0x49042000 0x400>;
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interrupts = <80>;
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clock-frequency = <48000000>;
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cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
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rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
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dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
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dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
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dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
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rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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};
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- |
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#include <dt-bindings/clock/aspeed-clock.h>
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serial@1e787000 {
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compatible = "aspeed,ast2500-vuart";
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reg = <0x1e787000 0x40>;
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reg-shift = <2>;
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interrupts = <8>;
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clocks = <&syscon ASPEED_CLK_APB>;
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no-loopback-test;
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aspeed,sirq-polarity-sense = <&syscon 0x70 25>;
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};
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...
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