leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

drm/i915/gvt: combine access to consecutive guest context pages

Browse Source 
IOVA(GPA)s of context pages are checked and if they are consecutive,
read/write them together in one intel_gvt_hypervisor_read_gpa() /
intel_gvt_hypervisor_write_gpa().

Signed-off-by: Yan Zhao <yan.y.zhao@intel.com>
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20200415035827.26476-1-yan.y.zhao@intel.com
This commit is contained in:
Yan Zhao
2020-04-14 23:58:27 -04:00
committed by Zhenyu Wang
parent 6c2f73e26a
commit e5e113079e
1 changed files with 48 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

58
drivers/gpu/drm/i915/gvt/scheduler.c
View File

@@ -133,6 +133,8 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
void *dst; void *dst;
void *context_base; void *context_base;
unsigned long context_gpa, context_page_num; unsigned long context_gpa, context_page_num;
unsigned long gpa_base; /* first gpa of consecutive GPAs */
unsigned long gpa_size; /* size of consecutive GPAs */
int i; int i;
GEM_BUG_ON(!intel_context_is_pinned(ctx)); GEM_BUG_ON(!intel_context_is_pinned(ctx));
@@ -186,8 +188,11 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
if (IS_BROADWELL(gvt->gt->i915) && workload->engine->id == RCS0) if (IS_BROADWELL(gvt->gt->i915) && workload->engine->id == RCS0)
context_page_num = 19; context_page_num = 19;
i = 2; /* find consecutive GPAs from gma until the first inconsecutive GPA.
while (i < context_page_num) { * read from the continuous GPAs into dst virtual address
*/
gpa_size = 0;
for (i = 2; i < context_page_num; i++) {
context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
(u32)((workload->ctx_desc.lrca + i) << (u32)((workload->ctx_desc.lrca + i) <<
I915_GTT_PAGE_SHIFT)); I915_GTT_PAGE_SHIFT));
@@ -196,10 +201,24 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
return -EFAULT; return -EFAULT;
} }
if (gpa_size == 0) {
gpa_base = context_gpa;
dst = context_base + (i << I915_GTT_PAGE_SHIFT);
} else if (context_gpa != gpa_base + gpa_size)
goto read;
gpa_size += I915_GTT_PAGE_SIZE;
if (i == context_page_num - 1)
goto read;
continue;
read:
intel_gvt_hypervisor_read_gpa(vgpu, gpa_base, dst, gpa_size);
gpa_base = context_gpa;
gpa_size = I915_GTT_PAGE_SIZE;
dst = context_base + (i << I915_GTT_PAGE_SHIFT); dst = context_base + (i << I915_GTT_PAGE_SHIFT);
intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
I915_GTT_PAGE_SIZE);
i++;
} }
return 0; return 0;
} }
@@ -789,6 +808,8 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
void *context_base; void *context_base;
void *src; void *src;
unsigned long context_gpa, context_page_num; unsigned long context_gpa, context_page_num;
unsigned long gpa_base; /* first gpa of consecutive GPAs */
unsigned long gpa_size; /* size of consecutive GPAs*/
int i; int i;
u32 ring_base; u32 ring_base;
u32 head, tail; u32 head, tail;
@@ -822,11 +843,14 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0) if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0)
context_page_num = 19; context_page_num = 19;
i = 2;
context_base = (void *) ctx->lrc_reg_state - context_base = (void *) ctx->lrc_reg_state -
(LRC_STATE_PN << I915_GTT_PAGE_SHIFT); (LRC_STATE_PN << I915_GTT_PAGE_SHIFT);
while (i < context_page_num) { /* find consecutive GPAs from gma until the first inconsecutive GPA.
* write to the consecutive GPAs from src virtual address
*/
gpa_size = 0;
for (i = 2; i < context_page_num; i++) {
context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
(u32)((workload->ctx_desc.lrca + i) << (u32)((workload->ctx_desc.lrca + i) <<
I915_GTT_PAGE_SHIFT)); I915_GTT_PAGE_SHIFT));
@@ -835,10 +859,24 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
return; return;
} }
if (gpa_size == 0) {
gpa_base = context_gpa;
src = context_base + (i << I915_GTT_PAGE_SHIFT);
} else if (context_gpa != gpa_base + gpa_size)
goto write;
gpa_size += I915_GTT_PAGE_SIZE;
if (i == context_page_num - 1)
goto write;
continue;
write:
intel_gvt_hypervisor_write_gpa(vgpu, gpa_base, src, gpa_size);
gpa_base = context_gpa;
gpa_size = I915_GTT_PAGE_SIZE;
src = context_base + (i << I915_GTT_PAGE_SHIFT); src = context_base + (i << I915_GTT_PAGE_SHIFT);
intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
I915_GTT_PAGE_SIZE);
i++;
} }
intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +