ARM: S3C2443: Move i2s clock definitions to common code
S3C2416/S3C2450 use the same clocks for their i2s blocks and can therefore reuse the existing ones. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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7301794c87
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@ -57,10 +57,6 @@
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/* clock selections */
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/* clock selections */
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static struct clk clk_i2s_ext = {
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.name = "i2s-ext",
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};
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/* armdiv
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/* armdiv
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*
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*
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* this clock is sourced from msysclk and can have a number of
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* this clock is sourced from msysclk and can have a number of
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@ -235,48 +231,6 @@ static struct clk clk_hsmmc = {
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},
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},
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};
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};
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/* i2s_eplldiv
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*
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* This clock is the output from the I2S divisor of ESYSCLK, and is separate
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* from the mux that comes after it (cannot merge into one single clock)
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*/
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static struct clksrc_clk clk_i2s_eplldiv = {
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.clk = {
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.name = "i2s-eplldiv",
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.parent = &clk_esysclk.clk,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
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};
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/* i2s-ref
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*
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* i2s bus reference clock, selectable from external, esysclk or epllref
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*
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* Note, this used to be two clocks, but was compressed into one.
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*/
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struct clk *clk_i2s_srclist[] = {
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[0] = &clk_i2s_eplldiv.clk,
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[1] = &clk_i2s_ext,
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[2] = &clk_epllref.clk,
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[3] = &clk_epllref.clk,
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};
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static struct clksrc_clk clk_i2s = {
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.clk = {
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.name = "i2s-if",
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.ctrlbit = S3C2443_SCLKCON_I2SCLK,
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.enable = s3c2443_clkcon_enable_s,
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},
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.sources = &(struct clksrc_sources) {
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.sources = clk_i2s_srclist,
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.nr_sources = ARRAY_SIZE(clk_i2s_srclist),
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},
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.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
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};
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/* standard clock definitions */
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/* standard clock definitions */
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static struct clk init_clocks_off[] = {
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static struct clk init_clocks_off[] = {
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@ -285,11 +239,6 @@ static struct clk init_clocks_off[] = {
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.parent = &clk_p,
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_SDI,
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.ctrlbit = S3C2443_PCLKCON_SDI,
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}, {
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.name = "iis",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_IIS,
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}, {
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}, {
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.name = "spi",
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.name = "spi",
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.devname = "s3c2410-spi.0",
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.devname = "s3c2410-spi.0",
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@ -312,8 +261,6 @@ static struct clk init_clocks[] = {
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static struct clksrc_clk *clksrcs[] __initdata = {
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static struct clksrc_clk *clksrcs[] __initdata = {
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&clk_arm,
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&clk_arm,
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&clk_i2s_eplldiv,
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&clk_i2s,
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&clk_hsspi,
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&clk_hsspi,
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&clk_hsmmc_div,
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&clk_hsmmc_div,
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};
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};
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@ -205,9 +205,59 @@ static struct clksrc_clk clksrc_clks[] = {
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},
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},
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};
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};
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static struct clk clk_i2s_ext = {
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.name = "i2s-ext",
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};
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/* i2s_eplldiv
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*
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* This clock is the output from the I2S divisor of ESYSCLK, and is separate
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* from the mux that comes after it (cannot merge into one single clock)
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*/
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static struct clksrc_clk clk_i2s_eplldiv = {
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.clk = {
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.name = "i2s-eplldiv",
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.parent = &clk_esysclk.clk,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
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};
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/* i2s-ref
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*
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* i2s bus reference clock, selectable from external, esysclk or epllref
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*
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* Note, this used to be two clocks, but was compressed into one.
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*/
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static struct clk *clk_i2s_srclist[] = {
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[0] = &clk_i2s_eplldiv.clk,
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[1] = &clk_i2s_ext,
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[2] = &clk_epllref.clk,
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[3] = &clk_epllref.clk,
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};
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static struct clksrc_clk clk_i2s = {
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.clk = {
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.name = "i2s-if",
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.ctrlbit = S3C2443_SCLKCON_I2SCLK,
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.enable = s3c2443_clkcon_enable_s,
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},
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.sources = &(struct clksrc_sources) {
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.sources = clk_i2s_srclist,
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.nr_sources = ARRAY_SIZE(clk_i2s_srclist),
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},
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.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
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};
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static struct clk init_clocks_off[] = {
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static struct clk init_clocks_off[] = {
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{
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{
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.name = "iis",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_IIS,
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}, {
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.name = "adc",
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.name = "adc",
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.parent = &clk_p,
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.enable = s3c2443_clkcon_enable_p,
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@ -406,6 +456,8 @@ static struct clk *clks[] __initdata = {
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};
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};
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static struct clksrc_clk *clksrcs[] __initdata = {
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static struct clksrc_clk *clksrcs[] __initdata = {
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&clk_i2s_eplldiv,
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&clk_i2s,
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&clk_usb_bus_host,
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&clk_usb_bus_host,
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&clk_epllref,
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&clk_epllref,
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&clk_esysclk,
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&clk_esysclk,
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