forked from Minki/linux
IB/ipath: Need to always request and handle PIO avail interrupts
Now that we always use PIO for vl15 on 7220, we could get stuck forever if we happened to run out of PIO buffers from the verbs code, because the setup code wouldn't run; the interrupt was also ignored if SDMA was supported. We also have to reduce the pio update threshold if we have fewer kernel buffers than the existing threshold. Clean up the initialization a bit to get ordering safer and more sensible, and use the existing ipath_chg_kernavail call to do init, rather than doing it separately. Drop unnecessary clearing of pio buffer on pio parity error. Drop incorrect updating of pioavailshadow when exitting freeze mode (software state may not match chip state if buffer has been allocated and not yet written). If we couldn't get a kernel buffer for a while, make sure we are in sync with hardware, mainly to handle the exitting freeze case. Signed-off-by: Dave Olson <dave.olson@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
This commit is contained in:
Dave Olson
Roland Dreier
parent
2889d1ef12
commit
e2ab41cae4
@ -1428,6 +1428,40 @@ static void ipath_update_pio_bufs(struct ipath_devdata *dd)
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spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
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}
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/*
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* used to force update of pioavailshadow if we can't get a pio buffer.
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* Needed primarily due to exitting freeze mode after recovering
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* from errors. Done lazily, because it's safer (known to not
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* be writing pio buffers).
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*/
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static void ipath_reset_availshadow(struct ipath_devdata *dd)
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{
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int i, im;
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unsigned long flags;
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spin_lock_irqsave(&ipath_pioavail_lock, flags);
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for (i = 0; i < dd->ipath_pioavregs; i++) {
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u64 val, oldval;
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/* deal with 6110 chip bug on high register #s */
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im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ?
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i ^ 1 : i;
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val = le64_to_cpu(dd->ipath_pioavailregs_dma[im]);
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/*
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* busy out the buffers not in the kernel avail list,
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* without changing the generation bits.
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*/
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oldval = dd->ipath_pioavailshadow[i];
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dd->ipath_pioavailshadow[i] = val |
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((~dd->ipath_pioavailkernel[i] <<
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INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT) &
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0xaaaaaaaaaaaaaaaaULL); /* All BUSY bits in qword */
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if (oldval != dd->ipath_pioavailshadow[i])
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ipath_dbg("shadow[%d] was %Lx, now %lx\n",
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i, oldval, dd->ipath_pioavailshadow[i]);
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}
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spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
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}
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/**
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* ipath_setrcvhdrsize - set the receive header size
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* @dd: the infinipath device
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@ -1482,9 +1516,12 @@ static noinline void no_pio_bufs(struct ipath_devdata *dd)
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*/
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ipath_stats.sps_nopiobufs++;
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if (!(++dd->ipath_consec_nopiobuf % 100000)) {
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ipath_dbg("%u pio sends with no bufavail; dmacopy: "
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"%llx %llx %llx %llx; shadow: %lx %lx %lx %lx\n",
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ipath_force_pio_avail_update(dd); /* at start */
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ipath_dbg("%u tries no piobufavail ts%lx; dmacopy: "
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"%llx %llx %llx %llx\n"
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"ipath shadow: %lx %lx %lx %lx\n",
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dd->ipath_consec_nopiobuf,
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(unsigned long)get_cycles(),
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(unsigned long long) le64_to_cpu(dma[0]),
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(unsigned long long) le64_to_cpu(dma[1]),
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(unsigned long long) le64_to_cpu(dma[2]),
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@ -1496,14 +1533,17 @@ static noinline void no_pio_bufs(struct ipath_devdata *dd)
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*/
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if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) >
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(sizeof(shadow[0]) * 4 * 4))
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ipath_dbg("2nd group: dmacopy: %llx %llx "
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"%llx %llx; shadow: %lx %lx %lx %lx\n",
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ipath_dbg("2nd group: dmacopy: "
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"%llx %llx %llx %llx\n"
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"ipath shadow: %lx %lx %lx %lx\n",
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(unsigned long long)le64_to_cpu(dma[4]),
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(unsigned long long)le64_to_cpu(dma[5]),
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(unsigned long long)le64_to_cpu(dma[6]),
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(unsigned long long)le64_to_cpu(dma[7]),
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shadow[4], shadow[5], shadow[6],
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shadow[7]);
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shadow[4], shadow[5], shadow[6], shadow[7]);
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/* at end, so update likely happened */
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ipath_reset_availshadow(dd);
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}
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}
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@ -1652,19 +1692,46 @@ void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start,
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unsigned len, int avail)
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{
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unsigned long flags;
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unsigned end;
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unsigned end, cnt = 0, next;
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/* There are two bits per send buffer (busy and generation) */
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start *= 2;
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len *= 2;
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end = start + len;
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end = start + len * 2;
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/* Set or clear the generation bits. */
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spin_lock_irqsave(&ipath_pioavail_lock, flags);
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/* Set or clear the busy bit in the shadow. */
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while (start < end) {
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if (avail) {
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__clear_bit(start + INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT,
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dd->ipath_pioavailshadow);
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unsigned long dma;
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int i, im;
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/*
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* the BUSY bit will never be set, because we disarm
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* the user buffers before we hand them back to the
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* kernel. We do have to make sure the generation
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* bit is set correctly in shadow, since it could
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* have changed many times while allocated to user.
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* We can't use the bitmap functions on the full
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* dma array because it is always little-endian, so
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* we have to flip to host-order first.
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* BITS_PER_LONG is slightly wrong, since it's
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* always 64 bits per register in chip...
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* We only work on 64 bit kernels, so that's OK.
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*/
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/* deal with 6110 chip bug on high register #s */
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i = start / BITS_PER_LONG;
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im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ?
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i ^ 1 : i;
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__clear_bit(INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT
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+ start, dd->ipath_pioavailshadow);
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dma = (unsigned long) le64_to_cpu(
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dd->ipath_pioavailregs_dma[im]);
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if (test_bit((INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
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+ start) % BITS_PER_LONG, &dma))
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__set_bit(INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
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+ start, dd->ipath_pioavailshadow);
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else
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__clear_bit(INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
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+ start, dd->ipath_pioavailshadow);
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__set_bit(start, dd->ipath_pioavailkernel);
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} else {
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__set_bit(start + INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT,
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@ -1673,7 +1740,44 @@ void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start,
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}
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start += 2;
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}
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if (dd->ipath_pioupd_thresh) {
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end = 2 * (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k);
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next = find_first_bit(dd->ipath_pioavailkernel, end);
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while (next < end) {
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cnt++;
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next = find_next_bit(dd->ipath_pioavailkernel, end,
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next + 1);
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}
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}
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spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
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/*
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* When moving buffers from kernel to user, if number assigned to
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* the user is less than the pio update threshold, and threshold
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* is supported (cnt was computed > 0), drop the update threshold
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* so we update at least once per allocated number of buffers.
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* In any case, if the kernel buffers are less than the threshold,
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* drop the threshold. We don't bother increasing it, having once
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* decreased it, since it would typically just cycle back and forth.
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* If we don't decrease below buffers in use, we can wait a long
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* time for an update, until some other context uses PIO buffers.
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*/
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if (!avail && len < cnt)
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cnt = len;
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if (cnt < dd->ipath_pioupd_thresh) {
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dd->ipath_pioupd_thresh = cnt;
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ipath_dbg("Decreased pio update threshold to %u\n",
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dd->ipath_pioupd_thresh);
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spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
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dd->ipath_sendctrl &= ~(INFINIPATH_S_UPDTHRESH_MASK
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<< INFINIPATH_S_UPDTHRESH_SHIFT);
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dd->ipath_sendctrl |= dd->ipath_pioupd_thresh
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<< INFINIPATH_S_UPDTHRESH_SHIFT;
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ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
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dd->ipath_sendctrl);
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spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
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}
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}
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/**
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@ -173,47 +173,25 @@ static int ipath_get_base_info(struct file *fp,
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(void *) dd->ipath_statusp -
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(void *) dd->ipath_pioavailregs_dma;
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if (!shared) {
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kinfo->spi_piocnt = dd->ipath_pbufsport;
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kinfo->spi_piocnt = pd->port_piocnt;
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kinfo->spi_piobufbase = (u64) pd->port_piobufs;
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kinfo->__spi_uregbase = (u64) dd->ipath_uregbase +
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dd->ipath_ureg_align * pd->port_port;
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} else if (master) {
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kinfo->spi_piocnt = (dd->ipath_pbufsport / subport_cnt) +
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(dd->ipath_pbufsport % subport_cnt);
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kinfo->spi_piocnt = (pd->port_piocnt / subport_cnt) +
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(pd->port_piocnt % subport_cnt);
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/* Master's PIO buffers are after all the slave's */
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kinfo->spi_piobufbase = (u64) pd->port_piobufs +
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dd->ipath_palign *
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(dd->ipath_pbufsport - kinfo->spi_piocnt);
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(pd->port_piocnt - kinfo->spi_piocnt);
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} else {
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unsigned slave = subport_fp(fp) - 1;
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kinfo->spi_piocnt = dd->ipath_pbufsport / subport_cnt;
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kinfo->spi_piocnt = pd->port_piocnt / subport_cnt;
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kinfo->spi_piobufbase = (u64) pd->port_piobufs +
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dd->ipath_palign * kinfo->spi_piocnt * slave;
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}
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/*
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* Set the PIO avail update threshold to no larger
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* than the number of buffers per process. Note that
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* we decrease it here, but won't ever increase it.
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*/
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if (dd->ipath_pioupd_thresh &&
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kinfo->spi_piocnt < dd->ipath_pioupd_thresh) {
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unsigned long flags;
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dd->ipath_pioupd_thresh = kinfo->spi_piocnt;
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ipath_dbg("Decreased pio update threshold to %u\n",
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dd->ipath_pioupd_thresh);
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spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
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dd->ipath_sendctrl &= ~(INFINIPATH_S_UPDTHRESH_MASK
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<< INFINIPATH_S_UPDTHRESH_SHIFT);
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dd->ipath_sendctrl |= dd->ipath_pioupd_thresh
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<< INFINIPATH_S_UPDTHRESH_SHIFT;
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ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
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dd->ipath_sendctrl);
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spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
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}
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if (shared) {
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kinfo->spi_port_uregbase = (u64) dd->ipath_uregbase +
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dd->ipath_ureg_align * pd->port_port;
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@ -1309,19 +1287,19 @@ static int ipath_mmap(struct file *fp, struct vm_area_struct *vma)
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ureg = dd->ipath_uregbase + dd->ipath_ureg_align * pd->port_port;
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if (!pd->port_subport_cnt) {
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/* port is not shared */
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piocnt = dd->ipath_pbufsport;
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piocnt = pd->port_piocnt;
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piobufs = pd->port_piobufs;
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} else if (!subport_fp(fp)) {
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/* caller is the master */
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piocnt = (dd->ipath_pbufsport / pd->port_subport_cnt) +
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(dd->ipath_pbufsport % pd->port_subport_cnt);
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piocnt = (pd->port_piocnt / pd->port_subport_cnt) +
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(pd->port_piocnt % pd->port_subport_cnt);
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piobufs = pd->port_piobufs +
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dd->ipath_palign * (dd->ipath_pbufsport - piocnt);
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dd->ipath_palign * (pd->port_piocnt - piocnt);
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} else {
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unsigned slave = subport_fp(fp) - 1;
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/* caller is a slave */
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piocnt = dd->ipath_pbufsport / pd->port_subport_cnt;
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piocnt = pd->port_piocnt / pd->port_subport_cnt;
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piobufs = pd->port_piobufs + dd->ipath_palign * piocnt * slave;
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}
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@ -1633,9 +1611,6 @@ static int try_alloc_port(struct ipath_devdata *dd, int port,
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port_fp(fp) = pd;
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pd->port_pid = current->pid;
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strncpy(pd->port_comm, current->comm, sizeof(pd->port_comm));
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ipath_chg_pioavailkernel(dd,
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dd->ipath_pbufsport * (pd->port_port - 1),
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dd->ipath_pbufsport, 0);
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ipath_stats.sps_ports++;
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ret = 0;
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} else
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@ -1938,11 +1913,25 @@ static int ipath_do_user_init(struct file *fp,
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/* for now we do nothing with rcvhdrcnt: uinfo->spu_rcvhdrcnt */
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/* some ports may get extra buffers, calculate that here */
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if (pd->port_port <= dd->ipath_ports_extrabuf)
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pd->port_piocnt = dd->ipath_pbufsport + 1;
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else
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pd->port_piocnt = dd->ipath_pbufsport;
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/* for right now, kernel piobufs are at end, so port 1 is at 0 */
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if (pd->port_port <= dd->ipath_ports_extrabuf)
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pd->port_pio_base = (dd->ipath_pbufsport + 1)
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* (pd->port_port - 1);
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else
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pd->port_pio_base = dd->ipath_ports_extrabuf +
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dd->ipath_pbufsport * (pd->port_port - 1);
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pd->port_piobufs = dd->ipath_piobufbase +
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dd->ipath_pbufsport * (pd->port_port - 1) * dd->ipath_palign;
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ipath_cdbg(VERBOSE, "Set base of piobufs for port %u to 0x%x\n",
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pd->port_port, pd->port_piobufs);
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pd->port_pio_base * dd->ipath_palign;
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ipath_cdbg(VERBOSE, "piobuf base for port %u is 0x%x, piocnt %u,"
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" first pio %u\n", pd->port_port, pd->port_piobufs,
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pd->port_piocnt, pd->port_pio_base);
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ipath_chg_pioavailkernel(dd, pd->port_pio_base, pd->port_piocnt, 0);
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/*
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* Now allocate the rcvhdr Q and eager TIDs; skip the TID
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@ -2107,7 +2096,6 @@ static int ipath_close(struct inode *in, struct file *fp)
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}
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if (dd->ipath_kregbase) {
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int i;
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/* atomically clear receive enable port and intr avail. */
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clear_bit(dd->ipath_r_portenable_shift + port,
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&dd->ipath_rcvctrl);
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@ -2136,9 +2124,9 @@ static int ipath_close(struct inode *in, struct file *fp)
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ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr,
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pd->port_port, dd->ipath_dummy_hdrq_phys);
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i = dd->ipath_pbufsport * (port - 1);
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ipath_disarm_piobufs(dd, i, dd->ipath_pbufsport);
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ipath_chg_pioavailkernel(dd, i, dd->ipath_pbufsport, 1);
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ipath_disarm_piobufs(dd, pd->port_pio_base, pd->port_piocnt);
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ipath_chg_pioavailkernel(dd, pd->port_pio_base,
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pd->port_piocnt, 1);
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dd->ipath_f_clear_tids(dd, pd->port_port);
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@ -595,7 +595,7 @@ static void ipath_7220_txe_recover(struct ipath_devdata *dd)
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dev_info(&dd->pcidev->dev,
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"Recovering from TXE PIO parity error\n");
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ipath_disarm_senderrbufs(dd, 1);
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ipath_disarm_senderrbufs(dd);
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}
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@ -675,10 +675,8 @@ static void ipath_7220_handle_hwerrors(struct ipath_devdata *dd, char *msg,
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ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
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if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
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/*
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* Parity errors in send memory are recoverable,
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* just cancel the send (if indicated in * sendbuffererror),
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* count the occurrence, unfreeze (if no other handled
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* hardware error bits are set), and continue.
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* Parity errors in send memory are recoverable by h/w
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* just do housekeeping, exit freeze mode and continue.
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*/
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if (hwerrs & ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
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INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
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@ -687,13 +685,6 @@ static void ipath_7220_handle_hwerrors(struct ipath_devdata *dd, char *msg,
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hwerrs &= ~((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
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INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
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<< INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT);
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if (!hwerrs) {
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/* else leave in freeze mode */
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ipath_write_kreg(dd,
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dd->ipath_kregs->kr_control,
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dd->ipath_control);
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goto bail;
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}
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}
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if (hwerrs) {
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/*
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@ -723,8 +714,8 @@ static void ipath_7220_handle_hwerrors(struct ipath_devdata *dd, char *msg,
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*dd->ipath_statusp |= IPATH_STATUS_HWERROR;
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dd->ipath_flags &= ~IPATH_INITTED;
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} else {
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ipath_dbg("Clearing freezemode on ignored hardware "
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"error\n");
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ipath_dbg("Clearing freezemode on ignored or "
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"recovered hardware error\n");
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ipath_clear_freeze(dd);
|
||||
}
|
||||
}
|
||||
@ -1967,7 +1958,7 @@ static void ipath_7220_config_ports(struct ipath_devdata *dd, ushort cfgports)
|
||||
dd->ipath_rcvctrl);
|
||||
dd->ipath_p0_rcvegrcnt = 2048; /* always */
|
||||
if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
|
||||
dd->ipath_pioreserved = 1; /* reserve a buffer */
|
||||
dd->ipath_pioreserved = 3; /* kpiobufs used for PIO */
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -41,7 +41,7 @@
|
||||
/*
|
||||
* min buffers we want to have per port, after driver
|
||||
*/
|
||||
#define IPATH_MIN_USER_PORT_BUFCNT 8
|
||||
#define IPATH_MIN_USER_PORT_BUFCNT 7
|
||||
|
||||
/*
|
||||
* Number of ports we are configured to use (to allow for more pio
|
||||
@ -54,13 +54,9 @@ MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
|
||||
|
||||
/*
|
||||
* Number of buffers reserved for driver (verbs and layered drivers.)
|
||||
* Reserved at end of buffer list. Initialized based on
|
||||
* number of PIO buffers if not set via module interface.
|
||||
* Initialized based on number of PIO buffers if not set via module interface.
|
||||
* The problem with this is that it's global, but we'll use different
|
||||
* numbers for different chip types. So the default value is not
|
||||
* very useful. I've redefined it for the 1.3 release so that it's
|
||||
* zero unless set by the user to something else, in which case we
|
||||
* try to respect it.
|
||||
* numbers for different chip types.
|
||||
*/
|
||||
static ushort ipath_kpiobufs;
|
||||
|
||||
@ -546,9 +542,12 @@ static void enable_chip(struct ipath_devdata *dd, int reinit)
|
||||
pioavail = dd->ipath_pioavailregs_dma[i ^ 1];
|
||||
else
|
||||
pioavail = dd->ipath_pioavailregs_dma[i];
|
||||
dd->ipath_pioavailshadow[i] = le64_to_cpu(pioavail) |
|
||||
(~dd->ipath_pioavailkernel[i] <<
|
||||
INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT);
|
||||
/*
|
||||
* don't need to worry about ipath_pioavailkernel here
|
||||
* because we will call ipath_chg_pioavailkernel() later
|
||||
* in initialization, to busy out buffers as needed
|
||||
*/
|
||||
dd->ipath_pioavailshadow[i] = le64_to_cpu(pioavail);
|
||||
}
|
||||
/* can get counters, stats, etc. */
|
||||
dd->ipath_flags |= IPATH_PRESENT;
|
||||
@ -708,12 +707,11 @@ static void verify_interrupt(unsigned long opaque)
|
||||
int ipath_init_chip(struct ipath_devdata *dd, int reinit)
|
||||
{
|
||||
int ret = 0;
|
||||
u32 val32, kpiobufs;
|
||||
u32 kpiobufs, defkbufs;
|
||||
u32 piobufs, uports;
|
||||
u64 val;
|
||||
struct ipath_portdata *pd;
|
||||
gfp_t gfp_flags = GFP_USER | __GFP_COMP;
|
||||
unsigned long flags;
|
||||
|
||||
ret = init_housekeeping(dd, reinit);
|
||||
if (ret)
|
||||
@ -753,69 +751,52 @@ int ipath_init_chip(struct ipath_devdata *dd, int reinit)
|
||||
dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2)
|
||||
/ (sizeof(u64) * BITS_PER_BYTE / 2);
|
||||
uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0;
|
||||
if (ipath_kpiobufs == 0) {
|
||||
/* not set by user (this is default) */
|
||||
if (piobufs > 144)
|
||||
kpiobufs = 32;
|
||||
else
|
||||
kpiobufs = 16;
|
||||
}
|
||||
if (piobufs > 144)
|
||||
defkbufs = 32 + dd->ipath_pioreserved;
|
||||
else
|
||||
kpiobufs = ipath_kpiobufs;
|
||||
defkbufs = 16 + dd->ipath_pioreserved;
|
||||
|
||||
if (kpiobufs + (uports * IPATH_MIN_USER_PORT_BUFCNT) > piobufs) {
|
||||
if (ipath_kpiobufs && (ipath_kpiobufs +
|
||||
(uports * IPATH_MIN_USER_PORT_BUFCNT)) > piobufs) {
|
||||
int i = (int) piobufs -
|
||||
(int) (uports * IPATH_MIN_USER_PORT_BUFCNT);
|
||||
if (i < 1)
|
||||
i = 1;
|
||||
dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of "
|
||||
"%d for kernel leaves too few for %d user ports "
|
||||
"(%d each); using %u\n", kpiobufs,
|
||||
"(%d each); using %u\n", ipath_kpiobufs,
|
||||
piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i);
|
||||
/*
|
||||
* shouldn't change ipath_kpiobufs, because could be
|
||||
* different for different devices...
|
||||
*/
|
||||
kpiobufs = i;
|
||||
}
|
||||
} else if (ipath_kpiobufs)
|
||||
kpiobufs = ipath_kpiobufs;
|
||||
else
|
||||
kpiobufs = defkbufs;
|
||||
dd->ipath_lastport_piobuf = piobufs - kpiobufs;
|
||||
dd->ipath_pbufsport =
|
||||
uports ? dd->ipath_lastport_piobuf / uports : 0;
|
||||
val32 = dd->ipath_lastport_piobuf - (dd->ipath_pbufsport * uports);
|
||||
if (val32 > 0) {
|
||||
ipath_dbg("allocating %u pbufs/port leaves %u unused, "
|
||||
"add to kernel\n", dd->ipath_pbufsport, val32);
|
||||
dd->ipath_lastport_piobuf -= val32;
|
||||
kpiobufs += val32;
|
||||
ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n",
|
||||
dd->ipath_pbufsport, val32);
|
||||
}
|
||||
/* if not an even divisor, some user ports get extra buffers */
|
||||
dd->ipath_ports_extrabuf = dd->ipath_lastport_piobuf -
|
||||
(dd->ipath_pbufsport * uports);
|
||||
if (dd->ipath_ports_extrabuf)
|
||||
ipath_dbg("%u pbufs/port leaves some unused, add 1 buffer to "
|
||||
"ports <= %u\n", dd->ipath_pbufsport,
|
||||
dd->ipath_ports_extrabuf);
|
||||
dd->ipath_lastpioindex = 0;
|
||||
dd->ipath_lastpioindexl = dd->ipath_piobcnt2k;
|
||||
ipath_chg_pioavailkernel(dd, 0, piobufs, 1);
|
||||
/* ipath_pioavailshadow initialized earlier */
|
||||
ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
|
||||
"each for %u user ports\n", kpiobufs,
|
||||
piobufs, dd->ipath_pbufsport, uports);
|
||||
if (dd->ipath_pioupd_thresh) {
|
||||
if (dd->ipath_pbufsport < dd->ipath_pioupd_thresh)
|
||||
dd->ipath_pioupd_thresh = dd->ipath_pbufsport;
|
||||
if (kpiobufs < dd->ipath_pioupd_thresh)
|
||||
dd->ipath_pioupd_thresh = kpiobufs;
|
||||
}
|
||||
|
||||
ret = dd->ipath_f_early_init(dd);
|
||||
if (ret) {
|
||||
ipath_dev_err(dd, "Early initialization failure\n");
|
||||
goto done;
|
||||
}
|
||||
|
||||
/*
|
||||
* Cancel any possible active sends from early driver load.
|
||||
* Follows early_init because some chips have to initialize
|
||||
* PIO buffers in early_init to avoid false parity errors.
|
||||
*/
|
||||
ipath_cancel_sends(dd, 0);
|
||||
|
||||
/*
|
||||
* Early_init sets rcvhdrentsize and rcvhdrsize, so this must be
|
||||
* done after early_init.
|
||||
@ -836,6 +817,7 @@ int ipath_init_chip(struct ipath_devdata *dd, int reinit)
|
||||
|
||||
ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
|
||||
dd->ipath_pioavailregs_phys);
|
||||
|
||||
/*
|
||||
* this is to detect s/w errors, which the h/w works around by
|
||||
* ignoring the low 6 bits of address, if it wasn't aligned.
|
||||
@ -862,12 +844,6 @@ int ipath_init_chip(struct ipath_devdata *dd, int reinit)
|
||||
~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
|
||||
ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
|
||||
|
||||
spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
|
||||
dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE;
|
||||
ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
|
||||
ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
|
||||
spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
|
||||
|
||||
/*
|
||||
* before error clears, since we expect serdes pll errors during
|
||||
* this, the first time after reset
|
||||
@ -940,6 +916,19 @@ int ipath_init_chip(struct ipath_devdata *dd, int reinit)
|
||||
else
|
||||
enable_chip(dd, reinit);
|
||||
|
||||
/* after enable_chip, so pioavailshadow setup */
|
||||
ipath_chg_pioavailkernel(dd, 0, piobufs, 1);
|
||||
|
||||
/*
|
||||
* Cancel any possible active sends from early driver load.
|
||||
* Follows early_init because some chips have to initialize
|
||||
* PIO buffers in early_init to avoid false parity errors.
|
||||
* After enable and ipath_chg_pioavailkernel so we can safely
|
||||
* enable pioavail updates and PIOENABLE; packets are now
|
||||
* ready to go out.
|
||||
*/
|
||||
ipath_cancel_sends(dd, 1);
|
||||
|
||||
if (!reinit) {
|
||||
/*
|
||||
* Used when we close a port, for DMA already in flight
|
||||
|
||||
@ -38,42 +38,12 @@
|
||||
#include "ipath_verbs.h"
|
||||
#include "ipath_common.h"
|
||||
|
||||
/*
|
||||
* clear (write) a pio buffer, to clear a parity error. This routine
|
||||
* should only be called when in freeze mode, and the buffer should be
|
||||
* canceled afterwards.
|
||||
*/
|
||||
static void ipath_clrpiobuf(struct ipath_devdata *dd, u32 pnum)
|
||||
{
|
||||
u32 __iomem *pbuf;
|
||||
u32 dwcnt; /* dword count to write */
|
||||
if (pnum < dd->ipath_piobcnt2k) {
|
||||
pbuf = (u32 __iomem *) (dd->ipath_pio2kbase + pnum *
|
||||
dd->ipath_palign);
|
||||
dwcnt = dd->ipath_piosize2k >> 2;
|
||||
}
|
||||
else {
|
||||
pbuf = (u32 __iomem *) (dd->ipath_pio4kbase +
|
||||
(pnum - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
|
||||
dwcnt = dd->ipath_piosize4k >> 2;
|
||||
}
|
||||
dev_info(&dd->pcidev->dev,
|
||||
"Rewrite PIO buffer %u, to recover from parity error\n",
|
||||
pnum);
|
||||
|
||||
/* no flush required, since already in freeze */
|
||||
writel(dwcnt + 1, pbuf);
|
||||
while (--dwcnt)
|
||||
writel(0, pbuf++);
|
||||
}
|
||||
|
||||
/*
|
||||
* Called when we might have an error that is specific to a particular
|
||||
* PIO buffer, and may need to cancel that buffer, so it can be re-used.
|
||||
* If rewrite is true, and bits are set in the sendbufferror registers,
|
||||
* we'll write to the buffer, for error recovery on parity errors.
|
||||
*/
|
||||
void ipath_disarm_senderrbufs(struct ipath_devdata *dd, int rewrite)
|
||||
void ipath_disarm_senderrbufs(struct ipath_devdata *dd)
|
||||
{
|
||||
u32 piobcnt;
|
||||
unsigned long sbuf[4];
|
||||
@ -109,11 +79,8 @@ void ipath_disarm_senderrbufs(struct ipath_devdata *dd, int rewrite)
|
||||
}
|
||||
|
||||
for (i = 0; i < piobcnt; i++)
|
||||
if (test_bit(i, sbuf)) {
|
||||
if (rewrite)
|
||||
ipath_clrpiobuf(dd, i);
|
||||
if (test_bit(i, sbuf))
|
||||
ipath_disarm_piobufs(dd, i, 1);
|
||||
}
|
||||
/* ignore armlaunch errs for a bit */
|
||||
dd->ipath_lastcancel = jiffies+3;
|
||||
}
|
||||
@ -164,7 +131,7 @@ static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs)
|
||||
{
|
||||
u64 ignore_this_time = 0;
|
||||
|
||||
ipath_disarm_senderrbufs(dd, 0);
|
||||
ipath_disarm_senderrbufs(dd);
|
||||
if ((errs & E_SUM_LINK_PKTERRS) &&
|
||||
!(dd->ipath_flags & IPATH_LINKACTIVE)) {
|
||||
/*
|
||||
@ -909,8 +876,8 @@ static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs)
|
||||
* processes (causing armlaunch), send errors due to going into freeze mode,
|
||||
* etc., and try to avoid causing extra interrupts while doing so.
|
||||
* Forcibly update the in-memory pioavail register copies after cleanup
|
||||
* because the chip won't do it for anything changing while in freeze mode
|
||||
* (we don't want to wait for the next pio buffer state change).
|
||||
* because the chip won't do it while in freeze mode (the register values
|
||||
* themselves are kept correct).
|
||||
* Make sure that we don't lose any important interrupts by using the chip
|
||||
* feature that says that writing 0 to a bit in *clear that is set in
|
||||
* *status will cause an interrupt to be generated again (if allowed by
|
||||
@ -918,47 +885,22 @@ static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs)
|
||||
*/
|
||||
void ipath_clear_freeze(struct ipath_devdata *dd)
|
||||
{
|
||||
int i, im;
|
||||
u64 val;
|
||||
|
||||
/* disable error interrupts, to avoid confusion */
|
||||
ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 0ULL);
|
||||
|
||||
/* also disable interrupts; errormask is sometimes overwriten */
|
||||
ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
|
||||
|
||||
/*
|
||||
* clear all sends, because they have may been
|
||||
* completed by usercode while in freeze mode, and
|
||||
* therefore would not be sent, and eventually
|
||||
* might cause the process to run out of bufs
|
||||
*/
|
||||
ipath_cancel_sends(dd, 1);
|
||||
|
||||
/* clear the freeze, and be sure chip saw it */
|
||||
ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
|
||||
dd->ipath_control);
|
||||
ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
|
||||
|
||||
/*
|
||||
* ensure pio avail updates continue (because the update
|
||||
* won't have happened from cancel_sends because we were
|
||||
* still in freeze
|
||||
*/
|
||||
/* force in-memory update now we are out of freeze */
|
||||
ipath_force_pio_avail_update(dd);
|
||||
|
||||
/*
|
||||
* We just enabled pioavailupdate, so dma copy is almost certainly
|
||||
* not yet right, so read the registers directly. Similar to init
|
||||
*/
|
||||
for (i = 0; i < dd->ipath_pioavregs; i++) {
|
||||
/* deal with 6110 chip bug */
|
||||
im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ?
|
||||
i ^ 1 : i;
|
||||
val = ipath_read_kreg64(dd, (0x1000 / sizeof(u64)) + im);
|
||||
dd->ipath_pioavailregs_dma[i] = cpu_to_le64(val);
|
||||
dd->ipath_pioavailshadow[i] = val |
|
||||
(~dd->ipath_pioavailkernel[i] <<
|
||||
INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT);
|
||||
}
|
||||
|
||||
/*
|
||||
* force new interrupt if any hwerr, error or interrupt bits are
|
||||
* still set, and clear "safe" send packet errors related to freeze
|
||||
@ -1316,10 +1258,8 @@ irqreturn_t ipath_intr(int irq, void *data)
|
||||
ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
|
||||
spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
|
||||
|
||||
if (!(dd->ipath_flags & IPATH_HAS_SEND_DMA))
|
||||
handle_layer_pioavail(dd);
|
||||
else
|
||||
ipath_dbg("unexpected BUFAVAIL intr\n");
|
||||
/* always process; sdma verbs uses PIO for acks and VL15 */
|
||||
handle_layer_pioavail(dd);
|
||||
}
|
||||
|
||||
ret = IRQ_HANDLED;
|
||||
|
||||
@ -117,6 +117,10 @@ struct ipath_portdata {
|
||||
u16 port_subport_cnt;
|
||||
/* non-zero if port is being shared. */
|
||||
u16 port_subport_id;
|
||||
/* number of pio bufs for this port (all procs, if shared) */
|
||||
u32 port_piocnt;
|
||||
/* first pio buffer for this port */
|
||||
u32 port_pio_base;
|
||||
/* chip offset of PIO buffers for this port */
|
||||
u32 port_piobufs;
|
||||
/* how many alloc_pages() chunks in port_rcvegrbuf_pages */
|
||||
@ -384,6 +388,8 @@ struct ipath_devdata {
|
||||
u32 ipath_lastrpkts;
|
||||
/* pio bufs allocated per port */
|
||||
u32 ipath_pbufsport;
|
||||
/* if remainder on bufs/port, ports < extrabuf get 1 extra */
|
||||
u32 ipath_ports_extrabuf;
|
||||
u32 ipath_pioupd_thresh; /* update threshold, some chips */
|
||||
/*
|
||||
* number of ports configured as max; zero is set to number chip
|
||||
@ -1011,7 +1017,7 @@ void ipath_get_eeprom_info(struct ipath_devdata *);
|
||||
int ipath_update_eeprom_log(struct ipath_devdata *dd);
|
||||
void ipath_inc_eeprom_err(struct ipath_devdata *dd, u32 eidx, u32 incr);
|
||||
u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg);
|
||||
void ipath_disarm_senderrbufs(struct ipath_devdata *, int);
|
||||
void ipath_disarm_senderrbufs(struct ipath_devdata *);
|
||||
void ipath_force_pio_avail_update(struct ipath_devdata *);
|
||||
void signal_ib_event(struct ipath_devdata *dd, enum ib_event_type ev);
|
||||
|
||||
|
||||
@ -481,9 +481,10 @@ done:
|
||||
wake_up(&qp->wait);
|
||||
}
|
||||
|
||||
static void want_buffer(struct ipath_devdata *dd)
|
||||
static void want_buffer(struct ipath_devdata *dd, struct ipath_qp *qp)
|
||||
{
|
||||
if (!(dd->ipath_flags & IPATH_HAS_SEND_DMA)) {
|
||||
if (!(dd->ipath_flags & IPATH_HAS_SEND_DMA) ||
|
||||
qp->ibqp.qp_type == IB_QPT_SMI) {
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
|
||||
@ -519,7 +520,7 @@ static void ipath_no_bufs_available(struct ipath_qp *qp,
|
||||
spin_lock_irqsave(&dev->pending_lock, flags);
|
||||
list_add_tail(&qp->piowait, &dev->piowait);
|
||||
spin_unlock_irqrestore(&dev->pending_lock, flags);
|
||||
want_buffer(dev->dd);
|
||||
want_buffer(dev->dd, qp);
|
||||
dev->n_piowait++;
|
||||
}
|
||||
|
||||
|
||||
@ -449,16 +449,19 @@ int setup_sdma(struct ipath_devdata *dd)
|
||||
ipath_write_kreg(dd, dd->ipath_kregs->kr_senddmaheadaddr,
|
||||
dd->ipath_sdma_head_phys);
|
||||
|
||||
/* Reserve all the former "kernel" piobufs */
|
||||
n = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - dd->ipath_pioreserved;
|
||||
for (i = dd->ipath_lastport_piobuf; i < n; ++i) {
|
||||
/*
|
||||
* Reserve all the former "kernel" piobufs, using high number range
|
||||
* so we get as many 4K buffers as possible
|
||||
*/
|
||||
n = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
|
||||
i = dd->ipath_lastport_piobuf + dd->ipath_pioreserved;
|
||||
ipath_chg_pioavailkernel(dd, i, n - i , 0);
|
||||
for (; i < n; ++i) {
|
||||
unsigned word = i / 64;
|
||||
unsigned bit = i & 63;
|
||||
BUG_ON(word >= 3);
|
||||
senddmabufmask[word] |= 1ULL << bit;
|
||||
}
|
||||
ipath_chg_pioavailkernel(dd, dd->ipath_lastport_piobuf,
|
||||
n - dd->ipath_lastport_piobuf, 0);
|
||||
ipath_write_kreg(dd, dd->ipath_kregs->kr_senddmabufmask0,
|
||||
senddmabufmask[0]);
|
||||
ipath_write_kreg(dd, dd->ipath_kregs->kr_senddmabufmask1,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user