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Merge branches 'devel-hwspinlock' and 'devel-mcspi' into omap-for-linus

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This commit is contained in:
Tony Lindgren 2011-02-17 10:01:18 -08:00
commit df7ffd317d
6 changed files with 777 additions and 304 deletions
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187
arch/arm/mach-omap2/devices.c
View File

@ -15,6 +15,7 @@
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
@ -279,163 +280,55 @@ static inline void omap_init_audio(void) {}
#include <plat/mcspi.h>
#define OMAP2_MCSPI1_BASE 0x48098000
#define OMAP2_MCSPI2_BASE 0x4809a000
#define OMAP2_MCSPI3_BASE 0x480b8000
#define OMAP2_MCSPI4_BASE 0x480ba000
#define OMAP4_MCSPI1_BASE 0x48098100
#define OMAP4_MCSPI2_BASE 0x4809a100
#define OMAP4_MCSPI3_BASE 0x480b8100
#define OMAP4_MCSPI4_BASE 0x480ba100
static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
.num_cs = 4,
};
static struct resource omap2_mcspi1_resources[] = {
{
.start = OMAP2_MCSPI1_BASE,
.end = OMAP2_MCSPI1_BASE + 0xff,
.flags = IORESOURCE_MEM,
struct omap_device_pm_latency omap_mcspi_latency[] = {
[0] = {
.deactivate_func = omap_device_idle_hwmods,
.activate_func = omap_device_enable_hwmods,
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
},
};
static struct platform_device omap2_mcspi1 = {
.name = "omap2_mcspi",
.id = 1,
.num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
.resource = omap2_mcspi1_resources,
.dev = {
.platform_data = &omap2_mcspi1_config,
},
};
static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
.num_cs = 2,
};
static struct resource omap2_mcspi2_resources[] = {
{
.start = OMAP2_MCSPI2_BASE,
.end = OMAP2_MCSPI2_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device omap2_mcspi2 = {
.name = "omap2_mcspi",
.id = 2,
.num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
.resource = omap2_mcspi2_resources,
.dev = {
.platform_data = &omap2_mcspi2_config,
},
};
#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
.num_cs = 2,
};
static struct resource omap2_mcspi3_resources[] = {
{
.start = OMAP2_MCSPI3_BASE,
.end = OMAP2_MCSPI3_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device omap2_mcspi3 = {
.name = "omap2_mcspi",
.id = 3,
.num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
.resource = omap2_mcspi3_resources,
.dev = {
.platform_data = &omap2_mcspi3_config,
},
};
#endif
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
.num_cs = 1,
};
static struct resource omap2_mcspi4_resources[] = {
{
.start = OMAP2_MCSPI4_BASE,
.end = OMAP2_MCSPI4_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device omap2_mcspi4 = {
.name = "omap2_mcspi",
.id = 4,
.num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
.resource = omap2_mcspi4_resources,
.dev = {
.platform_data = &omap2_mcspi4_config,
},
};
#endif
#ifdef CONFIG_ARCH_OMAP4
static inline void omap4_mcspi_fixup(void)
static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
{
omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
}
#else
static inline void omap4_mcspi_fixup(void)
{
}
#endif
struct omap_device *od;
char *name = "omap2_mcspi";
struct omap2_mcspi_platform_config *pdata;
static int spi_num;
struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
static inline void omap2_mcspi3_init(void)
{
platform_device_register(&omap2_mcspi3);
}
#else
static inline void omap2_mcspi3_init(void)
{
}
#endif
pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
if (!pdata) {
pr_err("Memory allocation for McSPI device failed\n");
return -ENOMEM;
}
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
static inline void omap2_mcspi4_init(void)
{
platform_device_register(&omap2_mcspi4);
pdata->num_cs = mcspi_attrib->num_chipselect;
switch (oh->class->rev) {
case OMAP2_MCSPI_REV:
case OMAP3_MCSPI_REV:
pdata->regs_offset = 0;
break;
case OMAP4_MCSPI_REV:
pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
break;
default:
pr_err("Invalid McSPI Revision value\n");
return -EINVAL;
}
spi_num++;
od = omap_device_build(name, spi_num, oh, pdata,
sizeof(*pdata), omap_mcspi_latency,
ARRAY_SIZE(omap_mcspi_latency), 0);
WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n",
name, oh->name);
kfree(pdata);
return 0;
}
#else
static inline void omap2_mcspi4_init(void)
{
}
#endif
static void omap_init_mcspi(void)
{
if (cpu_is_omap44xx())
omap4_mcspi_fixup();
platform_device_register(&omap2_mcspi1);
platform_device_register(&omap2_mcspi2);
if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
omap2_mcspi3_init();
if (cpu_is_omap343x() || cpu_is_omap44xx())
omap2_mcspi4_init();
omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
}
#else

156
arch/arm/mach-omap2/omap_hwmod_2420_data.c
View File

@ -18,6 +18,7 @@
#include <plat/serial.h>
#include <plat/i2c.h>
#include <plat/gpio.h>
#include <plat/mcspi.h>
#include "omap_hwmod_common_data.h"
@ -44,6 +45,8 @@ static struct omap_hwmod omap2420_gpio2_hwmod;
static struct omap_hwmod omap2420_gpio3_hwmod;
static struct omap_hwmod omap2420_gpio4_hwmod;
static struct omap_hwmod omap2420_dma_system_hwmod;
static struct omap_hwmod omap2420_mcspi1_hwmod;
static struct omap_hwmod omap2420_mcspi2_hwmod;
/* L3 -> L4_CORE interface */
static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
@ -88,6 +91,42 @@ static struct omap_hwmod omap2420_uart3_hwmod;
static struct omap_hwmod omap2420_i2c1_hwmod;
static struct omap_hwmod omap2420_i2c2_hwmod;
/* l4 core -> mcspi1 interface */
static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
{
.pa_start = 0x48098000,
.pa_end = 0x480980ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_mcspi1_hwmod,
.clk = "mcspi1_ick",
.addr = omap2420_mcspi1_addr_space,
.addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 core -> mcspi2 interface */
static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
{
.pa_start = 0x4809a000,
.pa_end = 0x4809a0ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_mcspi2_hwmod,
.clk = "mcspi2_ick",
.addr = omap2420_mcspi2_addr_space,
.addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* L4_CORE -> L4_WKUP interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
.master = &omap2420_l4_core_hwmod,
@ -864,6 +903,119 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
/*
* 'mcspi' class
* multichannel serial port interface (mcspi) / master/slave synchronous serial
* bus
*/
static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2420_mcspi_class = {
.name = "mcspi",
.sysc = &omap2420_mcspi_sysc,
.rev = OMAP2_MCSPI_REV,
};
/* mcspi1 */
static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
{ .irq = 65 },
};
static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
};
static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
&omap2420_l4_core__mcspi1,
};
static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
.num_chipselect = 4,
};
static struct omap_hwmod omap2420_mcspi1_hwmod = {
.name = "mcspi1_hwmod",
.mpu_irqs = omap2420_mcspi1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs),
.sdma_reqs = omap2420_mcspi1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
.main_clk = "mcspi1_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.prcm_reg_id = 1,
.module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
},
},
.slaves = omap2420_mcspi1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
.class = &omap2420_mcspi_class,
.dev_attr = &omap_mcspi1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* mcspi2 */
static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
{ .irq = 66 },
};
static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
};
static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
&omap2420_l4_core__mcspi2,
};
static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
.num_chipselect = 2,
};
static struct omap_hwmod omap2420_mcspi2_hwmod = {
.name = "mcspi2_hwmod",
.mpu_irqs = omap2420_mcspi2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs),
.sdma_reqs = omap2420_mcspi2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
.main_clk = "mcspi2_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.prcm_reg_id = 1,
.module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
},
},
.slaves = omap2420_mcspi2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
.class = &omap2420_mcspi_class,
.dev_attr = &omap_mcspi2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
static __initdata struct omap_hwmod *omap2420_hwmods[] = {
&omap2420_l3_main_hwmod,
&omap2420_l4_core_hwmod,
@ -885,6 +1037,10 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
/* dma_system class*/
&omap2420_dma_system_hwmod,
/* mcspi class */
&omap2420_mcspi1_hwmod,
&omap2420_mcspi2_hwmod,
NULL,
};

219
arch/arm/mach-omap2/omap_hwmod_2430_data.c
View File

@ -18,6 +18,7 @@
#include <plat/serial.h>
#include <plat/i2c.h>
#include <plat/gpio.h>
#include <plat/mcspi.h>
#include "omap_hwmod_common_data.h"
@ -45,6 +46,9 @@ static struct omap_hwmod omap2430_gpio3_hwmod;
static struct omap_hwmod omap2430_gpio4_hwmod;
static struct omap_hwmod omap2430_gpio5_hwmod;
static struct omap_hwmod omap2430_dma_system_hwmod;
static struct omap_hwmod omap2430_mcspi1_hwmod;
static struct omap_hwmod omap2430_mcspi2_hwmod;
static struct omap_hwmod omap2430_mcspi3_hwmod;
/* L3 -> L4_CORE interface */
static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@ -223,6 +227,60 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
};
/* l4 core -> mcspi1 interface */
static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
{
.pa_start = 0x48098000,
.pa_end = 0x480980ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mcspi1_hwmod,
.clk = "mcspi1_ick",
.addr = omap2430_mcspi1_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 core -> mcspi2 interface */
static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
{
.pa_start = 0x4809a000,
.pa_end = 0x4809a0ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mcspi2_hwmod,
.clk = "mcspi2_ick",
.addr = omap2430_mcspi2_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 core -> mcspi3 interface */
static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
{
.pa_start = 0x480b8000,
.pa_end = 0x480b80ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mcspi3_hwmod,
.clk = "mcspi3_ick",
.addr = omap2430_mcspi3_addr_space,
.addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* L4 WKUP */
static struct omap_hwmod omap2430_l4_wkup_hwmod = {
.name = "l4_wkup",
@ -919,6 +977,162 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
/*
* 'mcspi' class
* multichannel serial port interface (mcspi) / master/slave synchronous serial
* bus
*/
static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2430_mcspi_class = {
.name = "mcspi",
.sysc = &omap2430_mcspi_sysc,
.rev = OMAP2_MCSPI_REV,
};
/* mcspi1 */
static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
{ .irq = 65 },
};
static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
};
static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
&omap2430_l4_core__mcspi1,
};
static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
.num_chipselect = 4,
};
static struct omap_hwmod omap2430_mcspi1_hwmod = {
.name = "mcspi1_hwmod",
.mpu_irqs = omap2430_mcspi1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
.sdma_reqs = omap2430_mcspi1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
.main_clk = "mcspi1_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.prcm_reg_id = 1,
.module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
},
},
.slaves = omap2430_mcspi1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
.class = &omap2430_mcspi_class,
.dev_attr = &omap_mcspi1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* mcspi2 */
static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
{ .irq = 66 },
};
static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
};
static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
&omap2430_l4_core__mcspi2,
};
static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
.num_chipselect = 2,
};
static struct omap_hwmod omap2430_mcspi2_hwmod = {
.name = "mcspi2_hwmod",
.mpu_irqs = omap2430_mcspi2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
.sdma_reqs = omap2430_mcspi2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
.main_clk = "mcspi2_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.prcm_reg_id = 1,
.module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
},
},
.slaves = omap2430_mcspi2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
.class = &omap2430_mcspi_class,
.dev_attr = &omap_mcspi2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* mcspi3 */
static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
{ .irq = 91 },
};
static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
{ .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
{ .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
{ .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
};
static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
&omap2430_l4_core__mcspi3,
};
static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
.num_chipselect = 2,
};
static struct omap_hwmod omap2430_mcspi3_hwmod = {
.name = "mcspi3_hwmod",
.mpu_irqs = omap2430_mcspi3_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
.sdma_reqs = omap2430_mcspi3_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
.main_clk = "mcspi3_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.prcm_reg_id = 2,
.module_bit = OMAP2430_EN_MCSPI3_SHIFT,
.idlest_reg_id = 2,
.idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
},
},
.slaves = omap2430_mcspi3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
.class = &omap2430_mcspi_class,
.dev_attr = &omap_mcspi3_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
static __initdata struct omap_hwmod *omap2430_hwmods[] = {
&omap2430_l3_main_hwmod,
&omap2430_l4_core_hwmod,
@ -941,6 +1155,11 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
/* dma_system class*/
&omap2430_dma_system_hwmod,
/* mcspi class */
&omap2430_mcspi1_hwmod,
&omap2430_mcspi2_hwmod,
&omap2430_mcspi3_hwmod,
NULL,
};

280
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@ -22,6 +22,7 @@
#include <plat/i2c.h>
#include <plat/gpio.h>
#include <plat/smartreflex.h>
#include <plat/mcspi.h>
#include "omap_hwmod_common_data.h"
@ -55,6 +56,10 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod;
static struct omap_hwmod omap3xxx_gpio6_hwmod;
static struct omap_hwmod omap34xx_sr1_hwmod;
static struct omap_hwmod omap34xx_sr2_hwmod;
static struct omap_hwmod omap34xx_mcspi1;
static struct omap_hwmod omap34xx_mcspi2;
static struct omap_hwmod omap34xx_mcspi3;
static struct omap_hwmod omap34xx_mcspi4;
static struct omap_hwmod omap3xxx_dma_system_hwmod;
@ -1356,6 +1361,275 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
/* l4 core -> mcspi1 interface */
static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
{
.pa_start = 0x48098000,
.pa_end = 0x480980ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_mcspi1,
.clk = "mcspi1_ick",
.addr = omap34xx_mcspi1_addr_space,
.addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 core -> mcspi2 interface */
static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
{
.pa_start = 0x4809a000,
.pa_end = 0x4809a0ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_mcspi2,
.clk = "mcspi2_ick",
.addr = omap34xx_mcspi2_addr_space,
.addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 core -> mcspi3 interface */
static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
{
.pa_start = 0x480b8000,
.pa_end = 0x480b80ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_mcspi3,
.clk = "mcspi3_ick",
.addr = omap34xx_mcspi3_addr_space,
.addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 core -> mcspi4 interface */
static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
{
.pa_start = 0x480ba000,
.pa_end = 0x480ba0ff,
.flags = ADDR_TYPE_RT,
},
};
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_mcspi4,
.clk = "mcspi4_ick",
.addr = omap34xx_mcspi4_addr_space,
.addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/*
* 'mcspi' class
* multichannel serial port interface (mcspi) / master/slave synchronous serial
* bus
*/
static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap34xx_mcspi_class = {
.name = "mcspi",
.sysc = &omap34xx_mcspi_sysc,
.rev = OMAP3_MCSPI_REV,
};
/* mcspi1 */
static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
{ .name = "irq", .irq = 65 },
};
static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 35 },
{ .name = "rx0", .dma_req = 36 },
{ .name = "tx1", .dma_req = 37 },
{ .name = "rx1", .dma_req = 38 },
{ .name = "tx2", .dma_req = 39 },
{ .name = "rx2", .dma_req = 40 },
{ .name = "tx3", .dma_req = 41 },
{ .name = "rx3", .dma_req = 42 },
};
static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
&omap34xx_l4_core__mcspi1,
};
static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
.num_chipselect = 4,
};
static struct omap_hwmod omap34xx_mcspi1 = {
.name = "mcspi1",
.mpu_irqs = omap34xx_mcspi1_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
.sdma_reqs = omap34xx_mcspi1_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
.main_clk = "mcspi1_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.prcm_reg_id = 1,
.module_bit = OMAP3430_EN_MCSPI1_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
},
},
.slaves = omap34xx_mcspi1_slaves,
.slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
.class = &omap34xx_mcspi_class,
.dev_attr = &omap_mcspi1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* mcspi2 */
static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
{ .name = "irq", .irq = 66 },
};
static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 43 },
{ .name = "rx0", .dma_req = 44 },
{ .name = "tx1", .dma_req = 45 },
{ .name = "rx1", .dma_req = 46 },
};
static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
&omap34xx_l4_core__mcspi2,
};
static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
.num_chipselect = 2,
};
static struct omap_hwmod omap34xx_mcspi2 = {
.name = "mcspi2",
.mpu_irqs = omap34xx_mcspi2_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
.sdma_reqs = omap34xx_mcspi2_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
.main_clk = "mcspi2_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.prcm_reg_id = 1,
.module_bit = OMAP3430_EN_MCSPI2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
},
},
.slaves = omap34xx_mcspi2_slaves,
.slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
.class = &omap34xx_mcspi_class,
.dev_attr = &omap_mcspi2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* mcspi3 */
static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
{ .name = "irq", .irq = 91 }, /* 91 */
};
static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 15 },
{ .name = "rx0", .dma_req = 16 },
{ .name = "tx1", .dma_req = 23 },
{ .name = "rx1", .dma_req = 24 },
};
static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
&omap34xx_l4_core__mcspi3,
};
static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
.num_chipselect = 2,
};
static struct omap_hwmod omap34xx_mcspi3 = {
.name = "mcspi3",
.mpu_irqs = omap34xx_mcspi3_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
.sdma_reqs = omap34xx_mcspi3_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
.main_clk = "mcspi3_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.prcm_reg_id = 1,
.module_bit = OMAP3430_EN_MCSPI3_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
},
},
.slaves = omap34xx_mcspi3_slaves,
.slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
.class = &omap34xx_mcspi_class,
.dev_attr = &omap_mcspi3_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* SPI4 */
static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
{ .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
};
static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
{ .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
};
static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
&omap34xx_l4_core__mcspi4,
};
static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
.num_chipselect = 1,
};
static struct omap_hwmod omap34xx_mcspi4 = {
.name = "mcspi4",
.mpu_irqs = omap34xx_mcspi4_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
.sdma_reqs = omap34xx_mcspi4_sdma_reqs,
.sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
.main_clk = "mcspi4_fck",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.prcm_reg_id = 1,
.module_bit = OMAP3430_EN_MCSPI4_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
},
},
.slaves = omap34xx_mcspi4_slaves,
.slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
.class = &omap34xx_mcspi_class,
.dev_attr = &omap_mcspi4_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap3xxx_l3_main_hwmod,
&omap3xxx_l4_core_hwmod,
@ -1387,6 +1661,12 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
/* dma_system class*/
&omap3xxx_dma_system_hwmod,
/* mcspi class */
&omap34xx_mcspi1,
&omap34xx_mcspi2,
&omap34xx_mcspi3,
&omap34xx_mcspi4,
NULL,
};

11
arch/arm/plat-omap/include/plat/mcspi.h
View File

@ -1,8 +1,19 @@
#ifndef _OMAP2_MCSPI_H
#define _OMAP2_MCSPI_H
#define OMAP2_MCSPI_REV 0
#define OMAP3_MCSPI_REV 1
#define OMAP4_MCSPI_REV 2
#define OMAP4_MCSPI_REG_OFFSET 0x100
struct omap2_mcspi_platform_config {
unsigned short num_cs;
unsigned int regs_offset;
};
struct omap2_mcspi_dev_attr {
unsigned short num_chipselect;
};
struct omap2_mcspi_device_config {

228
drivers/spi/omap2_mcspi.c
View File

@ -3,7 +3,7 @@
*
* Copyright (C) 2005, 2006 Nokia Corporation
* Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
* Juha Yrjölä <juha.yrjola@nokia.com>
* Juha Yrj<EFBFBD>l<EFBFBD> <juha.yrjola@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -33,6 +33,7 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/spi/spi.h>
@ -46,7 +47,6 @@
#define OMAP2_MCSPI_MAX_CTRL 4
#define OMAP2_MCSPI_REVISION 0x00
#define OMAP2_MCSPI_SYSCONFIG 0x10
#define OMAP2_MCSPI_SYSSTATUS 0x14
#define OMAP2_MCSPI_IRQSTATUS 0x18
#define OMAP2_MCSPI_IRQENABLE 0x1c
@ -63,13 +63,6 @@
/* per-register bitmasks: */
#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
#define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
@ -122,13 +115,12 @@ struct omap2_mcspi {
spinlock_t lock;
struct list_head msg_queue;
struct spi_master *master;
struct clk *ick;
struct clk *fck;
/* Virtual base address of the controller */
void __iomem *base;
unsigned long phys;
/* SPI1 has 4 channels, while SPI2 has 2 */
struct omap2_mcspi_dma *dma_channels;
struct device *dev;
};
struct omap2_mcspi_cs {
@ -144,7 +136,6 @@ struct omap2_mcspi_cs {
* corresponding registers are modified.
*/
struct omap2_mcspi_regs {
u32 sysconfig;
u32 modulctrl;
u32 wakeupenable;
struct list_head cs;
@ -268,9 +259,6 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
@ -280,20 +268,12 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
}
static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
{
clk_disable(mcspi->ick);
clk_disable(mcspi->fck);
pm_runtime_put_sync(mcspi->dev);
}
static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
{
if (clk_enable(mcspi->ick))
return -ENODEV;
if (clk_enable(mcspi->fck))
return -ENODEV;
omap2_mcspi_restore_ctx(mcspi);
return 0;
return pm_runtime_get_sync(mcspi->dev);
}
static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
@ -819,8 +799,9 @@ static int omap2_mcspi_setup(struct spi_device *spi)
return ret;
}
if (omap2_mcspi_enable_clocks(mcspi))
return -ENODEV;
ret = omap2_mcspi_enable_clocks(mcspi);
if (ret < 0)
return ret;
ret = omap2_mcspi_setup_transfer(spi, NULL);
omap2_mcspi_disable_clocks(mcspi);
@ -863,10 +844,11 @@ static void omap2_mcspi_work(struct work_struct *work)
struct omap2_mcspi *mcspi;
mcspi = container_of(work, struct omap2_mcspi, work);
spin_lock_irq(&mcspi->lock);
if (omap2_mcspi_enable_clocks(mcspi))
goto out;
if (omap2_mcspi_enable_clocks(mcspi) < 0)
return;
spin_lock_irq(&mcspi->lock);
/* We only enable one channel at a time -- the one whose message is
* at the head of the queue -- although this controller would gladly
@ -979,10 +961,9 @@ static void omap2_mcspi_work(struct work_struct *work)
spin_lock_irq(&mcspi->lock);
}
omap2_mcspi_disable_clocks(mcspi);
out:
spin_unlock_irq(&mcspi->lock);
omap2_mcspi_disable_clocks(mcspi);
}
static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
@ -1058,25 +1039,15 @@ static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
return 0;
}
static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
{
struct spi_master *master = mcspi->master;
u32 tmp;
int ret = 0;
if (omap2_mcspi_enable_clocks(mcspi))
return -1;
mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
do {
tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
} while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
ret = omap2_mcspi_enable_clocks(mcspi);
if (ret < 0)
return ret;
tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
@ -1087,91 +1058,26 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
return 0;
}
static u8 __initdata spi1_rxdma_id [] = {
OMAP24XX_DMA_SPI1_RX0,
OMAP24XX_DMA_SPI1_RX1,
OMAP24XX_DMA_SPI1_RX2,
OMAP24XX_DMA_SPI1_RX3,
};
static int omap_mcspi_runtime_resume(struct device *dev)
{
struct omap2_mcspi *mcspi;
struct spi_master *master;
static u8 __initdata spi1_txdma_id [] = {
OMAP24XX_DMA_SPI1_TX0,
OMAP24XX_DMA_SPI1_TX1,
OMAP24XX_DMA_SPI1_TX2,
OMAP24XX_DMA_SPI1_TX3,
};
master = dev_get_drvdata(dev);
mcspi = spi_master_get_devdata(master);
omap2_mcspi_restore_ctx(mcspi);
static u8 __initdata spi2_rxdma_id[] = {
OMAP24XX_DMA_SPI2_RX0,
OMAP24XX_DMA_SPI2_RX1,
};
return 0;
}
static u8 __initdata spi2_txdma_id[] = {
OMAP24XX_DMA_SPI2_TX0,
OMAP24XX_DMA_SPI2_TX1,
};
#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
|| defined(CONFIG_ARCH_OMAP4)
static u8 __initdata spi3_rxdma_id[] = {
OMAP24XX_DMA_SPI3_RX0,
OMAP24XX_DMA_SPI3_RX1,
};
static u8 __initdata spi3_txdma_id[] = {
OMAP24XX_DMA_SPI3_TX0,
OMAP24XX_DMA_SPI3_TX1,
};
#endif
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
static u8 __initdata spi4_rxdma_id[] = {
OMAP34XX_DMA_SPI4_RX0,
};
static u8 __initdata spi4_txdma_id[] = {
OMAP34XX_DMA_SPI4_TX0,
};
#endif
static int __init omap2_mcspi_probe(struct platform_device *pdev)
{
struct spi_master *master;
struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data;
struct omap2_mcspi *mcspi;
struct resource *r;
int status = 0, i;
const u8 *rxdma_id, *txdma_id;
unsigned num_chipselect;
switch (pdev->id) {
case 1:
rxdma_id = spi1_rxdma_id;
txdma_id = spi1_txdma_id;
num_chipselect = 4;
break;
case 2:
rxdma_id = spi2_rxdma_id;
txdma_id = spi2_txdma_id;
num_chipselect = 2;
break;
#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
|| defined(CONFIG_ARCH_OMAP4)
case 3:
rxdma_id = spi3_rxdma_id;
txdma_id = spi3_txdma_id;
num_chipselect = 2;
break;
#endif
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
case 4:
rxdma_id = spi4_rxdma_id;
txdma_id = spi4_txdma_id;
num_chipselect = 1;
break;
#endif
default:
return -EINVAL;
}
master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
if (master == NULL) {
@ -1188,7 +1094,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
master->setup = omap2_mcspi_setup;
master->transfer = omap2_mcspi_transfer;
master->cleanup = omap2_mcspi_cleanup;
master->num_chipselect = num_chipselect;
master->num_chipselect = pdata->num_cs;
dev_set_drvdata(&pdev->dev, master);
@ -1206,49 +1112,62 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
goto err1;
}
r->start += pdata->regs_offset;
r->end += pdata->regs_offset;
mcspi->phys = r->start;
mcspi->base = ioremap(r->start, r->end - r->start + 1);
if (!mcspi->base) {
dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
status = -ENOMEM;
goto err1aa;
goto err2;
}
mcspi->dev = &pdev->dev;
INIT_WORK(&mcspi->work, omap2_mcspi_work);
spin_lock_init(&mcspi->lock);
INIT_LIST_HEAD(&mcspi->msg_queue);
INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
mcspi->ick = clk_get(&pdev->dev, "ick");
if (IS_ERR(mcspi->ick)) {
dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
status = PTR_ERR(mcspi->ick);
goto err1a;
}
mcspi->fck = clk_get(&pdev->dev, "fck");
if (IS_ERR(mcspi->fck)) {
dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
status = PTR_ERR(mcspi->fck);
goto err2;
}
mcspi->dma_channels = kcalloc(master->num_chipselect,
sizeof(struct omap2_mcspi_dma),
GFP_KERNEL);
if (mcspi->dma_channels == NULL)
goto err3;
goto err2;
for (i = 0; i < master->num_chipselect; i++) {
char dma_ch_name[14];
struct resource *dma_res;
sprintf(dma_ch_name, "rx%d", i);
dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
dma_ch_name);
if (!dma_res) {
dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
status = -ENODEV;
break;
}
for (i = 0; i < num_chipselect; i++) {
mcspi->dma_channels[i].dma_rx_channel = -1;
mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
sprintf(dma_ch_name, "tx%d", i);
dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
dma_ch_name);
if (!dma_res) {
dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
status = -ENODEV;
break;
}
mcspi->dma_channels[i].dma_tx_channel = -1;
mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
}
if (omap2_mcspi_reset(mcspi) < 0)
goto err4;
pm_runtime_enable(&pdev->dev);
if (status || omap2_mcspi_master_setup(mcspi) < 0)
goto err3;
status = spi_register_master(master);
if (status < 0)
@ -1257,17 +1176,13 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
return status;
err4:
kfree(mcspi->dma_channels);
err3:
clk_put(mcspi->fck);
err2:
clk_put(mcspi->ick);
err1a:
iounmap(mcspi->base);
err1aa:
release_mem_region(r->start, (r->end - r->start) + 1);
err1:
spi_master_put(master);
err3:
kfree(mcspi->dma_channels);
err2:
release_mem_region(r->start, (r->end - r->start) + 1);
iounmap(mcspi->base);
err1:
return status;
}
@ -1283,9 +1198,7 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
mcspi = spi_master_get_devdata(master);
dma_channels = mcspi->dma_channels;
clk_put(mcspi->fck);
clk_put(mcspi->ick);
omap2_mcspi_disable_clocks(mcspi);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(r->start, (r->end - r->start) + 1);
@ -1336,6 +1249,7 @@ static int omap2_mcspi_resume(struct device *dev)
static const struct dev_pm_ops omap2_mcspi_pm_ops = {
.resume = omap2_mcspi_resume,
.runtime_resume = omap_mcspi_runtime_resume,
};
static struct platform_driver omap2_mcspi_driver = {