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drm/amdgpu: export gfx config double offchip LDS buffers (v3)

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v2: move the config struct to drm_amdgpu_info_device
v3: move the config feature to amdgpu_gca_config

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Junwei Zhang 2017-02-17 11:05:49 +08:00 committed by Alex Deucher
parent 24de75151b
commit df6e2c4aeb
6 changed files with 33 additions and 0 deletions
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3
drivers/gpu/drm/amd/amdgpu/amdgpu.h
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@ -845,6 +845,9 @@ struct amdgpu_gca_config {
uint32_t macrotile_mode_array[16]; uint32_t macrotile_mode_array[16];
struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
/* gfx configure feature */
uint32_t double_offchip_lds_buf;
}; };
struct amdgpu_cu_info { struct amdgpu_cu_info {

2
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
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@ -528,6 +528,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
dev_info.vram_type = adev->mc.vram_type; dev_info.vram_type = adev->mc.vram_type;
dev_info.vram_bit_width = adev->mc.vram_width; dev_info.vram_bit_width = adev->mc.vram_width;
dev_info.vce_harvest_config = adev->vce.harvest_config; dev_info.vce_harvest_config = adev->vce.harvest_config;
dev_info.gc_double_offchip_lds_buf =
adev->gfx.config.double_offchip_lds_buf;
return copy_to_user(out, &dev_info, return copy_to_user(out, &dev_info,
min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;

6
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
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@ -1579,6 +1579,11 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
mutex_unlock(&adev->grbm_idx_mutex); mutex_unlock(&adev->grbm_idx_mutex);
} }
static void gfx_v6_0_config_init(struct amdgpu_device *adev)
{
adev->gfx.config.double_offchip_lds_buf = 1;
}
static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
{ {
u32 gb_addr_config = 0; u32 gb_addr_config = 0;
@ -1736,6 +1741,7 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
gfx_v6_0_setup_spi(adev); gfx_v6_0_setup_spi(adev);
gfx_v6_0_get_cu_info(adev); gfx_v6_0_get_cu_info(adev);
gfx_v6_0_config_init(adev);
WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
(0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));

6
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
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@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
mutex_unlock(&adev->srbm_mutex); mutex_unlock(&adev->srbm_mutex);
} }
static void gfx_v7_0_config_init(struct amdgpu_device *adev)
{
adev->gfx.config.double_offchip_lds_buf = 1;
}
/** /**
* gfx_v7_0_gpu_init - setup the 3D engine * gfx_v7_0_gpu_init - setup the 3D engine
* *
@ -1899,6 +1904,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
gfx_v7_0_setup_rb(adev); gfx_v7_0_setup_rb(adev);
gfx_v7_0_get_cu_info(adev); gfx_v7_0_get_cu_info(adev);
gfx_v7_0_config_init(adev);
/* set HW defaults for 3D engine */ /* set HW defaults for 3D engine */
WREG32(mmCP_MEQ_THRESHOLDS, WREG32(mmCP_MEQ_THRESHOLDS,

14
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
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@ -3846,6 +3846,19 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
mutex_unlock(&adev->srbm_mutex); mutex_unlock(&adev->srbm_mutex);
} }
static void gfx_v8_0_config_init(struct amdgpu_device *adev)
{
switch (adev->asic_type) {
default:
adev->gfx.config.double_offchip_lds_buf = 1;
break;
case CHIP_CARRIZO:
case CHIP_STONEY:
adev->gfx.config.double_offchip_lds_buf = 0;
break;
}
}
static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
{ {
u32 tmp; u32 tmp;
@ -3859,6 +3872,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
gfx_v8_0_tiling_mode_table_init(adev); gfx_v8_0_tiling_mode_table_init(adev);
gfx_v8_0_setup_rb(adev); gfx_v8_0_setup_rb(adev);
gfx_v8_0_get_cu_info(adev); gfx_v8_0_get_cu_info(adev);
gfx_v8_0_config_init(adev);
/* XXX SH_MEM regs */ /* XXX SH_MEM regs */
/* where to put LDS, scratch, GPUVM in FSA64 space */ /* where to put LDS, scratch, GPUVM in FSA64 space */

2
include/uapi/drm/amdgpu_drm.h
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@ -726,6 +726,8 @@ struct drm_amdgpu_info_device {
__u32 vram_bit_width; __u32 vram_bit_width;
/* vce harvesting instance */ /* vce harvesting instance */
__u32 vce_harvest_config; __u32 vce_harvest_config;
/* gfx double offchip LDS buffers */
__u32 gc_double_offchip_lds_buf;
}; };
struct drm_amdgpu_info_hw_ip { struct drm_amdgpu_info_hw_ip {