mmc: meson-axg: add support for the Meson-AXG platform
Introduce the compatible data to cover the register offset & mask change of the eMMC controller in Amlogic's Meson-AXG SoC. Signed-off-by: Nan Li <nan.li@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Kevin Hilman <khilman@baylibre.com>
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@ -47,15 +47,29 @@
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#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
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#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
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#define CLK_TX_PHASE_MASK GENMASK(11, 10)
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#define CLK_TX_PHASE_MASK GENMASK(11, 10)
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#define CLK_RX_PHASE_MASK GENMASK(13, 12)
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#define CLK_RX_PHASE_MASK GENMASK(13, 12)
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#define CLK_TX_DELAY_MASK GENMASK(19, 16)
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#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
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#define CLK_RX_DELAY_MASK GENMASK(23, 20)
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#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
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#define CLK_V2_ALWAYS_ON BIT(24)
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#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
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#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
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#define CLK_V3_ALWAYS_ON BIT(28)
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#define CLK_DELAY_STEP_PS 200
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#define CLK_DELAY_STEP_PS 200
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#define CLK_PHASE_STEP 30
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#define CLK_PHASE_STEP 30
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#define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
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#define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
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#define CLK_ALWAYS_ON BIT(24)
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#define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)
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#define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)
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#define CLK_ALWAYS_ON(h) (h->data->always_on)
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#define SD_EMMC_DELAY 0x4
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#define SD_EMMC_DELAY 0x4
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#define SD_EMMC_ADJUST 0x8
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#define SD_EMMC_ADJUST 0x8
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#define SD_EMMC_DELAY1 0x4
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#define SD_EMMC_DELAY2 0x8
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#define SD_EMMC_V3_ADJUST 0xc
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#define SD_EMMC_CALOUT 0x10
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#define SD_EMMC_CALOUT 0x10
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#define SD_EMMC_START 0x40
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#define SD_EMMC_START 0x40
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#define START_DESC_INIT BIT(0)
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#define START_DESC_INIT BIT(0)
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@ -122,6 +136,12 @@
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#define MUX_CLK_NUM_PARENTS 2
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#define MUX_CLK_NUM_PARENTS 2
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struct meson_mmc_data {
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unsigned int tx_delay_mask;
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unsigned int rx_delay_mask;
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unsigned int always_on;
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};
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struct sd_emmc_desc {
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struct sd_emmc_desc {
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u32 cmd_cfg;
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u32 cmd_cfg;
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u32 cmd_arg;
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u32 cmd_arg;
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@ -131,6 +151,7 @@ struct sd_emmc_desc {
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struct meson_host {
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struct meson_host {
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struct device *dev;
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struct device *dev;
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struct meson_mmc_data *data;
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struct mmc_host *mmc;
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struct mmc_host *mmc;
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struct mmc_command *cmd;
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struct mmc_command *cmd;
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@ -474,7 +495,7 @@ static int meson_mmc_clk_init(struct meson_host *host)
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/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
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/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
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clk_reg = 0;
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clk_reg = 0;
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clk_reg |= CLK_ALWAYS_ON;
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clk_reg |= CLK_ALWAYS_ON(host);
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clk_reg |= CLK_DIV_MASK;
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clk_reg |= CLK_DIV_MASK;
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writel(clk_reg, host->regs + SD_EMMC_CLOCK);
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writel(clk_reg, host->regs + SD_EMMC_CLOCK);
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@ -574,7 +595,7 @@ static int meson_mmc_clk_init(struct meson_host *host)
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tx->reg = host->regs + SD_EMMC_CLOCK;
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tx->reg = host->regs + SD_EMMC_CLOCK;
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tx->phase_mask = CLK_TX_PHASE_MASK;
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tx->phase_mask = CLK_TX_PHASE_MASK;
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tx->delay_mask = CLK_TX_DELAY_MASK;
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tx->delay_mask = CLK_TX_DELAY_MASK(host);
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tx->delay_step_ps = CLK_DELAY_STEP_PS;
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tx->delay_step_ps = CLK_DELAY_STEP_PS;
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tx->hw.init = &init;
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tx->hw.init = &init;
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@ -597,7 +618,7 @@ static int meson_mmc_clk_init(struct meson_host *host)
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rx->reg = host->regs + SD_EMMC_CLOCK;
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rx->reg = host->regs + SD_EMMC_CLOCK;
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rx->phase_mask = CLK_RX_PHASE_MASK;
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rx->phase_mask = CLK_RX_PHASE_MASK;
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rx->delay_mask = CLK_RX_DELAY_MASK;
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rx->delay_mask = CLK_RX_DELAY_MASK(host);
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rx->delay_step_ps = CLK_DELAY_STEP_PS;
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rx->delay_step_ps = CLK_DELAY_STEP_PS;
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rx->hw.init = &init;
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rx->hw.init = &init;
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@ -1184,6 +1205,13 @@ static int meson_mmc_probe(struct platform_device *pdev)
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goto free_host;
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goto free_host;
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}
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}
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host->data = (struct meson_mmc_data *)
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of_device_get_match_data(&pdev->dev);
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if (!host->data) {
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ret = -EINVAL;
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goto free_host;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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host->regs = devm_ioremap_resource(&pdev->dev, res);
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host->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(host->regs)) {
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if (IS_ERR(host->regs)) {
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@ -1315,11 +1343,24 @@ static int meson_mmc_remove(struct platform_device *pdev)
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return 0;
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return 0;
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}
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}
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static const struct meson_mmc_data meson_gx_data = {
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.tx_delay_mask = CLK_V2_TX_DELAY_MASK,
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.rx_delay_mask = CLK_V2_RX_DELAY_MASK,
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.always_on = CLK_V2_ALWAYS_ON,
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};
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static const struct meson_mmc_data meson_axg_data = {
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.tx_delay_mask = CLK_V3_TX_DELAY_MASK,
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.rx_delay_mask = CLK_V3_RX_DELAY_MASK,
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.always_on = CLK_V3_ALWAYS_ON,
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};
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static const struct of_device_id meson_mmc_of_match[] = {
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static const struct of_device_id meson_mmc_of_match[] = {
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{ .compatible = "amlogic,meson-gx-mmc", },
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{ .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data },
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{ .compatible = "amlogic,meson-gxbb-mmc", },
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{ .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data },
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{ .compatible = "amlogic,meson-gxl-mmc", },
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{ .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data },
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{ .compatible = "amlogic,meson-gxm-mmc", },
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{ .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data },
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{ .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data },
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{}
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{}
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};
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};
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MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
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MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
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