forked from Minki/linux
omap_hwmod: share identical omap_hwmod_addr_space arrays
To reduce kernel source file data duplication, share struct omap_hwmod_addr_space arrays across OMAP2xxx and 3xxx hwmod data files. Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Paul Walmsley
parent
78183f3fdf
commit
ded11383fc
@ -145,9 +145,14 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
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obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
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# hwmod data
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obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o
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obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
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obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
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obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o \
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omap_hwmod_2xxx_3xxx_interconnect_data.o \
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omap_hwmod_2420_data.o
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obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o \
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omap_hwmod_2xxx_3xxx_interconnect_data.o \
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omap_hwmod_2430_data.o
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obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o \
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omap_hwmod_3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
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# EMU peripherals
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@ -114,38 +114,20 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod;
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static struct omap_hwmod omap2420_mcbsp2_hwmod;
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/* l4 core -> mcspi1 interface */
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static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
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{
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.pa_start = 0x48098000,
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.pa_end = 0x480980ff,
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.flags = ADDR_TYPE_RT,
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},
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{ }
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};
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static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_mcspi1_hwmod,
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.clk = "mcspi1_ick",
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.addr = omap2420_mcspi1_addr_space,
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.addr = omap2_mcspi1_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4 core -> mcspi2 interface */
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static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
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{
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.pa_start = 0x4809a000,
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.pa_end = 0x4809a0ff,
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.flags = ADDR_TYPE_RT,
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},
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{ }
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};
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static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_mcspi2_hwmod,
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.clk = "mcspi2_ick",
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.addr = omap2420_mcspi2_addr_space,
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.addr = omap2_mcspi2_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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@ -157,95 +139,47 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
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};
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/* L4 CORE -> UART1 interface */
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static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
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{
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.pa_start = OMAP2_UART1_BASE,
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.pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
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.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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},
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{ }
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};
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static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_uart1_hwmod,
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.clk = "uart1_ick",
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.addr = omap2420_uart1_addr_space,
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.addr = omap2xxx_uart1_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> UART2 interface */
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static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
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{
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.pa_start = OMAP2_UART2_BASE,
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.pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
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.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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},
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{ }
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};
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static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_uart2_hwmod,
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.clk = "uart2_ick",
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.addr = omap2420_uart2_addr_space,
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.addr = omap2xxx_uart2_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 PER -> UART3 interface */
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static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
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{
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.pa_start = OMAP2_UART3_BASE,
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.pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
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.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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},
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{ }
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};
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static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_uart3_hwmod,
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.clk = "uart3_ick",
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.addr = omap2420_uart3_addr_space,
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.addr = omap2xxx_uart3_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* I2C IP block address space length (in bytes) */
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#define OMAP2_I2C_AS_LEN 128
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/* L4 CORE -> I2C1 interface */
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static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
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{
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.pa_start = 0x48070000,
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.pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
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.flags = ADDR_TYPE_RT,
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},
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{ }
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};
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static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_i2c1_hwmod,
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.clk = "i2c1_ick",
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.addr = omap2420_i2c1_addr_space,
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.addr = omap2_i2c1_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> I2C2 interface */
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static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
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{
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.pa_start = 0x48072000,
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.pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
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.flags = ADDR_TYPE_RT,
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},
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{ }
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};
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static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_i2c2_hwmod,
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.clk = "i2c2_ick",
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.addr = omap2420_i2c2_addr_space,
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.addr = omap2_i2c2_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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@ -414,21 +348,13 @@ static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
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{ .irq = 38, },
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};
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static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
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{
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.pa_start = 0x4802a000,
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.pa_end = 0x4802a000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_core -> timer2 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer2_hwmod,
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.clk = "gpt2_ick",
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.addr = omap2420_timer2_addrs,
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.addr = omap2xxx_timer2_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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@ -464,21 +390,12 @@ static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
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{ .irq = 39, },
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};
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static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
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{
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.pa_start = 0x48078000,
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.pa_end = 0x48078000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_core -> timer3 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer3_hwmod,
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.clk = "gpt3_ick",
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.addr = omap2420_timer3_addrs,
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.addr = omap2xxx_timer3_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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@ -514,21 +431,12 @@ static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
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{ .irq = 40, },
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};
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static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
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{
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.pa_start = 0x4807a000,
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.pa_end = 0x4807a000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_core -> timer4 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer4_hwmod,
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.clk = "gpt4_ick",
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.addr = omap2420_timer4_addrs,
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.addr = omap2xxx_timer4_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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@ -564,21 +472,12 @@ static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
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{ .irq = 41, },
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};
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static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
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{
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.pa_start = 0x4807c000,
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.pa_end = 0x4807c000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_core -> timer5 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer5_hwmod,
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.clk = "gpt5_ick",
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.addr = omap2420_timer5_addrs,
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.addr = omap2xxx_timer5_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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@ -615,21 +514,12 @@ static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
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{ .irq = 42, },
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};
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static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
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{
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.pa_start = 0x4807e000,
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.pa_end = 0x4807e000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_core -> timer6 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer6_hwmod,
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.clk = "gpt6_ick",
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.addr = omap2420_timer6_addrs,
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.addr = omap2xxx_timer6_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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@ -665,21 +555,12 @@ static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
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{ .irq = 43, },
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};
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static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
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{
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.pa_start = 0x48080000,
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.pa_end = 0x48080000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_core -> timer7 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer7_hwmod,
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.clk = "gpt7_ick",
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.addr = omap2420_timer7_addrs,
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.addr = omap2xxx_timer7_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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@ -715,21 +596,12 @@ static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
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{ .irq = 44, },
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};
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static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
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{
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.pa_start = 0x48082000,
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.pa_end = 0x48082000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_core -> timer8 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer8_hwmod,
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.clk = "gpt8_ick",
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.addr = omap2420_timer8_addrs,
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.addr = omap2xxx_timer8_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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@ -765,21 +637,12 @@ static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
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{ .irq = 45, },
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};
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static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
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{
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.pa_start = 0x48084000,
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.pa_end = 0x48084000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_core -> timer9 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer9_hwmod,
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.clk = "gpt9_ick",
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.addr = omap2420_timer9_addrs,
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.addr = omap2xxx_timer9_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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@ -815,21 +678,12 @@ static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
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{ .irq = 46, },
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};
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static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
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{
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.pa_start = 0x48086000,
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.pa_end = 0x48086000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_core -> timer10 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer10_hwmod,
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.clk = "gpt10_ick",
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.addr = omap2420_timer10_addrs,
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.addr = omap2_timer10_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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@ -865,21 +719,12 @@ static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
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{ .irq = 47, },
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};
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static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
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{
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.pa_start = 0x48088000,
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.pa_end = 0x48088000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_core -> timer11 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer11_hwmod,
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.clk = "gpt11_ick",
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.addr = omap2420_timer11_addrs,
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.addr = omap2_timer11_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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@ -915,21 +760,12 @@ static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
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{ .irq = 48, },
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};
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static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
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{
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.pa_start = 0x4808a000,
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.pa_end = 0x4808a000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_core -> timer12 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_timer12_hwmod,
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.clk = "gpt12_ick",
|
||||
.addr = omap2420_timer12_addrs,
|
||||
.addr = omap2xxx_timer12_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -1178,21 +1014,12 @@ static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
|
||||
&omap2420_dss__l3,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050000,
|
||||
.pa_end = 0x480503FF,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> dss */
|
||||
static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
|
||||
.master = &omap2420_l4_core_hwmod,
|
||||
.slave = &omap2420_dss_core_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap2420_dss_addrs,
|
||||
.addr = omap2_dss_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
|
||||
@ -1262,21 +1089,12 @@ static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = {
|
||||
{ .irq = 25 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050400,
|
||||
.pa_end = 0x480507FF,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> dss_dispc */
|
||||
static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
|
||||
.master = &omap2420_l4_core_hwmod,
|
||||
.slave = &omap2420_dss_dispc_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap2420_dss_dispc_addrs,
|
||||
.addr = omap2_dss_dispc_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
|
||||
@ -1332,21 +1150,12 @@ static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
|
||||
.sysc = &omap2420_rfbi_sysc,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050800,
|
||||
.pa_end = 0x48050BFF,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> dss_rfbi */
|
||||
static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
|
||||
.master = &omap2420_l4_core_hwmod,
|
||||
.slave = &omap2420_dss_rfbi_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap2420_dss_rfbi_addrs,
|
||||
.addr = omap2_dss_rfbi_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
|
||||
@ -1387,22 +1196,12 @@ static struct omap_hwmod_class omap2420_venc_hwmod_class = {
|
||||
.name = "venc",
|
||||
};
|
||||
|
||||
/* dss_venc */
|
||||
static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050C00,
|
||||
.pa_end = 0x48050FFF,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> dss_venc */
|
||||
static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
|
||||
.master = &omap2420_l4_core_hwmod,
|
||||
.slave = &omap2420_dss_venc_hwmod,
|
||||
.clk = "dss_54m_fck",
|
||||
.addr = omap2420_dss_venc_addrs,
|
||||
.addr = omap2_dss_venc_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
|
||||
@ -1783,15 +1582,6 @@ static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
|
||||
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48056000,
|
||||
.pa_end = 0x48056fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* dma_system -> L3 */
|
||||
static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
|
||||
.master = &omap2420_dma_system_hwmod,
|
||||
@ -1810,7 +1600,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
|
||||
.master = &omap2420_l4_core_hwmod,
|
||||
.slave = &omap2420_dma_system_hwmod,
|
||||
.clk = "sdma_ick",
|
||||
.addr = omap2420_dma_system_addrs,
|
||||
.addr = omap2_dma_system_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -1862,20 +1652,11 @@ static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
|
||||
{ .name = "iva", .irq = 34 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48094000,
|
||||
.pa_end = 0x480941ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> mailbox */
|
||||
static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
|
||||
.master = &omap2420_l4_core_hwmod,
|
||||
.slave = &omap2420_mailbox_hwmod,
|
||||
.addr = omap2420_mailbox_addrs,
|
||||
.addr = omap2_mailbox_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -2037,22 +1818,12 @@ static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
|
||||
{ .name = "tx", .dma_req = 31 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
|
||||
{
|
||||
.name = "mpu",
|
||||
.pa_start = 0x48074000,
|
||||
.pa_end = 0x480740ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> mcbsp1 */
|
||||
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
|
||||
.master = &omap2420_l4_core_hwmod,
|
||||
.slave = &omap2420_mcbsp1_hwmod,
|
||||
.clk = "mcbsp1_ick",
|
||||
.addr = omap2420_mcbsp1_addrs,
|
||||
.addr = omap2_mcbsp1_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -2094,22 +1865,12 @@ static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
|
||||
{ .name = "tx", .dma_req = 33 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
|
||||
{
|
||||
.name = "mpu",
|
||||
.pa_start = 0x48076000,
|
||||
.pa_end = 0x480760ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> mcbsp2 */
|
||||
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
|
||||
.master = &omap2420_l4_core_hwmod,
|
||||
.slave = &omap2420_mcbsp2_hwmod,
|
||||
.clk = "mcbsp2_ick",
|
||||
.addr = omap2420_mcbsp2_addrs,
|
||||
.addr = omap2xxx_mcbsp2_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
||||
@ -131,42 +131,21 @@ static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* I2C IP block address space length (in bytes) */
|
||||
#define OMAP2_I2C_AS_LEN 128
|
||||
|
||||
/* L4 CORE -> I2C1 interface */
|
||||
static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48070000,
|
||||
.pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_i2c1_hwmod,
|
||||
.clk = "i2c1_ick",
|
||||
.addr = omap2430_i2c1_addr_space,
|
||||
.addr = omap2_i2c1_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* L4 CORE -> I2C2 interface */
|
||||
static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48072000,
|
||||
.pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_i2c2_hwmod,
|
||||
.clk = "i2c2_ick",
|
||||
.addr = omap2430_i2c2_addr_space,
|
||||
.addr = omap2_i2c2_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -178,56 +157,29 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
|
||||
};
|
||||
|
||||
/* L4 CORE -> UART1 interface */
|
||||
static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP2_UART1_BASE,
|
||||
.pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
|
||||
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_uart1_hwmod,
|
||||
.clk = "uart1_ick",
|
||||
.addr = omap2430_uart1_addr_space,
|
||||
.addr = omap2xxx_uart1_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* L4 CORE -> UART2 interface */
|
||||
static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP2_UART2_BASE,
|
||||
.pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
|
||||
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_uart2_hwmod,
|
||||
.clk = "uart2_ick",
|
||||
.addr = omap2430_uart2_addr_space,
|
||||
.addr = omap2xxx_uart2_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* L4 PER -> UART3 interface */
|
||||
static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP2_UART3_BASE,
|
||||
.pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
|
||||
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_uart3_hwmod,
|
||||
.clk = "uart3_ick",
|
||||
.addr = omap2430_uart3_addr_space,
|
||||
.addr = omap2xxx_uart3_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -260,15 +212,6 @@ static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
|
||||
};
|
||||
|
||||
/* L4 CORE -> MMC1 interface */
|
||||
static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x4809c000,
|
||||
.pa_end = 0x4809c1ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_mmc1_hwmod,
|
||||
@ -278,15 +221,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
|
||||
};
|
||||
|
||||
/* L4 CORE -> MMC2 interface */
|
||||
static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x480b4000,
|
||||
.pa_end = 0x480b41ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_mmc2_hwmod,
|
||||
@ -332,51 +266,24 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
|
||||
};
|
||||
|
||||
/* l4 core -> mcspi1 interface */
|
||||
static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48098000,
|
||||
.pa_end = 0x480980ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_mcspi1_hwmod,
|
||||
.clk = "mcspi1_ick",
|
||||
.addr = omap2430_mcspi1_addr_space,
|
||||
.addr = omap2_mcspi1_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4 core -> mcspi2 interface */
|
||||
static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x4809a000,
|
||||
.pa_end = 0x4809a0ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_mcspi2_hwmod,
|
||||
.clk = "mcspi2_ick",
|
||||
.addr = omap2430_mcspi2_addr_space,
|
||||
.addr = omap2_mcspi2_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4 core -> mcspi3 interface */
|
||||
static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x480b8000,
|
||||
.pa_end = 0x480b80ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_mcspi3_hwmod,
|
||||
@ -514,21 +421,12 @@ static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
|
||||
{ .irq = 38, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4802a000,
|
||||
.pa_end = 0x4802a000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> timer2 */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_timer2_hwmod,
|
||||
.clk = "gpt2_ick",
|
||||
.addr = omap2430_timer2_addrs,
|
||||
.addr = omap2xxx_timer2_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -564,21 +462,12 @@ static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
|
||||
{ .irq = 39, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48078000,
|
||||
.pa_end = 0x48078000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> timer3 */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_timer3_hwmod,
|
||||
.clk = "gpt3_ick",
|
||||
.addr = omap2430_timer3_addrs,
|
||||
.addr = omap2xxx_timer3_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -614,21 +503,12 @@ static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
|
||||
{ .irq = 40, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4807a000,
|
||||
.pa_end = 0x4807a000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> timer4 */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_timer4_hwmod,
|
||||
.clk = "gpt4_ick",
|
||||
.addr = omap2430_timer4_addrs,
|
||||
.addr = omap2xxx_timer4_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -664,21 +544,12 @@ static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
|
||||
{ .irq = 41, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4807c000,
|
||||
.pa_end = 0x4807c000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> timer5 */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_timer5_hwmod,
|
||||
.clk = "gpt5_ick",
|
||||
.addr = omap2430_timer5_addrs,
|
||||
.addr = omap2xxx_timer5_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -714,21 +585,12 @@ static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
|
||||
{ .irq = 42, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4807e000,
|
||||
.pa_end = 0x4807e000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> timer6 */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_timer6_hwmod,
|
||||
.clk = "gpt6_ick",
|
||||
.addr = omap2430_timer6_addrs,
|
||||
.addr = omap2xxx_timer6_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -764,21 +626,12 @@ static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
|
||||
{ .irq = 43, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48080000,
|
||||
.pa_end = 0x48080000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> timer7 */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_timer7_hwmod,
|
||||
.clk = "gpt7_ick",
|
||||
.addr = omap2430_timer7_addrs,
|
||||
.addr = omap2xxx_timer7_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -814,21 +667,12 @@ static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
|
||||
{ .irq = 44, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48082000,
|
||||
.pa_end = 0x48082000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> timer8 */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_timer8_hwmod,
|
||||
.clk = "gpt8_ick",
|
||||
.addr = omap2430_timer8_addrs,
|
||||
.addr = omap2xxx_timer8_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -864,21 +708,12 @@ static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
|
||||
{ .irq = 45, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48084000,
|
||||
.pa_end = 0x48084000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> timer9 */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_timer9_hwmod,
|
||||
.clk = "gpt9_ick",
|
||||
.addr = omap2430_timer9_addrs,
|
||||
.addr = omap2xxx_timer9_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -914,21 +749,12 @@ static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
|
||||
{ .irq = 46, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48086000,
|
||||
.pa_end = 0x48086000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> timer10 */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_timer10_hwmod,
|
||||
.clk = "gpt10_ick",
|
||||
.addr = omap2430_timer10_addrs,
|
||||
.addr = omap2_timer10_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -964,21 +790,12 @@ static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
|
||||
{ .irq = 47, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48088000,
|
||||
.pa_end = 0x48088000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> timer11 */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_timer11_hwmod,
|
||||
.clk = "gpt11_ick",
|
||||
.addr = omap2430_timer11_addrs,
|
||||
.addr = omap2_timer11_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -1014,21 +831,12 @@ static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
|
||||
{ .irq = 48, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4808a000,
|
||||
.pa_end = 0x4808a000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> timer12 */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_timer12_hwmod,
|
||||
.clk = "gpt12_ick",
|
||||
.addr = omap2430_timer12_addrs,
|
||||
.addr = omap2xxx_timer12_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -1277,21 +1085,12 @@ static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
|
||||
&omap2430_dss__l3,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050000,
|
||||
.pa_end = 0x480503FF,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> dss */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_dss_core_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap2430_dss_addrs,
|
||||
.addr = omap2_dss_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -1355,21 +1154,12 @@ static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = {
|
||||
{ .irq = 25 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050400,
|
||||
.pa_end = 0x480507FF,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> dss_dispc */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_dss_dispc_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap2430_dss_dispc_addrs,
|
||||
.addr = omap2_dss_dispc_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -1419,21 +1209,12 @@ static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
|
||||
.sysc = &omap2430_rfbi_sysc,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050800,
|
||||
.pa_end = 0x48050BFF,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> dss_rfbi */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_dss_rfbi_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap2430_dss_rfbi_addrs,
|
||||
.addr = omap2_dss_rfbi_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -1468,22 +1249,12 @@ static struct omap_hwmod_class omap2430_venc_hwmod_class = {
|
||||
.name = "venc",
|
||||
};
|
||||
|
||||
/* dss_venc */
|
||||
static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050C00,
|
||||
.pa_end = 0x48050FFF,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> dss_venc */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_dss_venc_hwmod,
|
||||
.clk = "dss_54m_fck",
|
||||
.addr = omap2430_dss_venc_addrs,
|
||||
.addr = omap2_dss_venc_addrs,
|
||||
.flags = OCPIF_SWSUP_IDLE,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
@ -1916,15 +1687,6 @@ static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
|
||||
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48056000,
|
||||
.pa_end = 0x48056fff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* dma_system -> L3 */
|
||||
static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
|
||||
.master = &omap2430_dma_system_hwmod,
|
||||
@ -1943,7 +1705,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_dma_system_hwmod,
|
||||
.clk = "sdma_ick",
|
||||
.addr = omap2430_dma_system_addrs,
|
||||
.addr = omap2_dma_system_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -1994,20 +1756,11 @@ static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
|
||||
{ .irq = 26 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48094000,
|
||||
.pa_end = 0x480941ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> mailbox */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_mailbox_hwmod,
|
||||
.addr = omap2430_mailbox_addrs,
|
||||
.addr = omap2_mailbox_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -2279,22 +2032,12 @@ static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
|
||||
{ .name = "tx", .dma_req = 31 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
|
||||
{
|
||||
.name = "mpu",
|
||||
.pa_start = 0x48074000,
|
||||
.pa_end = 0x480740ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> mcbsp1 */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_mcbsp1_hwmod,
|
||||
.clk = "mcbsp1_ick",
|
||||
.addr = omap2430_mcbsp1_addrs,
|
||||
.addr = omap2_mcbsp1_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -2337,22 +2080,12 @@ static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
|
||||
{ .name = "tx", .dma_req = 33 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
|
||||
{
|
||||
.name = "mpu",
|
||||
.pa_start = 0x48076000,
|
||||
.pa_end = 0x480760ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> mcbsp2 */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_mcbsp2_hwmod,
|
||||
.clk = "mcbsp2_ick",
|
||||
.addr = omap2430_mcbsp2_addrs,
|
||||
.addr = omap2xxx_mcbsp2_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
||||
173
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
Normal file
173
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
Normal file
@ -0,0 +1,173 @@
|
||||
/*
|
||||
* omap_hwmod_2xxx_3xxx_interconnect_data.c - common interconnect data, OMAP2/3
|
||||
*
|
||||
* Copyright (C) 2009-2011 Nokia Corporation
|
||||
* Paul Walmsley
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* XXX handle crossbar/shared link difference for L3?
|
||||
* XXX these should be marked initdata for multi-OMAP kernels
|
||||
*/
|
||||
#include <asm/sizes.h>
|
||||
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/serial.h>
|
||||
|
||||
#include "omap_hwmod_common_data.h"
|
||||
|
||||
struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x4809c000,
|
||||
.pa_end = 0x4809c1ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x480b4000,
|
||||
.pa_end = 0x480b41ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_i2c1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48070000,
|
||||
.pa_end = 0x48070000 + SZ_128 - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_i2c2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48072000,
|
||||
.pa_end = 0x48072000 + SZ_128 - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_dss_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050000,
|
||||
.pa_end = 0x48050000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_dss_dispc_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050400,
|
||||
.pa_end = 0x48050400 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050800,
|
||||
.pa_end = 0x48050800 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_dss_venc_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050C00,
|
||||
.pa_end = 0x48050C00 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_timer10_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48086000,
|
||||
.pa_end = 0x48086000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_timer11_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48088000,
|
||||
.pa_end = 0x48088000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer12_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4808a000,
|
||||
.pa_end = 0x4808a000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_mcspi1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48098000,
|
||||
.pa_end = 0x48098000 + SZ_256 - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_mcspi2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x4809a000,
|
||||
.pa_end = 0x4809a000 + SZ_256 - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x480b8000,
|
||||
.pa_end = 0x480b8000 + SZ_256 - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48056000,
|
||||
.pa_end = 0x48056000 + SZ_4K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_mailbox_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48094000,
|
||||
.pa_end = 0x48094000 + SZ_512 - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
|
||||
{
|
||||
.name = "mpu",
|
||||
.pa_start = 0x48074000,
|
||||
.pa_end = 0x480740ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
130
arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
Normal file
130
arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
Normal file
@ -0,0 +1,130 @@
|
||||
/*
|
||||
* omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
|
||||
*
|
||||
* Copyright (C) 2009-2011 Nokia Corporation
|
||||
* Paul Walmsley
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* XXX handle crossbar/shared link difference for L3?
|
||||
* XXX these should be marked initdata for multi-OMAP kernels
|
||||
*/
|
||||
#include <asm/sizes.h>
|
||||
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/serial.h>
|
||||
|
||||
#include "omap_hwmod_common_data.h"
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP2_UART1_BASE,
|
||||
.pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
|
||||
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP2_UART2_BASE,
|
||||
.pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
|
||||
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP2_UART3_BASE,
|
||||
.pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
|
||||
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4802a000,
|
||||
.pa_end = 0x4802a000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48078000,
|
||||
.pa_end = 0x48078000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4807a000,
|
||||
.pa_end = 0x4807a000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4807c000,
|
||||
.pa_end = 0x4807c000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4807e000,
|
||||
.pa_end = 0x4807e000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48080000,
|
||||
.pa_end = 0x48080000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48082000,
|
||||
.pa_end = 0x48082000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48084000,
|
||||
.pa_end = 0x48084000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
|
||||
{
|
||||
.name = "mpu",
|
||||
.pa_start = 0x48076000,
|
||||
.pa_end = 0x480760ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
|
||||
@ -190,39 +190,21 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
|
||||
};
|
||||
|
||||
/* L4 CORE -> MMC1 interface */
|
||||
static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x4809c000,
|
||||
.pa_end = 0x4809c1ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3xxx_mmc1_hwmod,
|
||||
.clk = "mmchs1_ick",
|
||||
.addr = omap3xxx_mmc1_addr_space,
|
||||
.addr = omap2430_mmc1_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
.flags = OMAP_FIREWALL_L4
|
||||
};
|
||||
|
||||
/* L4 CORE -> MMC2 interface */
|
||||
static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x480b4000,
|
||||
.pa_end = 0x480b41ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3xxx_mmc2_hwmod,
|
||||
.clk = "mmchs2_ick",
|
||||
.addr = omap3xxx_mmc2_addr_space,
|
||||
.addr = omap2430_mmc2_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
.flags = OMAP_FIREWALL_L4
|
||||
};
|
||||
@ -318,24 +300,12 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* I2C IP block address space length (in bytes) */
|
||||
#define OMAP2_I2C_AS_LEN 128
|
||||
|
||||
/* L4 CORE -> I2C1 interface */
|
||||
static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48070000,
|
||||
.pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3xxx_i2c1_hwmod,
|
||||
.clk = "i2c1_ick",
|
||||
.addr = omap3xxx_i2c1_addr_space,
|
||||
.addr = omap2_i2c1_addr_space,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
|
||||
@ -347,20 +317,11 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
|
||||
};
|
||||
|
||||
/* L4 CORE -> I2C2 interface */
|
||||
static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48072000,
|
||||
.pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3xxx_i2c2_hwmod,
|
||||
.clk = "i2c2_ick",
|
||||
.addr = omap3xxx_i2c2_addr_space,
|
||||
.addr = omap2_i2c2_addr_space,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
|
||||
@ -375,7 +336,7 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
|
||||
static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48060000,
|
||||
.pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
|
||||
.pa_end = 0x48060000 + SZ_128 - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
@ -1065,21 +1026,12 @@ static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
|
||||
{ .irq = 46, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48086000,
|
||||
.pa_end = 0x48086000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> timer10 */
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3xxx_timer10_hwmod,
|
||||
.clk = "gpt10_ick",
|
||||
.addr = omap3xxx_timer10_addrs,
|
||||
.addr = omap2_timer10_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -1115,21 +1067,12 @@ static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
|
||||
{ .irq = 47, },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48088000,
|
||||
.pa_end = 0x48088000 + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> timer11 */
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3xxx_timer11_hwmod,
|
||||
.clk = "gpt11_ick",
|
||||
.addr = omap3xxx_timer11_addrs,
|
||||
.addr = omap2_timer11_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
@ -1491,21 +1434,12 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
|
||||
&omap3xxx_dss__l3,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050000,
|
||||
.pa_end = 0x480503FF,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> dss */
|
||||
static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3430es1_dss_core_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap3xxx_dss_addrs,
|
||||
.addr = omap2_dss_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
|
||||
@ -1520,7 +1454,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3xxx_dss_core_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap3xxx_dss_addrs,
|
||||
.addr = omap2_dss_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
|
||||
@ -1625,21 +1559,12 @@ static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
|
||||
{ .irq = 25 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050400,
|
||||
.pa_end = 0x480507FF,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> dss_dispc */
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3xxx_dss_dispc_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap3xxx_dss_dispc_addrs,
|
||||
.addr = omap2_dss_dispc_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
|
||||
@ -1760,21 +1685,12 @@ static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
|
||||
.sysc = &omap3xxx_rfbi_sysc,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050800,
|
||||
.pa_end = 0x48050BFF,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> dss_rfbi */
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3xxx_dss_rfbi_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap3xxx_dss_rfbi_addrs,
|
||||
.addr = omap2_dss_rfbi_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
|
||||
@ -1818,22 +1734,12 @@ static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
|
||||
.name = "venc",
|
||||
};
|
||||
|
||||
/* dss_venc */
|
||||
static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48050C00,
|
||||
.pa_end = 0x48050FFF,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/* l4_core -> dss_venc */
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3xxx_dss_venc_hwmod,
|
||||
.clk = "dss_tv_fck",
|
||||
.addr = omap3xxx_dss_venc_addrs,
|
||||
.addr = omap2_dss_venc_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
|
||||
@ -3070,56 +2976,29 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
|
||||
};
|
||||
|
||||
/* l4 core -> mcspi1 interface */
|
||||
static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x48098000,
|
||||
.pa_end = 0x480980ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap34xx_mcspi1,
|
||||
.clk = "mcspi1_ick",
|
||||
.addr = omap34xx_mcspi1_addr_space,
|
||||
.addr = omap2_mcspi1_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4 core -> mcspi2 interface */
|
||||
static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x4809a000,
|
||||
.pa_end = 0x4809a0ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap34xx_mcspi2,
|
||||
.clk = "mcspi2_ick",
|
||||
.addr = omap34xx_mcspi2_addr_space,
|
||||
.addr = omap2_mcspi2_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4 core -> mcspi3 interface */
|
||||
static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
|
||||
{
|
||||
.pa_start = 0x480b8000,
|
||||
.pa_end = 0x480b80ff,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap34xx_mcspi3,
|
||||
.clk = "mcspi3_ick",
|
||||
.addr = omap34xx_mcspi3_addr_space,
|
||||
.addr = omap2430_mcspi3_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
/*
|
||||
* omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
|
||||
*
|
||||
* Copyright (C) 2010 Nokia Corporation
|
||||
* Copyright (C) 2010-2011 Nokia Corporation
|
||||
* Paul Walmsley
|
||||
*
|
||||
* Copyright (C) 2010 Texas Instruments, Inc.
|
||||
* Copyright (C) 2010-2011 Texas Instruments, Inc.
|
||||
* Benoît Cousson
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
@ -16,10 +16,44 @@
|
||||
|
||||
#include <plat/omap_hwmod.h>
|
||||
|
||||
/* Common address space across OMAP2xxx */
|
||||
extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
|
||||
|
||||
/* Common address space across OMAP2xxx/3xxx */
|
||||
extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2_dss_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2_dss_dispc_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2_dss_venc_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2_timer10_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2_timer11_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2430_mmc1_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2430_mmc2_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
|
||||
|
||||
/* OMAP hwmod classes - forward declarations */
|
||||
extern struct omap_hwmod_class l3_hwmod_class;
|
||||
extern struct omap_hwmod_class l4_hwmod_class;
|
||||
extern struct omap_hwmod_class mpu_hwmod_class;
|
||||
extern struct omap_hwmod_class iva_hwmod_class;
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user