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Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

Browse Source 
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (124 commits)
  sh: allow building for both r2d boards in same binary.
  sh: fix r2d board detection
  sh: Discard .exit.text/.exit.data at runtime.
  sh: Fix up some section alignments in linker script.
  sh: Fix SH-4 DMAC CHCR masking.
  sh: Rip out left-over nommu cond syscall cruft.
  sh: Make kgdb i-cache flushing less inept.
  sh: kgdb section mismatches and tidying.
  sh: cleanup struct irqaction initializers.
  sh: early_printk tidying.
  video: pvr2fb: Add TV (RGB) support to Dreamcast PVR driver.
  sh: Conditionalize gUSA support.
  sh: Follow gUSA preempt changes in __switch_to().
  sh: Tidy up gUSA preempt handling.
  sh: __copy_user() optimizations for small copies.
  sh: clkfwk: Support multi-level clock propagation.
  sh: Fix URAM start address on SH7785.
  sh: Use boot_cpu_data for CPU probe.
  sh: Support extended mode TLB on SH-X3.
  sh: Bump MAX_ACTIVE_REGIONS for SH7785.
  ...
This commit is contained in:
Linus Torvalds 2007-10-13 09:49:04 -07:00
commit dcf397f037
142 changed files with 8775 additions and 3355 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
arch/sh/Kconfig
View File

@ -118,7 +118,7 @@ endchoice
config SH_FPU
bool "FPU support"
depends on CPU_SH4
depends on CPU_HAS_FPU
default y
help
Selecting this option will enable support for SH processors that
@ -178,12 +178,6 @@ config CPU_HAS_INTEVT
config CPU_HAS_MASKREG_IRQ
bool
config CPU_HAS_INTC_IRQ
bool
config CPU_HAS_INTC2_IRQ
bool
config CPU_HAS_IPR_IRQ
bool
@ -205,6 +199,9 @@ config CPU_HAS_PTEA
config CPU_HAS_DSP
bool
config CPU_HAS_FPU
bool
endmenu
menu "Board support"
@ -258,7 +255,6 @@ config SH_7780_SOLUTION_ENGINE
bool "SolutionEngine7780"
select SOLUTION_ENGINE
select SYS_SUPPORTS_PCI
select CPU_HAS_INTC2_IRQ
depends on CPU_SUBTYPE_SH7780
help
Select 7780 SolutionEngine if configuring for a Renesas SH7780
@ -309,7 +305,7 @@ config SH_MPC1211
config SH_SH03
bool "Interface CTP/PCI-SH03"
depends on CPU_SUBTYPE_SH7751 && BROKEN
depends on CPU_SUBTYPE_SH7751
select CPU_HAS_IPR_IRQ
select SYS_SUPPORTS_PCI
help
@ -395,11 +391,22 @@ config SH_LBOX_RE2
help
Select L-BOX RE2 if configuring for the NTT COMWARE L-BOX RE2.
config SH_X3PROTO
bool "SH-X3 Prototype board"
depends on CPU_SUBTYPE_SHX3
config SH_MAGIC_PANEL_R2
bool "Magic Panel R2"
depends on CPU_SUBTYPE_SH7720
help
Select Magic Panel R2 if configuring for Magic Panel R2.
endmenu
source "arch/sh/boards/renesas/hs7751rvoip/Kconfig"
source "arch/sh/boards/renesas/rts7751r2d/Kconfig"
source "arch/sh/boards/renesas/r7780rp/Kconfig"
source "arch/sh/boards/magicpanelr2/Kconfig"
menu "Timer and clock configuration"
@ -563,10 +570,19 @@ config NR_CPUS
source "kernel/Kconfig.preempt"
config NODES_SHIFT
int
default "1"
depends on NEED_MULTIPLE_NODES
config GUSA
def_bool y
depends on !SMP
help
This enables support for gUSA (general UserSpace Atomicity).
This is the default implementation for both UP and non-ll/sc
CPUs, and is used by the libc, amongst others.
For additional information, design information can be found
in <http://lc.linux.or.jp/lc2002/papers/niibe0919p.pdf>.
This should only be disabled for special cases where alternate
atomicity implementations exist.
endmenu
@ -659,6 +675,17 @@ config SUPERHYWAY
tristate "SuperHyway Bus support"
depends on CPU_SUBTYPE_SH4_202
config MAPLE
bool "Maple Bus support"
depends on SH_DREAMCAST
help
The Maple Bus is SEGA's serial communication bus for peripherals
on the Dreamcast. Without this bus support you won't be able to
get your Dreamcast keyboard etc to work, so most users
probably want to say 'Y' here, unless you are only using the
Dreamcast with a serial line terminal or a remote network
connection.
config CF_ENABLER
bool "Compact Flash Enabler support"
depends on SOLUTION_ENGINE || SH_SH03

6
arch/sh/Kconfig.debug
View File

@ -28,13 +28,17 @@ config EARLY_SCIF_CONSOLE
serial I/O.
config EARLY_SCIF_CONSOLE_PORT
hex "SCIF port for early console"
hex
depends on EARLY_SCIF_CONSOLE
default "0xffe00000" if CPU_SUBTYPE_SH7780
default "0xffea0000" if CPU_SUBTYPE_SH7785
default "0xfffe9800" if CPU_SUBTYPE_SH7206
default "0xf8420000" if CPU_SUBTYPE_SH7619
default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
default "0xa4430000" if CPU_SUBTYPE_SH7720
default "0xffc30000" if CPU_SUBTYPE_SHX3
default "0xffe80000" if CPU_SH4
default "0x00000000"
config EARLY_PRINTK
bool "Early printk support"

4
arch/sh/Makefile
View File

@ -118,6 +118,7 @@ machdir-$(CONFIG_SH_7751_SYSTEMH) += renesas/systemh
machdir-$(CONFIG_SH_EDOSK7705) += renesas/edosk7705
machdir-$(CONFIG_SH_HIGHLANDER) += renesas/r7780rp
machdir-$(CONFIG_SH_7710VOIPGW) += renesas/sh7710voipgw
machdir-$(CONFIG_SH_X3PROTO) += renesas/x3proto
machdir-$(CONFIG_SH_SH4202_MICRODEV) += superh/microdev
machdir-$(CONFIG_SH_LANDISK) += landisk
machdir-$(CONFIG_SH_TITAN) += titan
@ -125,6 +126,7 @@ machdir-$(CONFIG_SH_SHMIN) += shmin
machdir-$(CONFIG_SH_7206_SOLUTION_ENGINE) += se/7206
machdir-$(CONFIG_SH_7619_SOLUTION_ENGINE) += se/7619
machdir-$(CONFIG_SH_LBOX_RE2) += lboxre2
machdir-$(CONFIG_SH_MAGIC_PANEL_R2) += magicpanelr2
incdir-y := $(notdir $(machdir-y))
@ -135,7 +137,7 @@ endif
# Companion chips
core-$(CONFIG_HD6446X_SERIES) += arch/sh/cchips/hd6446x/
core-$(CONFIG_VOYAGERGX) += arch/sh/cchips/voyagergx/
core-$(CONFIG_MFD_SM501) += arch/sh/cchips/voyagergx/
cpuincdir-$(CONFIG_CPU_SH2) := cpu-sh2
cpuincdir-$(CONFIG_CPU_SH2A) := cpu-sh2a

9
arch/sh/boards/hp6xx/hp6xx_apm.c
View File

@ -20,9 +20,9 @@
#define APM_CRITICAL 10
#define APM_LOW 30
#define HP680_BATTERY_MAX 875
#define HP680_BATTERY_MIN 600
#define HP680_BATTERY_AC_ON 900
#define HP680_BATTERY_MAX 898
#define HP680_BATTERY_MIN 486
#define HP680_BATTERY_AC_ON 1023
#define MODNAME "hp6x0_apm"
@ -65,7 +65,7 @@ static void hp6x0_apm_get_power_status(struct apm_power_info *info)
static irqreturn_t hp6x0_apm_interrupt(int irq, void *dev)
{
if (!apm_suspended)
if (!APM_DISABLED)
apm_queue_event(APM_USER_SUSPEND);
return IRQ_HANDLED;
@ -91,7 +91,6 @@ static int __init hp6x0_apm_init(void)
static void __exit hp6x0_apm_exit(void)
{
free_irq(HP680_BTN_IRQ, 0);
apm_get_info = NULL;
}
module_init(hp6x0_apm_init);

37
arch/sh/boards/hp6xx/setup.c
View File

@ -7,7 +7,7 @@
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Setup code for an HP680 (internal peripherials only)
* Setup code for HP620/HP660/HP680/HP690 (internal peripherials only)
*/
#include <linux/types.h>
#include <linux/init.h>
@ -19,7 +19,7 @@
#include <asm/cpu/dac.h>
#define SCPCR 0xa4000116
#define SCPDR 0xa4000136
#define SCPDR 0xa4000136
/* CF Slot */
static struct resource cf_ide_resources[] = {
@ -34,7 +34,7 @@ static struct resource cf_ide_resources[] = {
.flags = IORESOURCE_MEM,
},
[2] = {
.start = 93,
.start = 77,
.flags = IORESOURCE_IRQ,
},
};
@ -46,10 +46,22 @@ static struct platform_device cf_ide_device = {
.resource = cf_ide_resources,
};
static struct platform_device *hp6xx_devices[] __initdata = {
&cf_ide_device,
static struct platform_device jornadakbd_device = {
.name = "jornada680_kbd",
.id = -1,
};
static struct platform_device *hp6xx_devices[] __initdata = {
&cf_ide_device,
&jornadakbd_device,
};
static void __init hp6xx_init_irq(void)
{
/* Gets touchscreen and powerbutton IRQ working */
plat_irq_setup_pins(IRQ_MODE_IRQ);
}
static int __init hp6xx_devices_setup(void)
{
return platform_add_devices(hp6xx_devices, ARRAY_SIZE(hp6xx_devices));
@ -61,11 +73,11 @@ static void __init hp6xx_setup(char **cmdline_p)
u16 v;
v = inw(HD64461_STBCR);
v |= HD64461_STBCR_SURTST | HD64461_STBCR_SIRST |
HD64461_STBCR_STM1ST | HD64461_STBCR_STM0ST |
HD64461_STBCR_SAFEST | HD64461_STBCR_SPC0ST |
HD64461_STBCR_SMIAST | HD64461_STBCR_SAFECKE_OST |
HD64461_STBCR_SAFECKE_IST;
v |= HD64461_STBCR_SURTST | HD64461_STBCR_SIRST |
HD64461_STBCR_STM1ST | HD64461_STBCR_STM0ST |
HD64461_STBCR_SAFEST | HD64461_STBCR_SPC0ST |
HD64461_STBCR_SMIAST | HD64461_STBCR_SAFECKE_OST|
HD64461_STBCR_SAFECKE_IST;
#ifndef CONFIG_HD64461_ENABLER
v |= HD64461_STBCR_SPC1ST;
#endif
@ -101,6 +113,9 @@ device_initcall(hp6xx_devices_setup);
static struct sh_machine_vector mv_hp6xx __initmv = {
.mv_name = "hp6xx",
.mv_setup = hp6xx_setup,
.mv_nr_irqs = HD64461_IRQBASE + HD64461_IRQ_NUM,
/* IRQ's : CPU(64) + CCHIP(16) + FREE_TO_USE(6) */
.mv_nr_irqs = HD64461_IRQBASE + HD64461_IRQ_NUM + 6,
.mv_irq_demux = hd64461_irq_demux,
/* Enable IRQ0 -> IRQ3 in IRQ_MODE */
.mv_init_irq = hp6xx_init_irq,
};

13
arch/sh/boards/magicpanelr2/Kconfig Normal file
View File

@ -0,0 +1,13 @@
if SH_MAGIC_PANEL_R2
menu "Magic Panel R2 options"
config SH_MAGIC_PANEL_R2_VERSION
int SH_MAGIC_PANEL_R2_VERSION
default "3"
help
Set the version of the Magic Panel R2
endmenu
endif

5
arch/sh/boards/magicpanelr2/Makefile Normal file
View File

@ -0,0 +1,5 @@
#
# Makefile for the Magic Panel specific parts
#
obj-y := setup.o

394
arch/sh/boards/magicpanelr2/setup.c Normal file
View File

@ -0,0 +1,394 @@
/*
* linux/arch/sh/boards/magicpanel/setup.c
*
* Copyright (C) 2007 Markus Brunner, Mark Jonas
*
* Magic Panel Release 2 board setup
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/map.h>
#include <asm/magicpanelr2.h>
#include <asm/heartbeat.h>
#define LAN9115_READY (ctrl_inl(0xA8000084UL) & 0x00000001UL)
/* Prefer cmdline over RedBoot */
static const char *probes[] = { "cmdlinepart", "RedBoot", NULL };
/* Wait until reset finished. Timeout is 100ms. */
static int __init ethernet_reset_finished(void)
{
int i;
if (LAN9115_READY)
return 1;
for (i = 0; i < 10; ++i) {
mdelay(10);
if (LAN9115_READY)
return 1;
}
return 0;
}
static void __init reset_ethernet(void)
{
/* PMDR: LAN_RESET=on */
CLRBITS_OUTB(0x10, PORT_PMDR);
udelay(200);
/* PMDR: LAN_RESET=off */
SETBITS_OUTB(0x10, PORT_PMDR);
}
static void __init setup_chip_select(void)
{
/* CS2: LAN (0x08000000 - 0x0bffffff) */
/* no idle cycles, normal space, 8 bit data bus */
ctrl_outl(0x36db0400, CS2BCR);
/* (SW:1.5 WR:3 HW:1.5), ext. wait */
ctrl_outl(0x000003c0, CS2WCR);
/* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */
/* no idle cycles, normal space, 8 bit data bus */
ctrl_outl(0x00000200, CS4BCR);
/* (SW:1.5 WR:3 HW:1.5), ext. wait */
ctrl_outl(0x00100981, CS4WCR);
/* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */
/* no idle cycles, normal space, 8 bit data bus */
ctrl_outl(0x00000200, CS5ABCR);
/* (SW:1.5 WR:3 HW:1.5), ext. wait */
ctrl_outl(0x00100981, CS5AWCR);
/* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */
/* no idle cycles, normal space, 8 bit data bus */
ctrl_outl(0x00000200, CS5BBCR);
/* (SW:1.5 WR:3 HW:1.5), ext. wait */
ctrl_outl(0x00100981, CS5BWCR);
/* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */
/* no idle cycles, normal space, 8 bit data bus */
ctrl_outl(0x00000200, CS6ABCR);
/* (SW:1.5 WR:3 HW:1.5), no ext. wait */
ctrl_outl(0x001009C1, CS6AWCR);
}
static void __init setup_port_multiplexing(void)
{
/* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
* A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1);
*/
ctrl_outw(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */
/* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
* B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0);
*/
ctrl_outw(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */
/* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
* C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0;
*/
ctrl_outw(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */
/* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
* D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0);
*/
ctrl_outw(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */
/* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
* E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM;
*/
ctrl_outw(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */
/* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
* F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc);
*/
ctrl_outw(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */
/* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2);
* G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9);
*/
ctrl_outw(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */
/* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
* H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR;
*/
ctrl_outw(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */
/* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
* J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC;
*/
ctrl_outw(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */
/* K7 (x); K6 (x); K5 (x); K4 (x);
* K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY)
*/
ctrl_outw(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */
/* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
* L3 TCK; L2 (x); L1 (x); L0 (x);
*/
ctrl_outw(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */
/* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED);
* M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL);
* M1 CS5B(CAN3_CS); M0 GPI+(nc);
*/
ctrl_outw(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */
/* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit,
* LAN_RESET=off, BUZZER=off, LCD_BL=off
*/
#if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2
ctrl_outb(0x30, PORT_PMDR);
#elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3
ctrl_outb(0xF0, PORT_PMDR);
#else
#error Unknown revision of PLATFORM_MP_R2
#endif
/* P7 (x); P6 (x); P5 (x);
* P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);
* P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ)
*/
ctrl_outw(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */
ctrl_outb(0x10, PORT_PPDR);
/* R7 A25; R6 A24; R5 A23; R4 A22;
* R3 A21; R2 A20; R1 A19; R0 A0;
*/
ctrl_outw(0x0000, PORT_PRCR); /* 00 00 00 00 00 00 00 00 */
/* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
* S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK;
*/
ctrl_outw(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */
/* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
* T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG)
*/
ctrl_outw(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */
/* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
* U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK;
*/
ctrl_outw(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */
/* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
* V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT);
*/
ctrl_outw(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */
}
static void __init mpr2_setup(char **cmdline_p)
{
__set_io_port_base(0xa0000000);
/* set Pin Select Register A:
* /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2,
* /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND
*/
ctrl_outw(0xAABC, PORT_PSELA);
/* set Pin Select Register B:
* /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC,
* LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved
*/
ctrl_outw(0x3C00, PORT_PSELB);
/* set Pin Select Register C:
* SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved
*/
ctrl_outw(0x0000, PORT_PSELC);
/* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK,
* Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved
*/
ctrl_outw(0x0000, PORT_PSELD);
/* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */
ctrl_outw(0x0101, PORT_UTRCTL);
/* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */
ctrl_outw(0xA5C0, PORT_UCLKCR_W);
setup_chip_select();
setup_port_multiplexing();
reset_ethernet();
printk(KERN_INFO "Magic Panel Release 2 A.%i\n",
CONFIG_SH_MAGIC_PANEL_R2_VERSION);
if (ethernet_reset_finished() == 0)
printk(KERN_WARNING "Ethernet not ready\n");
}
static struct resource smc911x_resources[] = {
[0] = {
.start = 0xa8000000,
.end = 0xabffffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 35,
.end = 35,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc911x_device = {
.name = "smc911x",
.id = -1,
.num_resources = ARRAY_SIZE(smc911x_resources),
.resource = smc911x_resources,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
};
static struct heartbeat_data heartbeat_data = {
.flags = HEARTBEAT_INVERTED,
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
static struct mtd_partition *parsed_partitions;
static struct mtd_partition mpr2_partitions[] = {
/* Reserved for bootloader, read-only */
{
.name = "Bootloader",
.offset = 0x00000000UL,
.size = MPR2_MTD_BOOTLOADER_SIZE,
.mask_flags = MTD_WRITEABLE,
},
/* Reserved for kernel image */
{
.name = "Kernel",
.offset = MTDPART_OFS_NXTBLK,
.size = MPR2_MTD_KERNEL_SIZE,
},
/* Rest is used for Flash FS */
{
.name = "Flash_FS",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL,
}
};
static struct physmap_flash_data flash_data = {
.width = 2,
};
static struct resource flash_resource = {
.start = 0x00000000,
.end = 0x2000000UL,
.flags = IORESOURCE_MEM,
};
static struct platform_device flash_device = {
.name = "physmap-flash",
.id = -1,
.resource = &flash_resource,
.num_resources = 1,
.dev = {
.platform_data = &flash_data,
},
};
static struct mtd_info *flash_mtd;
static struct map_info mpr2_flash_map = {
.name = "Magic Panel R2 Flash",
.size = 0x2000000UL,
.bankwidth = 2,
};
static void __init set_mtd_partitions(void)
{
int nr_parts = 0;
simple_map_init(&mpr2_flash_map);
flash_mtd = do_map_probe("cfi_probe", &mpr2_flash_map);
nr_parts = parse_mtd_partitions(flash_mtd, probes,
&parsed_partitions, 0);
/* If there is no partition table, used the hard coded table */
if (nr_parts <= 0) {
flash_data.parts = mpr2_partitions;
flash_data.nr_parts = ARRAY_SIZE(mpr2_partitions);
} else {
flash_data.nr_parts = nr_parts;
flash_data.parts = parsed_partitions;
}
}
/*
* Add all resources to the platform_device
*/
static struct platform_device *mpr2_devices[] __initdata = {
&heartbeat_device,
&smc911x_device,
&flash_device,
};
static int __init mpr2_devices_setup(void)
{
set_mtd_partitions();
return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices));
}
device_initcall(mpr2_devices_setup);
/*
* Initialize IRQ setting
*/
static void __init init_mpr2_IRQ(void)
{
plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */
set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */
set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */
set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */
set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */
set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */
set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */
intc_set_priority(32, 13); /* IRQ0 CAN1 */
intc_set_priority(33, 13); /* IRQ0 CAN2 */
intc_set_priority(34, 13); /* IRQ0 CAN3 */
intc_set_priority(35, 6); /* IRQ3 SMSC9115 */
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_mpr2 __initmv = {
.mv_name = "mpr2",
.mv_setup = mpr2_setup,
.mv_init_irq = init_mpr2_IRQ,
};

2
arch/sh/boards/mpc1211/setup.c
View File

@ -285,7 +285,7 @@ static int put_smb_blk(unsigned char *p, int address, int command, int no)
static struct resource heartbeat_resources[] = {
[0] = {
.start = 0xa2000000,
.end = 0xa2000000 + 8 - 1,
.end = 0xa2000000,
.flags = IORESOURCE_MEM,
},
};

5
arch/sh/boards/renesas/r7780rp/Makefile
View File

@ -1,9 +1,10 @@
#
# Makefile for the R7780RP-1 specific parts of the kernel
#
irqinit-y := irq-r7780rp.o
irqinit-$(CONFIG_SH_R7780MP) := irq-r7780mp.o
irqinit-$(CONFIG_SH_R7785RP) := irq-r7785rp.o
obj-y := setup.o irq.o $(irqinit-y)
irqinit-$(CONFIG_SH_R7780RP) := irq-r7780rp.o irq.o
obj-y := setup.o $(irqinit-y)
ifneq ($(CONFIG_SH_R7785RP),y)
obj-$(CONFIG_PUSH_SWITCH) += psw.o

61
arch/sh/boards/renesas/r7780rp/irq-r7780mp.c Normal file
View File

@ -0,0 +1,61 @@
/*
* Renesas Solutions Highlander R7780MP Support.
*
* Copyright (C) 2002 Atom Create Engineering Co., Ltd.
* Copyright (C) 2006 Paul Mundt
* Copyright (C) 2007 Magnus Damm
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/r7780rp.h>
enum {
UNUSED = 0,
/* board specific interrupt sources */
AX88796, /* Ethernet controller */
CF, /* Compact Flash */
PSW, /* Push Switch */
EXT1, /* EXT1n IRQ */
EXT4, /* EXT4n IRQ */
};
static struct intc_vect vectors[] __initdata = {
INTC_IRQ(CF, IRQ_CF),
INTC_IRQ(PSW, IRQ_PSW),
INTC_IRQ(AX88796, IRQ_AX88796),
INTC_IRQ(EXT1, IRQ_EXT1),
INTC_IRQ(EXT4, IRQ_EXT4),
};
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xa4000000, 0, 16, /* IRLMSK */
{ 0, 0, 0, 0, CF, 0, 0, 0,
0, 0, 0, EXT4, 0, EXT1, PSW, AX88796 } },
};
static unsigned char irl2irq[HL_NR_IRL] __initdata = {
0, IRQ_CF, 0, 0,
0, 0, 0, 0,
0, IRQ_EXT4, 0, IRQ_EXT1,
0, IRQ_AX88796, IRQ_PSW,
};
static DECLARE_INTC_DESC(intc_desc, "r7780mp", vectors,
NULL, NULL, mask_registers, NULL, NULL);
unsigned char * __init highlander_init_irq_r7780mp(void)
{
if ((ctrl_inw(0xa4000700) & 0xf000) == 0x2000) {
printk(KERN_INFO "Using r7780mp interrupt controller.\n");
register_intc_controller(&intc_desc);
return irl2irq;
}
return NULL;
}

6
arch/sh/boards/renesas/r7780rp/irq-r7780rp.c
View File

@ -9,13 +9,15 @@
* for more details.
*/
#include <linux/init.h>
#include <asm/io.h>
#include <linux/io.h>
#include <asm/r7780rp.h>
void __init highlander_init_irq(void)
unsigned char * __init highlander_init_irq_r7780rp(void)
{
int i;
for (i = 0; i < 15; i++)
make_r7780rp_irq(i);
return NULL;
}

46
arch/sh/boards/renesas/r7780rp/irq-r7785rp.c
View File

@ -1,19 +1,55 @@
/*
* Renesas Solutions Highlander R7780RP-1 Support.
* Renesas Solutions Highlander R7785RP Support.
*
* Copyright (C) 2002 Atom Create Engineering Co., Ltd.
* Copyright (C) 2006 Paul Mundt
* Copyright (C) 2007 Magnus Damm
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <asm/io.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/r7780rp.h>
void __init highlander_init_irq(void)
enum {
UNUSED = 0,
/* board specific interrupt sources */
AX88796, /* Ethernet controller */
CF, /* Compact Flash */
};
static struct intc_vect vectors[] __initdata = {
INTC_IRQ(CF, IRQ_CF),
INTC_IRQ(AX88796, IRQ_AX88796),
};
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xa4000010, 0, 16, /* IRLMCR1 */
{ 0, 0, 0, 0, CF, AX88796, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 } },
};
static unsigned char irl2irq[HL_NR_IRL] __initdata = {
0, IRQ_CF, 0, 0,
0, 0, 0, 0,
0, 0, IRQ_AX88796, 0,
0, 0, 0,
};
static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors,
NULL, NULL, mask_registers, NULL, NULL);
unsigned char * __init highlander_init_irq_r7785rp(void)
{
if ((ctrl_inw(0xa4000158) & 0xf000) != 0x1000)
return NULL;
printk(KERN_INFO "Using r7785rp interrupt controller.\n");
ctrl_outw(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */
/* Setup the FPGA IRL */
@ -24,6 +60,6 @@ void __init highlander_init_irq(void)
ctrl_outw(0x4321, PA_IRLPRE); /* FPGA IRLE */
ctrl_outw(0x0000, PA_IRLPRF); /* FPGA IRLF */
make_r7780rp_irq(1); /* CF card */
make_r7780rp_irq(10); /* On-board ethernet */
register_intc_controller(&intc_desc);
return irl2irq;
}

70
arch/sh/boards/renesas/r7780rp/setup.c
View File

@ -19,6 +19,7 @@
#include <asm/machvec.h>
#include <asm/r7780rp.h>
#include <asm/clock.h>
#include <asm/heartbeat.h>
#include <asm/io.h>
static struct resource r8a66597_usb_host_resources[] = {
@ -30,8 +31,8 @@ static struct resource r8a66597_usb_host_resources[] = {
},
[1] = {
.name = "r8a66597_hcd",
.start = 11, /* irq number */
.end = 11,
.start = IRQ_EXT1, /* irq number */
.end = IRQ_EXT1,
.flags = IORESOURCE_IRQ,
},
};
@ -56,8 +57,8 @@ static struct resource m66592_usb_peripheral_resources[] = {
},
[1] = {
.name = "m66592_udc",
.start = 9, /* irq number */
.end = 9,
.start = IRQ_EXT4, /* irq number */
.end = IRQ_EXT4,
.flags = IORESOURCE_IRQ,
},
};
@ -85,11 +86,7 @@ static struct resource cf_ide_resources[] = {
.flags = IORESOURCE_MEM,
},
[2] = {
#ifdef CONFIG_SH_R7780RP
.start = 4,
#else
.start = 1,
#endif
.start = IRQ_CF,
.flags = IORESOURCE_IRQ,
},
};
@ -108,16 +105,23 @@ static struct platform_device cf_ide_device = {
},
};
static unsigned char heartbeat_bit_pos[] = { 2, 1, 0, 3, 6, 5, 4, 7 };
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_OBLED,
.end = PA_OBLED + ARRAY_SIZE(heartbeat_bit_pos) - 1,
.end = PA_OBLED,
.flags = IORESOURCE_MEM,
},
};
#ifndef CONFIG_SH_R7785RP
static unsigned char heartbeat_bit_pos[] = { 2, 1, 0, 3, 6, 5, 4, 7 };
static struct heartbeat_data heartbeat_data = {
.bit_pos = heartbeat_bit_pos,
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
};
#endif
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
@ -125,7 +129,7 @@ static struct platform_device heartbeat_device = {
/* R7785RP has a slightly more sensible FPGA.. */
#ifndef CONFIG_SH_R7785RP
.dev = {
.platform_data = heartbeat_bit_pos,
.platform_data = &heartbeat_data,
},
#endif
.num_resources = ARRAY_SIZE(heartbeat_resources),
@ -217,12 +221,50 @@ static void __init highlander_setup(char **cmdline_p)
pm_power_off = r7780rp_power_off;
}
static unsigned char irl2irq[HL_NR_IRL];
int highlander_irq_demux(int irq)
{
if (irq >= HL_NR_IRL || !irl2irq[irq])
return irq;
return irl2irq[irq];
}
void __init highlander_init_irq(void)
{
unsigned char *ucp = NULL;
do {
#ifdef CONFIG_SH_R7780MP
ucp = highlander_init_irq_r7780mp();
if (ucp)
break;
#endif
#ifdef CONFIG_SH_R7785RP
ucp = highlander_init_irq_r7785rp();
if (ucp)
break;
#endif
#ifdef CONFIG_SH_R7780RP
highlander_init_irq_r7780rp();
ucp = irl2irq;
break;
#endif
} while (0);
if (ucp) {
plat_irq_setup_pins(IRQ_MODE_IRL3210);
memcpy(irl2irq, ucp, HL_NR_IRL);
}
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_highlander __initmv = {
.mv_name = "Highlander",
.mv_nr_irqs = 109,
.mv_setup = highlander_setup,
.mv_init_irq = highlander_init_irq,
.mv_irq_demux = highlander_irq_demux,
};

19
arch/sh/boards/renesas/rts7751r2d/Kconfig
View File

@ -1,11 +1,22 @@
if SH_RTS7751R2D
menu "RTS7751R2D options"
menu "RTS7751R2D Board Revision"
config RTS7751R2D_REV11
bool "RTS7751R2D Rev. 1.1 board support"
config RTS7751R2D_PLUS
bool "R2D-PLUS"
help
Selecting this option will support version rev. 1.1.
Selecting this option will configure the kernel for R2D-PLUS.
R2D-PLUS is the smaller of the two R2D board versions, equipped
with a single PCI slot.
config RTS7751R2D_1
bool "R2D-1"
help
Selecting this option will configure the kernel for R2D-1.
R2D-1 is the larger of the two R2D board versions, equipped
with two PCI slots.
endmenu
endif

177
arch/sh/boards/renesas/rts7751r2d/irq.c
View File

@ -1,84 +1,159 @@
/*
* linux/arch/sh/boards/renesas/rts7751r2d/irq.c
*
* Copyright (C) 2007 Magnus Damm
* Copyright (C) 2000 Kazumoto Kojima
*
* Renesas Technology Sales RTS7751R2D Support.
* Renesas Technology Sales RTS7751R2D Support, R2D-PLUS and R2D-1.
*
* Modified for RTS7751R2D by
* Atom Create Engineering Co., Ltd. 2002.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <asm/voyagergx.h>
#include <asm/rts7751r2d.h>
#if defined(CONFIG_RTS7751R2D_REV11)
static int mask_pos[] = {11, 9, 8, 12, 10, 6, 5, 4, 7, 14, 13, 0, 0, 0, 0};
#else
static int mask_pos[] = {6, 11, 9, 8, 12, 10, 5, 4, 7, 14, 13, 0, 0, 0, 0};
#endif
#define R2D_NR_IRL 13
extern int voyagergx_irq_demux(int irq);
extern void setup_voyagergx_irq(void);
enum {
UNUSED = 0,
static void enable_rts7751r2d_irq(unsigned int irq)
{
/* Set priority in IPR back to original value */
ctrl_outw(ctrl_inw(IRLCNTR1) | (1 << mask_pos[irq]), IRLCNTR1);
}
/* board specific interrupt sources (R2D-1 and R2D-PLUS) */
EXT, /* EXT_INT0-3 */
RTC_T, RTC_A, /* Real Time Clock */
AX88796, /* Ethernet controller (R2D-1 board) */
KEY, /* Key input (R2D-PLUS board) */
SDCARD, /* SD Card */
CF_CD, CF_IDE, /* CF Card Detect + CF IDE */
SM501, /* SM501 aka Voyager */
PCI_INTD_RTL8139, /* Ethernet controller */
PCI_INTC_PCI1520, /* Cardbus/PCMCIA bridge */
PCI_INTB_RTL8139, /* Ethernet controller with HUB (R2D-PLUS board) */
PCI_INTB_SLOT, /* PCI Slot 3.3v (R2D-1 board) */
PCI_INTA_SLOT, /* PCI Slot 3.3v */
TP, /* Touch Panel */
};
static void disable_rts7751r2d_irq(unsigned int irq)
{
/* Set the priority in IPR to 0 */
ctrl_outw(ctrl_inw(IRLCNTR1) & (0xffff ^ (1 << mask_pos[irq])),
IRLCNTR1);
}
#ifdef CONFIG_RTS7751R2D_1
/* Vectors for R2D-1 */
static struct intc_vect vectors_r2d_1[] __initdata = {
INTC_IRQ(EXT, IRQ_EXT),
INTC_IRQ(RTC_T, IRQ_RTC_T), INTC_IRQ(RTC_A, IRQ_RTC_A),
INTC_IRQ(AX88796, IRQ_AX88796), INTC_IRQ(SDCARD, IRQ_SDCARD),
INTC_IRQ(CF_CD, IRQ_CF_CD), INTC_IRQ(CF_IDE, IRQ_CF_IDE), /* ng */
INTC_IRQ(SM501, IRQ_VOYAGER),
INTC_IRQ(PCI_INTD_RTL8139, IRQ_PCI_INTD),
INTC_IRQ(PCI_INTC_PCI1520, IRQ_PCI_INTC),
INTC_IRQ(PCI_INTB_SLOT, IRQ_PCI_INTB),
INTC_IRQ(PCI_INTA_SLOT, IRQ_PCI_INTA),
INTC_IRQ(TP, IRQ_TP),
};
/* IRLMSK mask register layout for R2D-1 */
static struct intc_mask_reg mask_registers_r2d_1[] __initdata = {
{ 0xa4000000, 0, 16, /* IRLMSK */
{ TP, PCI_INTA_SLOT, PCI_INTB_SLOT,
PCI_INTC_PCI1520, PCI_INTD_RTL8139,
SM501, CF_IDE, CF_CD, SDCARD, AX88796,
RTC_A, RTC_T, 0, 0, 0, EXT } },
};
/* IRLn to IRQ table for R2D-1 */
static unsigned char irl2irq_r2d_1[R2D_NR_IRL] __initdata = {
IRQ_PCI_INTD, IRQ_CF_IDE, IRQ_CF_CD, IRQ_PCI_INTC,
IRQ_VOYAGER, IRQ_AX88796, IRQ_RTC_A, IRQ_RTC_T,
IRQ_SDCARD, IRQ_PCI_INTA, IRQ_PCI_INTB, IRQ_EXT,
IRQ_TP,
};
static DECLARE_INTC_DESC(intc_desc_r2d_1, "r2d-1", vectors_r2d_1,
NULL, NULL, mask_registers_r2d_1, NULL, NULL);
#endif /* CONFIG_RTS7751R2D_1 */
#ifdef CONFIG_RTS7751R2D_PLUS
/* Vectors for R2D-PLUS */
static struct intc_vect vectors_r2d_plus[] __initdata = {
INTC_IRQ(EXT, IRQ_EXT),
INTC_IRQ(RTC_T, IRQ_RTC_T), INTC_IRQ(RTC_A, IRQ_RTC_A),
INTC_IRQ(KEY, IRQ_KEY), INTC_IRQ(SDCARD, IRQ_SDCARD),
INTC_IRQ(CF_CD, IRQ_CF_CD), INTC_IRQ(CF_IDE, IRQ_CF_IDE),
INTC_IRQ(SM501, IRQ_VOYAGER),
INTC_IRQ(PCI_INTD_RTL8139, IRQ_PCI_INTD),
INTC_IRQ(PCI_INTC_PCI1520, IRQ_PCI_INTC),
INTC_IRQ(PCI_INTB_RTL8139, IRQ_PCI_INTB),
INTC_IRQ(PCI_INTA_SLOT, IRQ_PCI_INTA),
INTC_IRQ(TP, IRQ_TP),
};
/* IRLMSK mask register layout for R2D-PLUS */
static struct intc_mask_reg mask_registers_r2d_plus[] __initdata = {
{ 0xa4000000, 0, 16, /* IRLMSK */
{ TP, PCI_INTA_SLOT, PCI_INTB_RTL8139,
PCI_INTC_PCI1520, PCI_INTD_RTL8139,
SM501, CF_IDE, CF_CD, SDCARD, KEY,
RTC_A, RTC_T, 0, 0, 0, EXT } },
};
/* IRLn to IRQ table for R2D-PLUS */
static unsigned char irl2irq_r2d_plus[R2D_NR_IRL] __initdata = {
IRQ_PCI_INTD, IRQ_CF_IDE, IRQ_CF_CD, IRQ_PCI_INTC,
IRQ_VOYAGER, IRQ_KEY, IRQ_RTC_A, IRQ_RTC_T,
IRQ_SDCARD, IRQ_PCI_INTA, IRQ_PCI_INTB, IRQ_EXT,
IRQ_TP,
};
static DECLARE_INTC_DESC(intc_desc_r2d_plus, "r2d-plus", vectors_r2d_plus,
NULL, NULL, mask_registers_r2d_plus, NULL, NULL);
#endif /* CONFIG_RTS7751R2D_PLUS */
static unsigned char irl2irq[R2D_NR_IRL];
int rts7751r2d_irq_demux(int irq)
{
return voyagergx_irq_demux(irq);
}
if (irq >= R2D_NR_IRL || !irl2irq[irq])
return irq;
static struct irq_chip rts7751r2d_irq_chip __read_mostly = {
.name = "rts7751r2d",
.mask = disable_rts7751r2d_irq,
.unmask = enable_rts7751r2d_irq,
.mask_ack = disable_rts7751r2d_irq,
};
return irl2irq[irq];
}
/*
* Initialize IRQ setting
*/
void __init init_rts7751r2d_IRQ(void)
{
int i;
struct intc_desc *d;
/* IRL0=KEY Input
* IRL1=Ethernet
* IRL2=CF Card
* IRL3=CF Card Insert
* IRL4=PCMCIA
* IRL5=VOYAGER
* IRL6=RTC Alarm
* IRL7=RTC Timer
* IRL8=SD Card
* IRL9=PCI Slot #1
* IRL10=PCI Slot #2
* IRL11=Extention #0
* IRL12=Extention #1
* IRL13=Extention #2
* IRL14=Extention #3
*/
for (i=0; i<15; i++) {
disable_irq_nosync(i);
set_irq_chip_and_handler_name(i, &rts7751r2d_irq_chip,
handle_level_irq, "level");
enable_rts7751r2d_irq(i);
switch (ctrl_inw(PA_VERREG) & 0xf0) {
#ifdef CONFIG_RTS7751R2D_PLUS
case 0x10:
printk(KERN_INFO "Using R2D-PLUS interrupt controller.\n");
d = &intc_desc_r2d_plus;
memcpy(irl2irq, irl2irq_r2d_plus, R2D_NR_IRL);
break;
#endif
#ifdef CONFIG_RTS7751R2D_1
case 0x00: /* according to manual */
case 0x30: /* in reality */
printk(KERN_INFO "Using R2D-1 interrupt controller.\n");
d = &intc_desc_r2d_1;
memcpy(irl2irq, irl2irq_r2d_1, R2D_NR_IRL);
break;
#endif
default:
printk(KERN_INFO "Unknown R2D interrupt controller 0x%04x\n",
ctrl_inw(PA_VERREG));
return;
}
register_intc_controller(d);
#ifdef CONFIG_MFD_SM501
setup_voyagergx_irq();
#endif
}

95
arch/sh/boards/renesas/rts7751r2d/setup.c
View File

@ -45,20 +45,16 @@ static void __init voyagergx_serial_init(void)
static struct resource cf_ide_resources[] = {
[0] = {
.start = PA_AREA5_IO + 0x1000,
.end = PA_AREA5_IO + 0x1000 + 0x08 - 1,
.end = PA_AREA5_IO + 0x1000 + 0x10 - 0x2,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PA_AREA5_IO + 0x80c,
.end = PA_AREA5_IO + 0x80c + 0x16 - 1,
.end = PA_AREA5_IO + 0x80c,
.flags = IORESOURCE_MEM,
},
[2] = {
#ifdef CONFIG_RTS7751R2D_REV11
.start = 1,
#else
.start = 2,
#endif
.start = IRQ_CF_IDE,
.flags = IORESOURCE_IRQ,
},
};
@ -77,12 +73,28 @@ static struct platform_device cf_ide_device = {
},
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_OUTPORT,
.end = PA_OUTPORT,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
#ifdef CONFIG_MFD_SM501
static struct plat_serial8250_port uart_platform_data[] = {
{
.membase = (void __iomem *)VOYAGER_UART_BASE,
.mapbase = VOYAGER_UART_BASE,
.iotype = UPIO_MEM,
.irq = VOYAGER_UART0_IRQ,
.irq = IRQ_SM501_U0,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.regshift = 2,
.uartclk = (9600 * 16),
@ -98,21 +110,6 @@ static struct platform_device uart_device = {
},
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_OUTPORT,
.end = PA_OUTPORT + 8 - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
static struct resource sm501_resources[] = {
[0] = {
.start = 0x10000000,
@ -125,7 +122,7 @@ static struct resource sm501_resources[] = {
.flags = IORESOURCE_MEM,
},
[2] = {
.start = 32,
.start = IRQ_SM501_CV,
.flags = IORESOURCE_IRQ,
},
};
@ -137,22 +134,19 @@ static struct platform_device sm501_device = {
.resource = sm501_resources,
};
#endif /* CONFIG_MFD_SM501 */
static struct platform_device *rts7751r2d_devices[] __initdata = {
#ifdef CONFIG_MFD_SM501
&uart_device,
&heartbeat_device,
&sm501_device,
#endif
&cf_ide_device,
&heartbeat_device,
};
static int __init rts7751r2d_devices_setup(void)
{
int ret;
if (ctrl_inw(PA_BVERREG) == 0x10) { /* only working on R2D-PLUS */
ret = platform_device_register(&cf_ide_device);
if (ret)
return ret;
}
return platform_add_devices(rts7751r2d_devices,
ARRAY_SIZE(rts7751r2d_devices));
}
@ -163,6 +157,34 @@ static void rts7751r2d_power_off(void)
ctrl_outw(0x0001, PA_POWOFF);
}
static inline unsigned char is_ide_ioaddr(unsigned long addr)
{
return ((cf_ide_resources[0].start <= addr &&
addr <= cf_ide_resources[0].end) ||
(cf_ide_resources[1].start <= addr &&
addr <= cf_ide_resources[1].end));
}
void rts7751r2d_writeb(u8 b, void __iomem *addr)
{
unsigned long tmp = (unsigned long __force)addr;
if (is_ide_ioaddr(tmp))
ctrl_outw((u16)b, tmp);
else
ctrl_outb(b, tmp);
}
u8 rts7751r2d_readb(void __iomem *addr)
{
unsigned long tmp = (unsigned long __force)addr;
if (is_ide_ioaddr(tmp))
return ctrl_inw(tmp) & 0xff;
else
return ctrl_inb(tmp);
}
/*
* Initialize the board
*/
@ -187,12 +209,11 @@ static void __init rts7751r2d_setup(char **cmdline_p)
static struct sh_machine_vector mv_rts7751r2d __initmv = {
.mv_name = "RTS7751R2D",
.mv_setup = rts7751r2d_setup,
.mv_nr_irqs = 72,
.mv_init_irq = init_rts7751r2d_IRQ,
.mv_irq_demux = rts7751r2d_irq_demux,
#ifdef CONFIG_USB_SM501
.mv_writeb = rts7751r2d_writeb,
.mv_readb = rts7751r2d_readb,
#if defined(CONFIG_MFD_SM501) && defined(CONFIG_USB_OHCI_HCD)
.mv_consistent_alloc = voyagergx_consistent_alloc,
.mv_consistent_free = voyagergx_consistent_free,
#endif

1
arch/sh/boards/renesas/x3proto/Makefile Normal file
View File

@ -0,0 +1 @@
obj-y += setup.o ilsel.o

151
arch/sh/boards/renesas/x3proto/ilsel.c Normal file
View File

@ -0,0 +1,151 @@
/*
* arch/sh/boards/renesas/x3proto/ilsel.c
*
* Helper routines for SH-X3 proto board ILSEL.
*
* Copyright (C) 2007 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/bitmap.h>
#include <linux/io.h>
#include <asm/ilsel.h>
/*
* ILSEL is split across:
*
* ILSEL0 - 0xb8100004 [ Levels 1 - 4 ]
* ILSEL1 - 0xb8100006 [ Levels 5 - 8 ]
* ILSEL2 - 0xb8100008 [ Levels 9 - 12 ]
* ILSEL3 - 0xb810000a [ Levels 13 - 15 ]
*
* With each level being relative to an ilsel_source_t.
*/
#define ILSEL_BASE 0xb8100004
#define ILSEL_LEVELS 15
/*
* ILSEL level map, in descending order from the highest level down.
*
* Supported levels are 1 - 15 spread across ILSEL0 - ILSEL4, mapping
* directly to IRLs. As the IRQs are numbered in reverse order relative
* to the interrupt level, the level map is carefully managed to ensure a
* 1:1 mapping between the bit position and the IRQ number.
*
* This careful constructions allows ilsel_enable*() to be referenced
* directly for hooking up an ILSEL set and getting back an IRQ which can
* subsequently be used for internal accounting in the (optional) disable
* path.
*/
static unsigned long ilsel_level_map;
static inline unsigned int ilsel_offset(unsigned int bit)
{
return ILSEL_LEVELS - bit - 1;
}
static inline unsigned long mk_ilsel_addr(unsigned int bit)
{
return ILSEL_BASE + ((ilsel_offset(bit) >> 1) & ~0x1);
}
static inline unsigned int mk_ilsel_shift(unsigned int bit)
{
return (ilsel_offset(bit) & 0x3) << 2;
}
static void __ilsel_enable(ilsel_source_t set, unsigned int bit)
{
unsigned int tmp, shift;
unsigned long addr;
addr = mk_ilsel_addr(bit);
shift = mk_ilsel_shift(bit);
pr_debug("%s: bit#%d: addr - 0x%08lx (shift %d, set %d)\n",
__FUNCTION__, bit, addr, shift, set);
tmp = ctrl_inw(addr);
tmp &= ~(0xf << shift);
tmp |= set << shift;
ctrl_outw(tmp, addr);
}
/**
* ilsel_enable - Enable an ILSEL set.
* @set: ILSEL source (see ilsel_source_t enum in include/asm-sh/ilsel.h).
*
* Enables a given non-aliased ILSEL source (<= ILSEL_KEY) at the highest
* available interrupt level. Callers should take care to order callsites
* noting descending interrupt levels. Aliasing FPGA and external board
* IRQs need to use ilsel_enable_fixed().
*
* The return value is an IRQ number that can later be taken down with
* ilsel_disable().
*/
int ilsel_enable(ilsel_source_t set)
{
unsigned int bit;
/* Aliased sources must use ilsel_enable_fixed() */
BUG_ON(set > ILSEL_KEY);
do {
bit = find_first_zero_bit(&ilsel_level_map, ILSEL_LEVELS);
} while (test_and_set_bit(bit, &ilsel_level_map));
__ilsel_enable(set, bit);
return bit;
}
EXPORT_SYMBOL_GPL(ilsel_enable);
/**
* ilsel_enable_fixed - Enable an ILSEL set at a fixed interrupt level
* @set: ILSEL source (see ilsel_source_t enum in include/asm-sh/ilsel.h).
* @level: Interrupt level (1 - 15)
*
* Enables a given ILSEL source at a fixed interrupt level. Necessary
* both for level reservation as well as for aliased sources that only
* exist on special ILSEL#s.
*
* Returns an IRQ number (as ilsel_enable()).
*/
int ilsel_enable_fixed(ilsel_source_t set, unsigned int level)
{
unsigned int bit = ilsel_offset(level - 1);
if (test_and_set_bit(bit, &ilsel_level_map))
return -EBUSY;
__ilsel_enable(set, bit);
return bit;
}
EXPORT_SYMBOL_GPL(ilsel_enable_fixed);
/**
* ilsel_disable - Disable an ILSEL set
* @irq: Bit position for ILSEL set value (retval from enable routines)
*
* Disable a previously enabled ILSEL set.
*/
void ilsel_disable(unsigned int irq)
{
unsigned long addr;
unsigned int tmp;
addr = mk_ilsel_addr(irq);
tmp = ctrl_inw(addr);
tmp &= ~(0xf << mk_ilsel_shift(irq));
ctrl_outw(tmp, addr);
clear_bit(irq, &ilsel_level_map);
}
EXPORT_SYMBOL_GPL(ilsel_disable);

136
arch/sh/boards/renesas/x3proto/setup.c Normal file
View File

@ -0,0 +1,136 @@
/*
* arch/sh/boards/renesas/x3proto/setup.c
*
* Renesas SH-X3 Prototype Board Support.
*
* Copyright (C) 2007 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <asm/ilsel.h>
static struct resource heartbeat_resources[] = {
[0] = {
.start = 0xb8140020,
.end = 0xb8140020,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
static struct resource smc91x_resources[] = {
[0] = {
.start = 0x18000300,
.end = 0x18000300 + 0x10 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
/* Filled in by ilsel */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = -1,
.resource = smc91x_resources,
.num_resources = ARRAY_SIZE(smc91x_resources),
};
static struct resource r8a66597_usb_host_resources[] = {
[0] = {
.name = "r8a66597_hcd",
.start = 0x18040000,
.end = 0x18080000 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "r8a66597_hcd",
/* Filled in by ilsel */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device r8a66597_usb_host_device = {
.name = "r8a66597_hcd",
.id = -1,
.dev = {
.dma_mask = NULL, /* don't use dma */
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
.resource = r8a66597_usb_host_resources,
};
static struct resource m66592_usb_peripheral_resources[] = {
[0] = {
.name = "m66592_udc",
.start = 0x18080000,
.end = 0x180c0000 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "m66592_udc",
/* Filled in by ilsel */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device m66592_usb_peripheral_device = {
.name = "m66592_udc",
.id = -1,
.dev = {
.dma_mask = NULL, /* don't use dma */
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(m66592_usb_peripheral_resources),
.resource = m66592_usb_peripheral_resources,
};
static struct platform_device *x3proto_devices[] __initdata = {
&heartbeat_device,
&smc91x_device,
&r8a66597_usb_host_device,
&m66592_usb_peripheral_device,
};
static int __init x3proto_devices_setup(void)
{
r8a66597_usb_host_resources[1].start =
r8a66597_usb_host_resources[1].end = ilsel_enable(ILSEL_USBH_I);
m66592_usb_peripheral_resources[1].start =
m66592_usb_peripheral_resources[1].end = ilsel_enable(ILSEL_USBP_I);
smc91x_resources[1].start =
smc91x_resources[1].end = ilsel_enable(ILSEL_LAN);
return platform_add_devices(x3proto_devices,
ARRAY_SIZE(x3proto_devices));
}
device_initcall(x3proto_devices_setup);
static void __init x3proto_init_irq(void)
{
plat_irq_setup_pins(IRQ_MODE_IRL3210);
/* Set ICR0.LVLMODE */
ctrl_outl(ctrl_inl(0xfe410000) | (1 << 21), 0xfe410000);
}
static struct sh_machine_vector mv_x3proto __initmv = {
.mv_name = "x3proto",
.mv_init_irq = x3proto_init_irq,
};

31
arch/sh/boards/se/7206/io.c
View File

@ -26,22 +26,24 @@ static inline void delay(void)
static inline volatile __u16 *
port2adr(unsigned int port)
{
if (port >= 0x2000)
if (port >= 0x2000 && port < 0x2020)
return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
else if (port >= 0x300 || port < 0x310)
else if (port >= 0x300 && port < 0x310)
return (volatile __u16 *) (PA_SMSC + (port - 0x300));
return (volatile __u16 *)port;
}
unsigned char se7206_inb(unsigned long port)
{
return (*port2adr(port))&0xff;
return (*port2adr(port)) & 0xff;
}
unsigned char se7206_inb_p(unsigned long port)
{
unsigned long v;
v = (*port2adr(port))&0xff;
v = (*port2adr(port)) & 0xff;
delay();
return v;
}
@ -51,12 +53,6 @@ unsigned short se7206_inw(unsigned long port)
return *port2adr(port);;
}
unsigned int se7206_inl(unsigned long port)
{
maybebadio(port);
return 0;
}
void se7206_outb(unsigned char value, unsigned long port)
{
*(port2adr(port)) = value;
@ -73,11 +69,6 @@ void se7206_outw(unsigned short value, unsigned long port)
*port2adr(port) = value;
}
void se7206_outl(unsigned int value, unsigned long port)
{
maybebadio(port);
}
void se7206_insb(unsigned long port, void *addr, unsigned long count)
{
volatile __u16 *p = port2adr(port);
@ -95,11 +86,6 @@ void se7206_insw(unsigned long port, void *addr, unsigned long count)
*ap++ = *p;
}
void se7206_insl(unsigned long port, void *addr, unsigned long count)
{
maybebadio(port);
}
void se7206_outsb(unsigned long port, const void *addr, unsigned long count)
{
volatile __u16 *p = port2adr(port);
@ -116,8 +102,3 @@ void se7206_outsw(unsigned long port, const void *addr, unsigned long count)
while (count--)
*p = *ap++;
}
void se7206_outsl(unsigned long port, const void *addr, unsigned long count)
{
maybebadio(port);
}

19
arch/sh/boards/se/7206/setup.c
View File

@ -6,14 +6,13 @@
* Copyright (C) 2007 Paul Mundt
*
* Hitachi 7206 SolutionEngine Support.
*
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/se7206.h>
#include <asm/io.h>
#include <asm/machvec.h>
#include <asm/heartbeat.h>
static struct resource smc91x_resources[] = {
[0] = {
@ -37,10 +36,16 @@ static struct platform_device smc91x_device = {
static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
static struct heartbeat_data heartbeat_data = {
.bit_pos = heartbeat_bit_pos,
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
.regsize = 32,
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED + ARRAY_SIZE(heartbeat_bit_pos) - 1,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
};
@ -49,7 +54,7 @@ static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = heartbeat_bit_pos,
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
@ -75,24 +80,18 @@ static struct sh_machine_vector mv_se __initmv = {
.mv_nr_irqs = 256,
.mv_inb = se7206_inb,
.mv_inw = se7206_inw,
.mv_inl = se7206_inl,
.mv_outb = se7206_outb,
.mv_outw = se7206_outw,
.mv_outl = se7206_outl,
.mv_inb_p = se7206_inb_p,
.mv_inw_p = se7206_inw,
.mv_inl_p = se7206_inl,
.mv_outb_p = se7206_outb_p,
.mv_outw_p = se7206_outw,
.mv_outl_p = se7206_outl,
.mv_insb = se7206_insb,
.mv_insw = se7206_insw,
.mv_insl = se7206_insl,
.mv_outsb = se7206_outsb,
.mv_outsw = se7206_outsw,
.mv_outsl = se7206_outsl,
.mv_init_irq = init_se7206_IRQ,
};

7
arch/sh/boards/se/7343/irq.c
View File

@ -99,8 +99,11 @@ shmse_irq_demux(int irq)
*
* We configure IRQ5 as a cascade IRQ.
*/
static struct irqaction irq5 = { no_action, 0, CPU_MASK_NONE, "IRQ5-cascade",
NULL, NULL};
static struct irqaction irq5 = {
.handler = no_action,
.mask = CPU_MASK_NONE,
.name = "IRQ5-cascade",
};
static struct ipr_data se7343_irq5_ipr_map[] = {
{ IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY },

2
arch/sh/boards/se/7343/setup.c
View File

@ -33,7 +33,7 @@ static struct platform_device smc91x_device = {
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED + 8 - 1,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
};

10
arch/sh/boards/se/770x/setup.c
View File

@ -12,6 +12,7 @@
#include <asm/se.h>
#include <asm/io.h>
#include <asm/smc37c93x.h>
#include <asm/heartbeat.h>
void init_se_IRQ(void);
@ -90,10 +91,15 @@ static struct platform_device cf_ide_device = {
static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
static struct heartbeat_data heartbeat_data = {
.bit_pos = heartbeat_bit_pos,
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED + ARRAY_SIZE(heartbeat_bit_pos) - 1,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
};
@ -102,7 +108,7 @@ static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = heartbeat_bit_pos,
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,

9
arch/sh/boards/se/7722/setup.c
View File

@ -18,12 +18,10 @@
#include <asm/io.h>
/* Heartbeat */
static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED + ARRAY_SIZE(heartbeat_bit_pos) - 1,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
};
@ -31,9 +29,6 @@ static struct resource heartbeat_resources[] = {
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = heartbeat_bit_pos,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
@ -109,7 +104,7 @@ static void __init se7722_setup(char **cmdline_p)
ctrl_outl(0x00051001, MSTPCR0);
ctrl_outl(0x00000000, MSTPCR1);
/* KEYSC, VOU, BEU, CEU, VEU, VPU, LCDC */
ctrl_outl(0xffffbfC0, MSTPCR2);
ctrl_outl(0xffffbfC0, MSTPCR2);
ctrl_outw(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */
ctrl_outw(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */

11
arch/sh/boards/se/7751/setup.c
View File

@ -13,13 +13,19 @@
#include <asm/machvec.h>
#include <asm/se7751.h>
#include <asm/io.h>
#include <asm/heartbeat.h>
static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
static struct heartbeat_data heartbeat_data = {
.bit_pos = heartbeat_bit_pos,
.nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
};
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED + ARRAY_SIZE(heartbeat_bit_pos) - 1,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
};
@ -28,14 +34,13 @@ static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = heartbeat_bit_pos,
.platform_data = &heartbeat_data,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
static struct platform_device *se7751_devices[] __initdata = {
&smc91x_device,
&heartbeat_device,
};

28
arch/sh/boards/se/7780/irq.c
View File

@ -16,32 +16,6 @@
#include <asm/io.h>
#include <asm/se7780.h>
static struct intc2_data intc2_irq_table[] = {
{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT1 */
{ 4, 0, 30, 0, 30, 3 }, /* daughter board EXTINT2 */
{ 6, 0, 29, 0, 29, 3 }, /* daughter board EXTINT3 */
{ 8, 0, 28, 0, 28, 3 }, /* SMC 91C111 (LAN) */
{ 10, 0, 27, 0, 27, 3 }, /* daughter board EXTINT4 */
{ 4, 0, 30, 0, 30, 3 }, /* daughter board EXTINT5 */
{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT6 */
{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT7 */
{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT8 */
{ 0 , 0, 24, 0, 24, 3 }, /* SM501 */
};
static struct intc2_desc intc2_irq_desc __read_mostly = {
.prio_base = 0, /* N/A */
.msk_base = 0xffd00044,
.mskclr_base = 0xffd00064,
.intc2_data = intc2_irq_table,
.nr_irqs = ARRAY_SIZE(intc2_irq_table),
.chip = {
.name = "INTC2-se7780",
},
};
/*
* Initialize IRQ setting
*/
@ -68,5 +42,5 @@ void __init init_se7780_IRQ(void)
/* FPGA + 0x0A */
ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
register_intc2_controller(&intc2_irq_desc);
plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */
}

7
arch/sh/boards/se/7780/setup.c
View File

@ -16,12 +16,10 @@
#include <asm/io.h>
/* Heartbeat */
static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED + ARRAY_SIZE(heartbeat_bit_pos) - 1,
.end = PA_LED,
.flags = IORESOURCE_MEM,
},
};
@ -29,9 +27,6 @@ static struct resource heartbeat_resources[] = {
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = heartbeat_bit_pos,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};

28
arch/sh/boards/sh03/setup.c
View File

@ -15,33 +15,9 @@
#include <asm/sh03/sh03.h>
#include <asm/addrspace.h>
static struct ipr_data ipr_irq_table[] = {
{ IRL0_IRQ, 0, IRL0_IPR_POS, IRL0_PRIORITY },
{ IRL1_IRQ, 0, IRL1_IPR_POS, IRL1_PRIORITY },
{ IRL2_IRQ, 0, IRL2_IPR_POS, IRL2_PRIORITY },
{ IRL3_IRQ, 0, IRL3_IPR_POS, IRL3_PRIORITY },
};
static unsigned long ipr_offsets[] = {
INTC_IPRD,
};
static struct ipr_desc ipr_irq_desc = {
.ipr_offsets = ipr_offsets,
.nr_offsets = ARRAY_SIZE(ipr_offsets),
.ipr_data = ipr_irq_table,
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
.chip = {
.name = "IPR-sh03",
},
};
static void __init init_sh03_IRQ(void)
{
ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
register_ipr_controller(&ipr_irq_desc);
plat_irq_setup_pins(IRQ_MODE_IRQ);
}
extern void *cf_io_base;
@ -68,7 +44,7 @@ static void __init sh03_setup(char **cmdline_p)
static struct resource heartbeat_resources[] = {
[0] = {
.start = 0xa0800000,
.end = 0xa0800000 + 8 - 1,
.end = 0xa0800000,
.flags = IORESOURCE_MEM,
},
};

26
arch/sh/boards/shmin/setup.c
View File

@ -14,36 +14,12 @@
#define PFC_PHCR 0xa400010eUL
#define INTC_ICR1 0xa4000010UL
#define INTC_IPRC 0xa4000016UL
static struct ipr_data ipr_irq_table[] = {
{ 32, 0, 0, 0 },
{ 33, 0, 4, 0 },
{ 34, 0, 8, 8 },
{ 35, 0, 12, 0 },
};
static unsigned long ipr_offsets[] = {
INTC_IPRC,
};
static struct ipr_desc ipr_irq_desc = {
.ipr_offsets = ipr_offsets,
.nr_offsets = ARRAY_SIZE(ipr_offsets),
.ipr_data = ipr_irq_table,
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
.chip = {
.name = "IPR-shmin",
},
};
static void __init init_shmin_irq(void)
{
ctrl_outw(0x2a00, PFC_PHCR); // IRQ0-3=IRQ
ctrl_outw(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active.
register_ipr_controller(&ipr_irq_desc);
plat_irq_setup_pins(IRQ_MODE_IRQ);
}
static void __iomem *shmin_ioport_map(unsigned long port, unsigned int size)

30
arch/sh/boards/snapgear/setup.c
View File

@ -68,37 +68,11 @@ module_init(eraseconfig_init);
* IRL3 = crypto
*/
static struct ipr_data ipr_irq_table[] = {
{ IRL0_IRQ, 0, IRL0_IPR_POS, IRL0_PRIORITY },
{ IRL1_IRQ, 0, IRL1_IPR_POS, IRL1_PRIORITY },
{ IRL2_IRQ, 0, IRL2_IPR_POS, IRL2_PRIORITY },
{ IRL3_IRQ, 0, IRL3_IPR_POS, IRL3_PRIORITY },
};
static unsigned long ipr_offsets[] = {
INTC_IPRD,
};
static struct ipr_desc ipr_irq_desc = {
.ipr_offsets = ipr_offsets,
.nr_offsets = ARRAY_SIZE(ipr_offsets),
.ipr_data = ipr_irq_table,
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
.chip = {
.name = "IPR-snapgear",
},
};
static void __init init_snapgear_IRQ(void)
{
/* enable individual interrupt mode for externals */
ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
printk("Setup SnapGear IRQ/IPR ...\n");
register_ipr_controller(&ipr_irq_desc);
/* enable individual interrupt mode for externals */
plat_irq_setup_pins(IRQ_MODE_IRQ);
}
/*

30
arch/sh/boards/titan/setup.c
View File

@ -12,38 +12,10 @@
#include <asm/titan.h>
#include <asm/io.h>
static struct ipr_data ipr_irq_table[] = {
/* IRQ, IPR idx, shift, prio */
{ TITAN_IRQ_WAN, 3, 12, 8 }, /* eth0 (WAN) */
{ TITAN_IRQ_LAN, 3, 8, 8 }, /* eth1 (LAN) */
{ TITAN_IRQ_MPCIA, 3, 4, 8 }, /* mPCI A (top) */
{ TITAN_IRQ_USB, 3, 0, 8 }, /* mPCI B (bottom), USB */
};
static unsigned long ipr_offsets[] = { /* stolen from setup-sh7750.c */
0xffd00004UL, /* 0: IPRA */
0xffd00008UL, /* 1: IPRB */
0xffd0000cUL, /* 2: IPRC */
0xffd00010UL, /* 3: IPRD */
};
static struct ipr_desc ipr_irq_desc = {
.ipr_offsets = ipr_offsets,
.nr_offsets = ARRAY_SIZE(ipr_offsets),
.ipr_data = ipr_irq_table,
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
.chip = {
.name = "IPR-titan",
},
};
static void __init init_titan_irq(void)
{
/* enable individual interrupt mode for externals */
ipr_irq_enable_irlm();
/* register ipr irqs */
register_ipr_controller(&ipr_irq_desc);
plat_irq_setup_pins(IRQ_MODE_IRQ);
}
static struct sh_machine_vector mv_titan __initmv = {

13
arch/sh/cchips/Kconfig
View File

@ -1,18 +1,5 @@
menu "Companion Chips"
config VOYAGERGX
bool "VoyagerGX chip support"
depends on SH_RTS7751R2D
help
Selecting this option will support Silicon Motion, Inc. SM501.
Designed to complement needs for the embedded industry, it
provides video and 2D capability. To reduce system cost a
wide variety of include I/O is supported, including analog RGB
and digital LCD Panel interface, 8-bit parallel interface, USB,
UART, IrDA, Zoom Video, AC97 or I2S, SSP, PWM, and I2C. There
are additional GPIO bits that can be used to interface to
external as well.
config HD6446X_SERIES
bool

13
arch/sh/cchips/hd6446x/hd64461.c
View File

@ -14,6 +14,9 @@
#include <asm/irq.h>
#include <asm/hd64461.h>
/* This belongs in cpu specific */
#define INTC_ICR1 0xA4140010UL
static void disable_hd64461_irq(unsigned int irq)
{
unsigned short nimr;
@ -121,10 +124,15 @@ int hd64461_irq_demux(int irq)
}
}
}
return __irq_demux(irq);
return irq;
}
static struct irqaction irq0 = { hd64461_interrupt, IRQF_DISABLED, CPU_MASK_NONE, "HD64461", NULL, NULL };
static struct irqaction irq0 = {
.handler = hd64461_interrupt,
.flags = IRQF_DISABLED,
.mask = CPU_MASK_NONE,
.name = "HD64461",
};
int __init setup_hd64461(void)
{
@ -143,6 +151,7 @@ int __init setup_hd64461(void)
#endif
outw(0xffff, HD64461_NIMR);
/* IRQ 80 -> 95 belongs to HD64461 */
for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++) {
irq_desc[i].chip = &hd64461_irq_type;
}

7
arch/sh/cchips/hd6446x/hd64465/setup.c
View File

@ -147,7 +147,12 @@ int hd64465_irq_demux(int irq)
return irq;
}
static struct irqaction irq0 = { hd64465_interrupt, IRQF_DISABLED, CPU_MASK_NONE, "HD64465", NULL, NULL};
static struct irqaction irq0 = {
.handler = hd64465_interrupt,
.flags = IRQF_DISABLED,
.mask = CPU_MASK_NONE,
.name = "HD64465",
};
static int __init setup_hd64465(void)

190
arch/sh/cchips/voyagergx/irq.c
View File

@ -23,149 +23,79 @@
#include <asm/voyagergx.h>
#include <asm/rts7751r2d.h>
static void disable_voyagergx_irq(unsigned int irq)
{
unsigned long val;
unsigned long mask = 1 << (irq - VOYAGER_IRQ_BASE);
enum {
UNUSED = 0,
pr_debug("disable_voyagergx_irq(%d): mask=%lx\n", irq, mask);
val = readl((void __iomem *)VOYAGER_INT_MASK);
val &= ~mask;
writel(val, (void __iomem *)VOYAGER_INT_MASK);
}
static void enable_voyagergx_irq(unsigned int irq)
{
unsigned long val;
unsigned long mask = 1 << (irq - VOYAGER_IRQ_BASE);
pr_debug("disable_voyagergx_irq(%d): mask=%lx\n", irq, mask);
val = readl((void __iomem *)VOYAGER_INT_MASK);
val |= mask;
writel(val, (void __iomem *)VOYAGER_INT_MASK);
}
static void mask_and_ack_voyagergx(unsigned int irq)
{
disable_voyagergx_irq(irq);
}
static void end_voyagergx_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_voyagergx_irq(irq);
}
static unsigned int startup_voyagergx_irq(unsigned int irq)
{
enable_voyagergx_irq(irq);
return 0;
}
static void shutdown_voyagergx_irq(unsigned int irq)
{
disable_voyagergx_irq(irq);
}
static struct hw_interrupt_type voyagergx_irq_type = {
.typename = "VOYAGERGX-IRQ",
.startup = startup_voyagergx_irq,
.shutdown = shutdown_voyagergx_irq,
.enable = enable_voyagergx_irq,
.disable = disable_voyagergx_irq,
.ack = mask_and_ack_voyagergx,
.end = end_voyagergx_irq,
/* voyager specific interrupt sources */
UP, G54, G53, G52, G51, G50, G49, G48,
I2C, PW, DMA, PCI, I2S, AC, US,
U1, U0, CV, MC, S1, S0,
UH, TWOD, ZD, PV, CI,
};
static irqreturn_t voyagergx_interrupt(int irq, void *dev_id)
static struct intc_vect vectors[] __initdata = {
INTC_IRQ(UP, IRQ_SM501_UP), INTC_IRQ(G54, IRQ_SM501_G54),
INTC_IRQ(G53, IRQ_SM501_G53), INTC_IRQ(G52, IRQ_SM501_G52),
INTC_IRQ(G51, IRQ_SM501_G51), INTC_IRQ(G50, IRQ_SM501_G50),
INTC_IRQ(G49, IRQ_SM501_G49), INTC_IRQ(G48, IRQ_SM501_G48),
INTC_IRQ(I2C, IRQ_SM501_I2C), INTC_IRQ(PW, IRQ_SM501_PW),
INTC_IRQ(DMA, IRQ_SM501_DMA), INTC_IRQ(PCI, IRQ_SM501_PCI),
INTC_IRQ(I2S, IRQ_SM501_I2S), INTC_IRQ(AC, IRQ_SM501_AC),
INTC_IRQ(US, IRQ_SM501_US), INTC_IRQ(U1, IRQ_SM501_U1),
INTC_IRQ(U0, IRQ_SM501_U0), INTC_IRQ(CV, IRQ_SM501_CV),
INTC_IRQ(MC, IRQ_SM501_MC), INTC_IRQ(S1, IRQ_SM501_S1),
INTC_IRQ(S0, IRQ_SM501_S0), INTC_IRQ(UH, IRQ_SM501_UH),
INTC_IRQ(TWOD, IRQ_SM501_2D), INTC_IRQ(ZD, IRQ_SM501_ZD),
INTC_IRQ(PV, IRQ_SM501_PV), INTC_IRQ(CI, IRQ_SM501_CI),
};
static struct intc_mask_reg mask_registers[] __initdata = {
{ VOYAGER_INT_MASK, 0, 32, /* "Interrupt Mask", MMIO_base + 0x30 */
{ UP, G54, G53, G52, G51, G50, G49, G48,
I2C, PW, 0, DMA, PCI, I2S, AC, US,
0, 0, U1, U0, CV, MC, S1, S0,
0, UH, 0, 0, TWOD, ZD, PV, CI } },
};
static DECLARE_INTC_DESC(intc_desc, "voyagergx", vectors,
NULL, NULL, mask_registers, NULL, NULL);
static unsigned int voyagergx_stat2irq[32] = {
IRQ_SM501_CI, IRQ_SM501_PV, IRQ_SM501_ZD, IRQ_SM501_2D,
0, 0, IRQ_SM501_UH, 0,
IRQ_SM501_S0, IRQ_SM501_S1, IRQ_SM501_MC, IRQ_SM501_CV,
IRQ_SM501_U0, IRQ_SM501_U1, 0, 0,
IRQ_SM501_US, IRQ_SM501_AC, IRQ_SM501_I2S, IRQ_SM501_PCI,
IRQ_SM501_DMA, 0, IRQ_SM501_PW, IRQ_SM501_I2C,
IRQ_SM501_G48, IRQ_SM501_G49, IRQ_SM501_G50, IRQ_SM501_G51,
IRQ_SM501_G52, IRQ_SM501_G53, IRQ_SM501_G54, IRQ_SM501_UP
};
static void voyagergx_irq_demux(unsigned int irq, struct irq_desc *desc)
{
printk(KERN_INFO
"VoyagerGX: spurious interrupt, status: 0x%x\n",
(unsigned int)readl((void __iomem *)INT_STATUS));
return IRQ_HANDLED;
}
unsigned long intv = ctrl_inl(INT_STATUS);
struct irq_desc *ext_desc;
unsigned int ext_irq;
unsigned int k = 0;
static struct {
int (*func)(int, void *);
void *dev;
} voyagergx_demux[VOYAGER_IRQ_NUM];
void voyagergx_register_irq_demux(int irq,
int (*demux)(int irq, void *dev), void *dev)
{
voyagergx_demux[irq - VOYAGER_IRQ_BASE].func = demux;
voyagergx_demux[irq - VOYAGER_IRQ_BASE].dev = dev;
}
void voyagergx_unregister_irq_demux(int irq)
{
voyagergx_demux[irq - VOYAGER_IRQ_BASE].func = 0;
}
int voyagergx_irq_demux(int irq)
{
if (irq == IRQ_VOYAGER ) {
unsigned long i = 0, bit __attribute__ ((unused));
unsigned long val = readl((void __iomem *)INT_STATUS);
if (val & (1 << 1))
i = 1;
else if (val & (1 << 2))
i = 2;
else if (val & (1 << 6))
i = 6;
else if (val & (1 << 10))
i = 10;
else if (val & (1 << 11))
i = 11;
else if (val & (1 << 12))
i = 12;
else if (val & (1 << 17))
i = 17;
else
printk("Unexpected IRQ irq = %d status = 0x%08lx\n", irq, val);
pr_debug("voyagergx_irq_demux %ld \n", i);
if (i < VOYAGER_IRQ_NUM) {
irq = VOYAGER_IRQ_BASE + i;
if (voyagergx_demux[i].func != 0)
irq = voyagergx_demux[i].func(irq,
voyagergx_demux[i].dev);
while (intv) {
ext_irq = voyagergx_stat2irq[k];
if (ext_irq && (intv & 1)) {
ext_desc = irq_desc + ext_irq;
handle_level_irq(ext_irq, ext_desc);
}
intv >>= 1;
k++;
}
return irq;
}
static struct irqaction irq0 = {
.name = "voyagergx",
.handler = voyagergx_interrupt,
.flags = IRQF_DISABLED,
.mask = CPU_MASK_NONE,
};
void __init setup_voyagergx_irq(void)
{
int i, flag;
printk(KERN_INFO "VoyagerGX configured at 0x%x on irq %d(mapped into %d to %d)\n",
VOYAGER_BASE,
printk(KERN_INFO "VoyagerGX on irq %d (mapped into %d to %d)\n",
IRQ_VOYAGER,
VOYAGER_IRQ_BASE,
VOYAGER_IRQ_BASE + VOYAGER_IRQ_NUM - 1);
for (i=0; i<VOYAGER_IRQ_NUM; i++) {
flag = 0;
switch (VOYAGER_IRQ_BASE + i) {
case VOYAGER_USBH_IRQ:
case VOYAGER_8051_IRQ:
case VOYAGER_UART0_IRQ:
case VOYAGER_UART1_IRQ:
case VOYAGER_AC97_IRQ:
flag = 1;
}
if (flag == 1)
irq_desc[VOYAGER_IRQ_BASE + i].chip = &voyagergx_irq_type;
}
setup_irq(IRQ_VOYAGER, &irq0);
register_intc_controller(&intc_desc);
set_irq_chained_handler(IRQ_VOYAGER, voyagergx_irq_demux);
}

155
arch/sh/configs/dreamcast_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.22-rc4
# Sat Jul 7 03:47:45 2007
# Linux kernel version: 2.6.23-rc7
# Fri Sep 21 15:46:27 2007
#
CONFIG_SUPERH=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
@ -18,30 +18,26 @@ CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_NO_VIRT_TO_BUS=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# Code maturity level options
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_IPC_NS is not set
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
# CONFIG_TASKSTATS is not set
# CONFIG_UTS_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
@ -64,7 +60,6 @@ CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
@ -74,24 +69,17 @@ CONFIG_SLAB=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
#
# Block layer
#
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
@ -112,7 +100,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_CPU_SH4=y
# CONFIG_CPU_SUBTYPE_SH7619 is not set
# CONFIG_CPU_SUBTYPE_SH7206 is not set
# CONFIG_CPU_SUBTYPE_SH7300 is not set
# CONFIG_CPU_SUBTYPE_SH7705 is not set
# CONFIG_CPU_SUBTYPE_SH7706 is not set
# CONFIG_CPU_SUBTYPE_SH7707 is not set
@ -120,6 +107,7 @@ CONFIG_CPU_SH4=y
# CONFIG_CPU_SUBTYPE_SH7709 is not set
# CONFIG_CPU_SUBTYPE_SH7710 is not set
# CONFIG_CPU_SUBTYPE_SH7712 is not set
# CONFIG_CPU_SUBTYPE_SH7720 is not set
# CONFIG_CPU_SUBTYPE_SH7750 is not set
CONFIG_CPU_SUBTYPE_SH7091=y
# CONFIG_CPU_SUBTYPE_SH7750R is not set
@ -134,7 +122,6 @@ CONFIG_CPU_SUBTYPE_SH7091=y
# CONFIG_CPU_SUBTYPE_SH7780 is not set
# CONFIG_CPU_SUBTYPE_SH7785 is not set
# CONFIG_CPU_SUBTYPE_SHX3 is not set
# CONFIG_CPU_SUBTYPE_SH73180 is not set
# CONFIG_CPU_SUBTYPE_SH7343 is not set
# CONFIG_CPU_SUBTYPE_SH7722 is not set
@ -177,7 +164,9 @@ CONFIG_NR_QUICK=2
# Cache configuration
#
# CONFIG_SH_DIRECT_MAPPED is not set
# CONFIG_SH_WRITETHROUGH is not set
CONFIG_CACHE_WRITEBACK=y
# CONFIG_CACHE_WRITETHROUGH is not set
# CONFIG_CACHE_OFF is not set
#
# Processor features
@ -185,12 +174,11 @@ CONFIG_NR_QUICK=2
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_SH_FPU=y
# CONFIG_SH_DSP is not set
CONFIG_SH_STORE_QUEUES=y
CONFIG_CPU_HAS_INTEVT=y
CONFIG_CPU_HAS_IPR_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
CONFIG_CPU_HAS_PTEA=y
CONFIG_CPU_HAS_FPU=y
#
# Board support
@ -270,6 +258,7 @@ CONFIG_CMDLINE="console=ttySC1,115200 panic=3"
#
# Bus options
#
CONFIG_MAPLE=y
CONFIG_PCI=y
CONFIG_SH_PCIDMA_NONCOHERENT=y
CONFIG_PCI_AUTO=y
@ -368,6 +357,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
@ -380,27 +370,10 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_SYS_HYPERVISOR is not set
#
# Connector - unified userspace <-> kernelspace linker
#
# CONFIG_CONNECTOR is not set
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNPACPI is not set
#
# Block devices
#
# CONFIG_BLK_CPQ_DA is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
@ -411,14 +384,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
#
# Misc devices
#
CONFIG_MISC_DEVICES=y
# CONFIG_PHANTOM is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_SGI_IOC4 is not set
# CONFIG_TIFM_CORE is not set
# CONFIG_BLINK is not set
# CONFIG_IDE is not set
#
@ -426,12 +396,9 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
@ -444,26 +411,16 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
#
# CONFIG_FIREWIRE is not set
# CONFIG_IEEE1394 is not set
#
# I2O device support
#
# CONFIG_I2O is not set
#
# Network device support
#
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ARCNET is not set
# CONFIG_PHYLIB is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_STNIC is not set
@ -472,10 +429,6 @@ CONFIG_MII=y
# CONFIG_CASSINI is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_SMC91X is not set
#
# Tulip family network device support
#
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
CONFIG_NET_PCI=y
@ -520,15 +473,7 @@ CONFIG_8139TOO=y
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
@ -536,6 +481,7 @@ CONFIG_8139TOO=y
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
@ -606,10 +552,6 @@ CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
@ -631,10 +573,6 @@ CONFIG_HW_RANDOM=y
# CONFIG_APPLICOM is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
CONFIG_DEVPORT=y
# CONFIG_I2C is not set
@ -644,11 +582,8 @@ CONFIG_DEVPORT=y
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
#
@ -673,6 +608,7 @@ CONFIG_DEVPORT=y
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
# CONFIG_FB_DDC is not set
@ -699,7 +635,6 @@ CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
CONFIG_FB_PVR2=y
# CONFIG_FB_EPSON1355 is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
@ -725,6 +660,7 @@ CONFIG_FB_PVR2=y
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
@ -749,16 +685,10 @@ CONFIG_LOGO_SUPERH_CLUT224=y
# Sound
#
# CONFIG_SOUND is not set
#
# HID Devices
#
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
#
# USB support
#
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB_ARCH_HAS_EHCI=y
@ -773,32 +703,8 @@ CONFIG_USB_ARCH_HAS_EHCI=y
#
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
#
# LED devices
#
# CONFIG_NEW_LEDS is not set
#
# LED drivers
#
#
# LED Triggers
#
#
# InfiniBand support
#
# CONFIG_INFINIBAND is not set
#
# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
#
#
# Real Time Clock
#
# CONFIG_RTC_CLASS is not set
#
@ -814,6 +720,11 @@ CONFIG_USB_ARCH_HAS_EHCI=y
# DMA Devices
#
#
# Userspace I/O
#
# CONFIG_UIO is not set
#
# File systems
#
@ -890,7 +801,6 @@ CONFIG_RAMFS=y
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
# CONFIG_9P_FS is not set
#
# Partition Types
@ -935,10 +845,6 @@ CONFIG_ENABLE_MUST_CHECK=y
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
#
@ -949,6 +855,7 @@ CONFIG_BITREVERSE=y
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y

557
arch/sh/configs/hp6xx_defconfig
View File

@ -1,37 +1,47 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.18
# Tue Oct 3 11:10:06 2006
# Linux kernel version: 2.6.23-rc4
# Tue Sep 11 19:42:44 2007
#
CONFIG_SUPERH=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_SYS_SUPPORTS_PM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_NO_VIRT_TO_BUS=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
# CONFIG_SYSVIPC is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_UTS_NS is not set
# CONFIG_IKCONFIG is not set
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
# CONFIG_USER_NS is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
@ -44,27 +54,25 @@ CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_SLAB=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
#
# Loadable module support
#
# CONFIG_MODULES is not set
#
# Block layer
#
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
@ -82,55 +90,17 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
#
# System type
#
# CONFIG_SH_SOLUTION_ENGINE is not set
# CONFIG_SH_7751_SOLUTION_ENGINE is not set
# CONFIG_SH_7300_SOLUTION_ENGINE is not set
# CONFIG_SH_7343_SOLUTION_ENGINE is not set
# CONFIG_SH_73180_SOLUTION_ENGINE is not set
# CONFIG_SH_7751_SYSTEMH is not set
CONFIG_SH_HP6XX=y
# CONFIG_SH_EC3104 is not set
# CONFIG_SH_SATURN is not set
# CONFIG_SH_DREAMCAST is not set
# CONFIG_SH_BIGSUR is not set
# CONFIG_SH_MPC1211 is not set
# CONFIG_SH_SH03 is not set
# CONFIG_SH_SECUREEDGE5410 is not set
# CONFIG_SH_HS7751RVOIP is not set
# CONFIG_SH_7710VOIPGW is not set
# CONFIG_SH_RTS7751R2D is not set
# CONFIG_SH_R7780RP is not set
# CONFIG_SH_EDOSK7705 is not set
# CONFIG_SH_SH4202_MICRODEV is not set
# CONFIG_SH_LANDISK is not set
# CONFIG_SH_TITAN is not set
# CONFIG_SH_SHMIN is not set
# CONFIG_SH_UNKNOWN is not set
#
# Processor selection
#
CONFIG_CPU_SH3=y
#
# SH-2 Processor Support
#
# CONFIG_CPU_SUBTYPE_SH7604 is not set
#
# SH-3 Processor Support
#
# CONFIG_CPU_SUBTYPE_SH7300 is not set
# CONFIG_CPU_SUBTYPE_SH7619 is not set
# CONFIG_CPU_SUBTYPE_SH7206 is not set
# CONFIG_CPU_SUBTYPE_SH7705 is not set
# CONFIG_CPU_SUBTYPE_SH7706 is not set
# CONFIG_CPU_SUBTYPE_SH7707 is not set
# CONFIG_CPU_SUBTYPE_SH7708 is not set
CONFIG_CPU_SUBTYPE_SH7709=y
# CONFIG_CPU_SUBTYPE_SH7710 is not set
#
# SH-4 Processor Support
#
# CONFIG_CPU_SUBTYPE_SH7712 is not set
# CONFIG_CPU_SUBTYPE_SH7720 is not set
# CONFIG_CPU_SUBTYPE_SH7750 is not set
# CONFIG_CPU_SUBTYPE_SH7091 is not set
# CONFIG_CPU_SUBTYPE_SH7750R is not set
@ -139,66 +109,78 @@ CONFIG_CPU_SUBTYPE_SH7709=y
# CONFIG_CPU_SUBTYPE_SH7751R is not set
# CONFIG_CPU_SUBTYPE_SH7760 is not set
# CONFIG_CPU_SUBTYPE_SH4_202 is not set
#
# ST40 Processor Support
#
# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
#
# SH-4A Processor Support
#
# CONFIG_CPU_SUBTYPE_SH7770 is not set
# CONFIG_CPU_SUBTYPE_SH7780 is not set
#
# SH4AL-DSP Processor Support
#
# CONFIG_CPU_SUBTYPE_SH73180 is not set
# CONFIG_CPU_SUBTYPE_SH7785 is not set
# CONFIG_CPU_SUBTYPE_SHX3 is not set
# CONFIG_CPU_SUBTYPE_SH7343 is not set
# CONFIG_CPU_SUBTYPE_SH7722 is not set
#
# Memory management options
#
CONFIG_QUICKLIST=y
CONFIG_MMU=y
CONFIG_PAGE_OFFSET=0x80000000
CONFIG_MEMORY_START=0x0c000000
CONFIG_MEMORY_START=0x0d000000
CONFIG_MEMORY_SIZE=0x00400000
CONFIG_VSYSCALL=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_MAX_ACTIVE_REGIONS=1
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PAGE_SIZE_64KB is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPARSEMEM_STATIC=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_NR_QUICK=2
#
# Cache configuration
#
# CONFIG_SH_DIRECT_MAPPED is not set
# CONFIG_SH_WRITETHROUGH is not set
# CONFIG_SH_OCRAM is not set
CONFIG_CACHE_WRITEBACK=y
# CONFIG_CACHE_WRITETHROUGH is not set
# CONFIG_CACHE_OFF is not set
#
# Processor features
#
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_CPU_BIG_ENDIAN is not set
# CONFIG_SH_FPU_EMU is not set
# CONFIG_SH_DSP is not set
CONFIG_SH_ADC=y
CONFIG_CPU_HAS_INTEVT=y
CONFIG_CPU_HAS_PINT_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
#
# Timer support
# Board support
#
# CONFIG_SH_SOLUTION_ENGINE is not set
CONFIG_SH_HP6XX=y
#
# Timer and clock configuration
#
CONFIG_SH_TMU=y
CONFIG_SH_TIMER_IRQ=16
CONFIG_SH_PCLK_FREQ=22110000
# CONFIG_TICK_ONESHOT is not set
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
#
# CPU Frequency scaling
@ -208,6 +190,7 @@ CONFIG_SH_PCLK_FREQ=22110000
#
# DMA support
#
CONFIG_SH_DMA_API=y
CONFIG_SH_DMA=y
CONFIG_NR_ONCHIP_DMA_CHANNELS=4
# CONFIG_NR_DMA_CHANNELS_BOOL is not set
@ -222,15 +205,22 @@ CONFIG_HD64461_IRQ=36
CONFIG_HD64461_IOBASE=0xb0000000
CONFIG_HD64461_ENABLER=y
#
# Additional SuperH Device Drivers
#
# CONFIG_HEARTBEAT is not set
# CONFIG_PUSH_SWITCH is not set
#
# Kernel features
#
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
# CONFIG_KEXEC is not set
# CONFIG_SMP is not set
# CONFIG_CRASH_DUMP is not set
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
@ -240,14 +230,13 @@ CONFIG_PREEMPT_NONE=y
#
CONFIG_ZERO_PAGE_OFFSET=0x00001000
CONFIG_BOOT_LINK_OFFSET=0x00800000
# CONFIG_UBC_WAKEUP is not set
# CONFIG_CMDLINE_BOOL is not set
#
# Bus options
#
CONFIG_ISA=y
# CONFIG_PCI is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
#
# PCCARD (PCMCIA/CardBus) support
@ -265,15 +254,10 @@ CONFIG_PCMCIA_IOCTL=y
# CONFIG_TCIC is not set
CONFIG_PCMCIA_PROBE=y
#
# PCI Hotplug Support
#
#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_FLAT is not set
# CONFIG_BINFMT_MISC is not set
#
@ -282,8 +266,9 @@ CONFIG_BINFMT_ELF=y
CONFIG_PM=y
CONFIG_PM_LEGACY=y
# CONFIG_PM_DEBUG is not set
# CONFIG_PM_SYSFS_DEPRECATED is not set
CONFIG_APM=y
CONFIG_PM_SLEEP=y
CONFIG_SUSPEND=y
CONFIG_APM_EMULATION=y
#
# Networking
@ -301,109 +286,76 @@ CONFIG_APM=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
# CONFIG_SYS_HYPERVISOR is not set
#
# Connector - unified userspace <-> kernelspace linker
#
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Block devices
#
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
CONFIG_BLK_DEV_INITRD=y
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
#
# ATA/ATAPI/MFM/RLL support
#
CONFIG_IDE=y
CONFIG_IDE_MAX_HWIFS=4
CONFIG_BLK_DEV_IDE=y
#
# Please see Documentation/ide.txt for help/info on IDE drives
#
# CONFIG_BLK_DEV_IDE_SATA is not set
CONFIG_BLK_DEV_IDEDISK=y
# CONFIG_IDEDISK_MULTI_MODE is not set
CONFIG_BLK_DEV_IDECS=y
# CONFIG_BLK_DEV_IDECD is not set
# CONFIG_BLK_DEV_IDETAPE is not set
# CONFIG_BLK_DEV_IDEFLOPPY is not set
# CONFIG_IDE_TASK_IOCTL is not set
#
# IDE chipset support/bugfixes
#
CONFIG_IDE_GENERIC=y
# CONFIG_IDE_ARM is not set
# CONFIG_IDE_CHIPSETS is not set
# CONFIG_BLK_DEV_IDEDMA is not set
# CONFIG_IDEDMA_AUTO is not set
# CONFIG_BLK_DEV_HD is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
#
# Serial ATA (prod) and Parallel ATA (experimental) drivers
# SCSI support type (disk, tape, CD-ROM)
#
# CONFIG_ATA is not set
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
#
# Old CD-ROM drivers (not SCSI, not IDE)
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_CD_NO_IDESCSI is not set
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
#
# Multi-device support (RAID and LVM)
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_SCSI_AHA152X is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_IN2000 is not set
# CONFIG_SCSI_DTC3280 is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GENERIC_NCR5380 is not set
# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
# CONFIG_SCSI_NCR53C406A is not set
# CONFIG_SCSI_PAS16 is not set
# CONFIG_SCSI_PSI240I is not set
# CONFIG_SCSI_QLOGIC_FAS is not set
# CONFIG_SCSI_SYM53C416 is not set
# CONFIG_SCSI_T128 is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
CONFIG_ATA=y
# CONFIG_ATA_NONSTANDARD is not set
# CONFIG_PATA_LEGACY is not set
# CONFIG_PATA_PCMCIA is not set
# CONFIG_PATA_QDI is not set
# CONFIG_PATA_WINBOND_VLB is not set
CONFIG_PATA_PLATFORM=y
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
#
# I2O device support
#
#
# ISDN subsystem
#
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
@ -411,19 +363,17 @@ CONFIG_IDE_GENERIC=y
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
CONFIG_INPUT_POLLDEV=y
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_TSDEV=y
CONFIG_INPUT_TSDEV_SCREEN_X=240
CONFIG_INPUT_TSDEV_SCREEN_Y=320
# CONFIG_INPUT_EVDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
#
@ -436,9 +386,12 @@ CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
CONFIG_KEYBOARD_HP6XX=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
@ -447,6 +400,7 @@ CONFIG_TOUCHSCREEN_HP600=y
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_UCB1400 is not set
# CONFIG_INPUT_MISC is not set
#
@ -476,29 +430,20 @@ CONFIG_HW_CONSOLE=y
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_SH_SCI is not set
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=3
CONFIG_SERIAL_SH_SCI_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
#
# IPMI
#
CONFIG_LEGACY_PTY_COUNT=64
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
CONFIG_HW_RANDOM=y
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
#
# Ftape, the floppy tape device driver
#
#
# PCMCIA character devices
#
@ -506,16 +451,8 @@ CONFIG_HW_RANDOM=y
# CONFIG_CARDMAN_4000 is not set
# CONFIG_CARDMAN_4040 is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
# CONFIG_TELCLOCK is not set
#
# I2C support
#
CONFIG_DEVPORT=y
# CONFIG_I2C is not set
#
@ -523,48 +460,55 @@ CONFIG_HW_RANDOM=y
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
#
# Dallas's 1-wire bus
#
#
# Hardware Monitoring support
#
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_SENSORS_ABITUGURU is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
#
# Misc devices
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
CONFIG_VIDEO_V4L2=y
#
# Digital Video Broadcasting Devices
#
# CONFIG_DAB is not set
#
# Graphics support
#
CONFIG_FIRMWARE_EDID=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_HP680=y
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=y
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
# CONFIG_FB_DDC is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_SYS_FOPS is not set
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set
# CONFIG_FB_EPSON1355 is not set
#
# Frame buffer hardware drivers
#
# CONFIG_FB_S1D13XXX is not set
CONFIG_FB_HIT=y
# CONFIG_FB_VIRTUAL is not set
@ -575,6 +519,7 @@ CONFIG_FB_HIT=y
# CONFIG_MDA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FONTS=y
# CONFIG_FONT_8x8 is not set
@ -587,79 +532,49 @@ CONFIG_FONT_PEARL_8x8=y
# CONFIG_FONT_SUN8x16 is not set
# CONFIG_FONT_SUN12x22 is not set
# CONFIG_FONT_10x18 is not set
#
# Logo configuration
#
# CONFIG_LOGO is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Sound
#
CONFIG_SOUND=y
#
# Advanced Linux Sound Architecture
#
# CONFIG_SND is not set
#
# Open Sound System
#
CONFIG_SOUND_PRIME=y
# CONFIG_OSS_OBSOLETE_DRIVER is not set
# CONFIG_SOUND_MSNDCLAS is not set
# CONFIG_SOUND_MSNDPIN is not set
CONFIG_SOUND_SH_DAC_AUDIO=y
CONFIG_SOUND_SH_DAC_AUDIO_CHANNEL=1
#
# USB support
#
# CONFIG_USB_ARCH_HAS_HCD is not set
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# MMC/SD Card support
#
# CONFIG_SOUND is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
#
# LED devices
#
# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
#
# LED drivers
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# SPI RTC drivers
#
#
# LED Triggers
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# InfiniBand support
# on-CPU RTC drivers
#
#
# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
#
#
# Real Time Clock
#
# CONFIG_RTC_CLASS is not set
CONFIG_RTC_DRV_SH=y
#
# DMA Engine support
@ -674,6 +589,11 @@ CONFIG_SOUND_SH_DAC_AUDIO_CHANNEL=1
# DMA Devices
#
#
# Userspace I/O
#
# CONFIG_UIO is not set
#
# File systems
#
@ -681,10 +601,12 @@ CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
@ -705,7 +627,7 @@ CONFIG_DNOTIFY=y
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
# CONFIG_MSDOS_FS is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
@ -755,7 +677,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_437 is not set
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
CONFIG_NLS_CODEPAGE_850=y
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
@ -799,34 +721,73 @@ CONFIG_NLS_DEFAULT="iso8859-1"
#
# Kernel hacking
#
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_UNWIND_INFO is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_SH_STANDARD_BIOS is not set
# CONFIG_KGDB is not set
# CONFIG_EARLY_SCIF_CONSOLE is not set
# CONFIG_SH_KGDB is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_MANAGER=y
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_GF128MUL is not set
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_PCBC=y
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_HW is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
CONFIG_CRC16=y
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

925
arch/sh/configs/magicpanelr2_defconfig Normal file
View File

@ -0,0 +1,925 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.23-rc2
# Fri Aug 17 12:15:16 2007
#
CONFIG_SUPERH=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_NO_VIRT_TO_BUS=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
CONFIG_AUDIT=y
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=17
CONFIG_SYSFS_DEPRECATED=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_KMOD=y
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
#
# System type
#
CONFIG_CPU_SH3=y
# CONFIG_CPU_SUBTYPE_SH7619 is not set
# CONFIG_CPU_SUBTYPE_SH7206 is not set
# CONFIG_CPU_SUBTYPE_SH7705 is not set
# CONFIG_CPU_SUBTYPE_SH7706 is not set
# CONFIG_CPU_SUBTYPE_SH7707 is not set
# CONFIG_CPU_SUBTYPE_SH7708 is not set
# CONFIG_CPU_SUBTYPE_SH7709 is not set
# CONFIG_CPU_SUBTYPE_SH7710 is not set
# CONFIG_CPU_SUBTYPE_SH7712 is not set
CONFIG_CPU_SUBTYPE_SH7720=y
# CONFIG_CPU_SUBTYPE_SH7750 is not set
# CONFIG_CPU_SUBTYPE_SH7091 is not set
# CONFIG_CPU_SUBTYPE_SH7750R is not set
# CONFIG_CPU_SUBTYPE_SH7750S is not set
# CONFIG_CPU_SUBTYPE_SH7751 is not set
# CONFIG_CPU_SUBTYPE_SH7751R is not set
# CONFIG_CPU_SUBTYPE_SH7760 is not set
# CONFIG_CPU_SUBTYPE_SH4_202 is not set
# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
# CONFIG_CPU_SUBTYPE_SH7770 is not set
# CONFIG_CPU_SUBTYPE_SH7780 is not set
# CONFIG_CPU_SUBTYPE_SH7785 is not set
# CONFIG_CPU_SUBTYPE_SHX3 is not set
# CONFIG_CPU_SUBTYPE_SH7343 is not set
# CONFIG_CPU_SUBTYPE_SH7722 is not set
#
# Memory management options
#
CONFIG_QUICKLIST=y
CONFIG_MMU=y
CONFIG_PAGE_OFFSET=0x80000000
CONFIG_MEMORY_START=0x0C000000
CONFIG_MEMORY_SIZE=0x03F00000
CONFIG_VSYSCALL=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_MAX_ACTIVE_REGIONS=1
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PAGE_SIZE_64KB is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_SPARSEMEM_STATIC=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_NR_QUICK=2
#
# Cache configuration
#
# CONFIG_SH_DIRECT_MAPPED is not set
CONFIG_CACHE_WRITEBACK=y
# CONFIG_CACHE_WRITETHROUGH is not set
# CONFIG_CACHE_OFF is not set
#
# Processor features
#
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_CPU_BIG_ENDIAN is not set
# CONFIG_SH_FPU_EMU is not set
CONFIG_SH_DSP=y
CONFIG_SH_ADC=y
CONFIG_CPU_HAS_INTEVT=y
CONFIG_CPU_HAS_INTC_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
CONFIG_CPU_HAS_DSP=y
#
# Board support
#
CONFIG_SH_MAGIC_PANEL_R2=y
#
# Magic Panel R2 options
#
CONFIG_SH_MAGIC_PANEL_R2_VERSION=3
#
# Timer and clock configuration
#
CONFIG_SH_TMU=y
CONFIG_SH_TIMER_IRQ=16
CONFIG_SH_PCLK_FREQ=24000000
# CONFIG_TICK_ONESHOT is not set
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
#
# DMA support
#
CONFIG_SH_DMA_API=y
CONFIG_SH_DMA=y
CONFIG_NR_ONCHIP_DMA_CHANNELS=6
# CONFIG_NR_DMA_CHANNELS_BOOL is not set
#
# Companion Chips
#
#
# Additional SuperH Device Drivers
#
CONFIG_HEARTBEAT=y
# CONFIG_PUSH_SWITCH is not set
#
# Kernel features
#
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
# CONFIG_KEXEC is not set
# CONFIG_CRASH_DUMP is not set
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
#
# Boot options
#
CONFIG_ZERO_PAGE_OFFSET=0x00001000
CONFIG_BOOT_LINK_OFFSET=0x00800000
# CONFIG_CMDLINE_BOOL is not set
#
# Bus options
#
# CONFIG_ARCH_SUPPORTS_MSI is not set
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_MMAP=y
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_FW_LOADER=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
CONFIG_MTD_CMDLINE_PARTS=y
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_START=0x0000000
CONFIG_MTD_PHYSMAP_LEN=0
CONFIG_MTD_PHYSMAP_BANKWIDTH=0
# CONFIG_MTD_SOLUTIONENGINE is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_STNIC is not set
# CONFIG_SMC91X is not set
CONFIG_SMC911X=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
CONFIG_INPUT_MOUSE=y
# CONFIG_MOUSE_PS2 is not set
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=48
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_RSA is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=2
CONFIG_SERIAL_SH_SCI_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
CONFIG_DAB=y
#
# Graphics support
#
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
#
# Sound
#
# CONFIG_SOUND is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set
# CONFIG_RTC_DEBUG is not set
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# SPI RTC drivers
#
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_SH=y
#
# DMA Engine support
#
# CONFIG_DMA_ENGINE is not set
#
# DMA Clients
#
#
# DMA Devices
#
#
# Userspace I/O
#
# CONFIG_UIO is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
# CONFIG_EXT4DEV_FS is not set
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_INOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_DNOTIFY is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLBFS is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
# CONFIG_JFFS2_FS_WRITEBUFFER is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_BIND34=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="cp437"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
CONFIG_NLS_CODEPAGE_850=y
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
#
# Distributed Lock Manager
#
# CONFIG_DLM is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
# CONFIG_DETECT_SOFTLOCKUP is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
CONFIG_DEBUG_KOBJECT=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
CONFIG_FRAME_POINTER=y
# CONFIG_FORCED_INLINING is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SH_STANDARD_BIOS is not set
CONFIG_EARLY_SCIF_CONSOLE=y
CONFIG_EARLY_SCIF_CONSOLE_PORT=0xa4430000
CONFIG_EARLY_PRINTK=y
# CONFIG_DEBUG_BOOTMEM is not set
# CONFIG_DEBUG_STACKOVERFLOW is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_4KSTACKS is not set
CONFIG_SH_KGDB=y
#
# KGDB configuration options
#
# CONFIG_MORE_COMPILE_OPTIONS is not set
# CONFIG_KGDB_NMI is not set
CONFIG_KGDB_SYSRQ=y
#
# Serial port setup
#
CONFIG_KGDB_DEFPORT=0
CONFIG_KGDB_DEFBAUD=115200
CONFIG_KGDB_DEFPARITY_N=y
# CONFIG_KGDB_DEFPARITY_E is not set
# CONFIG_KGDB_DEFPARITY_O is not set
CONFIG_KGDB_DEFBITS_8=y
# CONFIG_KGDB_DEFBITS_7 is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_CRYPTO is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_CRC_CCITT=m
CONFIG_CRC16=m
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_AUDIT_GENERIC=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

478
arch/sh/configs/rts7751r2d_defconfig → arch/sh/configs/rts7751r2d1_defconfig
View File

@ -1,46 +1,47 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.21-rc1
# Thu Mar 1 16:42:40 2007
# Linux kernel version: 2.6.23-rc2
# Tue Aug 14 18:04:44 2007
#
CONFIG_SUPERH=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
# CONFIG_GENERIC_TIME is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_SYS_SUPPORTS_PCI=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_NO_VIRT_TO_BUS=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_IPC_NS is not set
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_UTS_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
@ -54,31 +55,29 @@ CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_SLAB=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
#
# Loadable module support
#
CONFIG_MODULES=y
# CONFIG_MODULE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_KMOD is not set
#
# Block layer
#
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
@ -96,61 +95,16 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
#
# System type
#
# CONFIG_SH_SOLUTION_ENGINE is not set
# CONFIG_SH_7751_SOLUTION_ENGINE is not set
# CONFIG_SH_7300_SOLUTION_ENGINE is not set
# CONFIG_SH_7343_SOLUTION_ENGINE is not set
# CONFIG_SH_73180_SOLUTION_ENGINE is not set
# CONFIG_SH_7751_SYSTEMH is not set
# CONFIG_SH_HP6XX is not set
# CONFIG_SH_SATURN is not set
# CONFIG_SH_DREAMCAST is not set
# CONFIG_SH_MPC1211 is not set
# CONFIG_SH_SH03 is not set
# CONFIG_SH_SECUREEDGE5410 is not set
# CONFIG_SH_HS7751RVOIP is not set
# CONFIG_SH_7710VOIPGW is not set
CONFIG_SH_RTS7751R2D=y
# CONFIG_SH_R7780RP is not set
# CONFIG_SH_EDOSK7705 is not set
# CONFIG_SH_SH4202_MICRODEV is not set
# CONFIG_SH_LANDISK is not set
# CONFIG_SH_TITAN is not set
# CONFIG_SH_SHMIN is not set
# CONFIG_SH_7206_SOLUTION_ENGINE is not set
# CONFIG_SH_7619_SOLUTION_ENGINE is not set
# CONFIG_SH_UNKNOWN is not set
#
# Processor selection
#
CONFIG_CPU_SH4=y
#
# SH-2 Processor Support
#
# CONFIG_CPU_SUBTYPE_SH7604 is not set
# CONFIG_CPU_SUBTYPE_SH7619 is not set
#
# SH-2A Processor Support
#
# CONFIG_CPU_SUBTYPE_SH7206 is not set
#
# SH-3 Processor Support
#
# CONFIG_CPU_SUBTYPE_SH7300 is not set
# CONFIG_CPU_SUBTYPE_SH7705 is not set
# CONFIG_CPU_SUBTYPE_SH7706 is not set
# CONFIG_CPU_SUBTYPE_SH7707 is not set
# CONFIG_CPU_SUBTYPE_SH7708 is not set
# CONFIG_CPU_SUBTYPE_SH7709 is not set
# CONFIG_CPU_SUBTYPE_SH7710 is not set
#
# SH-4 Processor Support
#
# CONFIG_CPU_SUBTYPE_SH7712 is not set
# CONFIG_CPU_SUBTYPE_SH7750 is not set
# CONFIG_CPU_SUBTYPE_SH7091 is not set
# CONFIG_CPU_SUBTYPE_SH7750R is not set
@ -159,35 +113,30 @@ CONFIG_CPU_SH4=y
CONFIG_CPU_SUBTYPE_SH7751R=y
# CONFIG_CPU_SUBTYPE_SH7760 is not set
# CONFIG_CPU_SUBTYPE_SH4_202 is not set
#
# ST40 Processor Support
#
# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
#
# SH-4A Processor Support
#
# CONFIG_CPU_SUBTYPE_SH7770 is not set
# CONFIG_CPU_SUBTYPE_SH7780 is not set
# CONFIG_CPU_SUBTYPE_SH7785 is not set
#
# SH4AL-DSP Processor Support
#
# CONFIG_CPU_SUBTYPE_SH73180 is not set
# CONFIG_CPU_SUBTYPE_SHX3 is not set
# CONFIG_CPU_SUBTYPE_SH7343 is not set
# CONFIG_CPU_SUBTYPE_SH7722 is not set
#
# Memory management options
#
CONFIG_QUICKLIST=y
CONFIG_MMU=y
CONFIG_PAGE_OFFSET=0x80000000
CONFIG_MEMORY_START=0x0c000000
CONFIG_MEMORY_SIZE=0x04000000
CONFIG_VSYSCALL=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_MAX_ACTIVE_REGIONS=1
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PAGE_SIZE_64KB is not set
@ -197,17 +146,19 @@ CONFIG_FLATMEM_MANUAL=y
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPARSEMEM_STATIC=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_NR_QUICK=2
#
# Cache configuration
#
# CONFIG_SH_DIRECT_MAPPED is not set
# CONFIG_SH_WRITETHROUGH is not set
# CONFIG_SH_OCRAM is not set
CONFIG_CACHE_WRITEBACK=y
# CONFIG_CACHE_WRITETHROUGH is not set
# CONFIG_CACHE_OFF is not set
#
# Processor features
@ -215,7 +166,6 @@ CONFIG_ZONE_DMA_FLAG=0
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_SH_FPU=y
# CONFIG_SH_DSP is not set
# CONFIG_SH_STORE_QUEUES is not set
CONFIG_CPU_HAS_INTEVT=y
CONFIG_CPU_HAS_INTC_IRQ=y
@ -223,17 +173,31 @@ CONFIG_CPU_HAS_SR_RB=y
CONFIG_CPU_HAS_PTEA=y
#
# Timer support
# Board support
#
CONFIG_SH_TMU=y
# CONFIG_SH_7751_SYSTEMH is not set
# CONFIG_SH_SECUREEDGE5410 is not set
# CONFIG_SH_HS7751RVOIP is not set
CONFIG_SH_RTS7751R2D=y
# CONFIG_SH_LANDISK is not set
# CONFIG_SH_TITAN is not set
# CONFIG_SH_LBOX_RE2 is not set
#
# RTS7751R2D options
#
CONFIG_RTS7751R2D_REV11=y
# CONFIG_RTS7751R2D_PLUS is not set
CONFIG_RTS7751R2D_1=y
#
# Timer and clock configuration
#
CONFIG_SH_TMU=y
CONFIG_SH_TIMER_IRQ=16
# CONFIG_NO_IDLE_HZ is not set
CONFIG_SH_PCLK_FREQ=60000000
# CONFIG_TICK_ONESHOT is not set
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
#
# CPU Frequency scaling
@ -244,19 +208,15 @@ CONFIG_SH_PCLK_FREQ=60000000
# DMA support
#
# CONFIG_SH_DMA is not set
# CONFIG_NR_ONCHIP_DMA_CHANNELS is not set
# CONFIG_NR_DMA_CHANNELS_BOOL is not set
#
# Companion Chips
#
CONFIG_VOYAGERGX=y
# CONFIG_HD6446X_SERIES is not set
CONFIG_HEARTBEAT=y
#
# Additional SuperH Device Drivers
#
CONFIG_HEARTBEAT=y
# CONFIG_PUSH_SWITCH is not set
#
@ -268,7 +228,7 @@ CONFIG_HZ_250=y
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
# CONFIG_KEXEC is not set
# CONFIG_SMP is not set
# CONFIG_CRASH_DUMP is not set
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
@ -289,15 +249,12 @@ CONFIG_PCI=y
CONFIG_SH_PCIDMA_NONCOHERENT=y
CONFIG_PCI_AUTO=y
CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
# CONFIG_ARCH_SUPPORTS_MSI is not set
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
#
# PCI Hotplug Support
#
CONFIG_HOTPLUG_PCI=y
# CONFIG_HOTPLUG_PCI_FAKE is not set
# CONFIG_HOTPLUG_PCI_CPCI is not set
@ -307,14 +264,8 @@ CONFIG_HOTPLUG_PCI=y
# Executable file formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_FLAT is not set
# CONFIG_BINFMT_MISC is not set
#
# Power management options (EXPERIMENTAL)
#
# CONFIG_PM is not set
#
# Networking
#
@ -323,7 +274,6 @@ CONFIG_NET=y
#
# Networking options
#
# CONFIG_NETDEBUG is not set
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
@ -360,20 +310,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
#
# DCCP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_DCCP is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_SCTP is not set
#
# TIPC Configuration (EXPERIMENTAL)
#
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
@ -399,8 +337,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_IEEE80211 is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
CONFIG_WIRELESS_EXT=y
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
@ -413,31 +360,10 @@ CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=m
# CONFIG_SYS_HYPERVISOR is not set
#
# Connector - unified userspace <-> kernelspace linker
#
# CONFIG_CONNECTOR is not set
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNPACPI is not set
#
# Block devices
#
# CONFIG_BLK_CPQ_DA is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
@ -449,19 +375,13 @@ CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
#
# Misc devices
#
CONFIG_MISC_DEVICES=y
# CONFIG_PHANTOM is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_SGI_IOC4 is not set
# CONFIG_TIFM_CORE is not set
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
@ -469,6 +389,7 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
@ -490,6 +411,7 @@ CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
@ -497,12 +419,8 @@ CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
#
# SCSI low-level drivers
#
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_3W_9XXX is not set
@ -512,7 +430,6 @@ CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
@ -535,10 +452,6 @@ CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_NSP32 is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_SRP is not set
#
# Serial ATA (prod) and Parallel ATA (experimental) drivers
#
CONFIG_ATA=y
# CONFIG_ATA_NONSTANDARD is not set
# CONFIG_SATA_AHCI is not set
@ -561,6 +474,7 @@ CONFIG_ATA=y
# CONFIG_PATA_AMD is not set
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CS5520 is not set
# CONFIG_PATA_CS5530 is not set
@ -593,10 +507,6 @@ CONFIG_ATA=y
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set
CONFIG_PATA_PLATFORM=y
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
@ -610,35 +520,18 @@ CONFIG_PATA_PLATFORM=y
#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_IEEE1394 is not set
#
# I2O device support
#
# CONFIG_I2O is not set
#
# Network device support
#
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
#
# PHY device support
#
# CONFIG_PHYLIB is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_STNIC is not set
@ -647,10 +540,6 @@ CONFIG_MII=y
# CONFIG_CASSINI is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_SMC91X is not set
#
# Tulip family network device support
#
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
CONFIG_NET_PCI=y
@ -677,10 +566,7 @@ CONFIG_8139TOO=y
# CONFIG_TLAN is not set
# CONFIG_VIA_RHINE is not set
# CONFIG_SC92031 is not set
#
# Ethernet (1000 Mbit)
#
CONFIG_NETDEV_1000=y
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
@ -691,61 +577,26 @@ CONFIG_8139TOO=y
# CONFIG_SIS190 is not set
# CONFIG_SKGE is not set
# CONFIG_SKY2 is not set
# CONFIG_SK98LIN is not set
# CONFIG_VIA_VELOCITY is not set
# CONFIG_TIGON3 is not set
# CONFIG_BNX2 is not set
# CONFIG_QLA3XXX is not set
# CONFIG_ATL1 is not set
#
# Ethernet (10000 Mbit)
#
CONFIG_NETDEV_10000=y
# CONFIG_CHELSIO_T1 is not set
# CONFIG_CHELSIO_T3 is not set
# CONFIG_IXGB is not set
# CONFIG_S2IO is not set
# CONFIG_MYRI10GE is not set
# CONFIG_NETXEN_NIC is not set
#
# Token Ring devices
#
# CONFIG_MLX4_CORE is not set
# CONFIG_TR is not set
#
# Wireless LAN (non-hamradio)
#
CONFIG_NET_RADIO=y
# CONFIG_NET_WIRELESS_RTNETLINK is not set
#
# Obsolete Wireless cards support (pre-802.11)
#
# CONFIG_STRIP is not set
#
# Wireless 802.11b ISA/PCI cards support
#
# CONFIG_IPW2100 is not set
# CONFIG_IPW2200 is not set
CONFIG_HERMES=m
# CONFIG_PLX_HERMES is not set
# CONFIG_TMD_HERMES is not set
# CONFIG_NORTEL_HERMES is not set
# CONFIG_PCI_HERMES is not set
# CONFIG_ATMEL is not set
#
# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support
#
# CONFIG_PRISM54 is not set
# CONFIG_HOSTAP is not set
CONFIG_NET_WIRELESS=y
#
# Wan interfaces
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
@ -756,15 +607,7 @@ CONFIG_NET_WIRELESS=y
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
@ -772,6 +615,7 @@ CONFIG_NET_WIRELESS=y
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
@ -788,6 +632,7 @@ CONFIG_INPUT=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
@ -828,32 +673,15 @@ CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
CONFIG_HW_RANDOM=y
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
#
# I2C support
#
CONFIG_DEVPORT=y
# CONFIG_I2C is not set
#
@ -861,21 +689,24 @@ CONFIG_HW_RANDOM=y
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#
# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_SENSORS_ABITUGURU is not set
# CONFIG_SENSORS_ABITUGURU3 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
#
@ -887,22 +718,31 @@ CONFIG_MFD_SM501=y
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
# CONFIG_DVB_CORE is not set
CONFIG_DAB=y
#
# Graphics support
#
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_SYS_FOPS is not set
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
@ -910,14 +750,13 @@ CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_TILEBLITTING is not set
#
# Frambuffer hardware drivers
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_EPSON1355 is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
@ -932,7 +771,10 @@ CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
CONFIG_FB_SM501=y
# CONFIG_FB_VIRTUAL is not set
@ -941,14 +783,11 @@ CONFIG_FB_SM501=y
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
#
# Logo configuration
#
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
@ -1048,35 +887,34 @@ CONFIG_SND_AC97_CODEC=m
# CONFIG_SND_VIA82XX_MODEM is not set
# CONFIG_SND_VX222 is not set
CONFIG_SND_YMFPCI=m
CONFIG_SND_YMFPCI_FIRMWARE_IN_KERNEL=y
# CONFIG_SND_AC97_POWER_SAVE is not set
#
# SoC audio support
# SUPERH devices
#
#
# System on Chip audio support
#
# CONFIG_SND_SOC is not set
#
# SoC Audio support for SuperH
#
#
# Open Sound System
#
CONFIG_SOUND_PRIME=m
# CONFIG_OBSOLETE_OSS is not set
# CONFIG_SOUND_BT878 is not set
# CONFIG_SOUND_ICH is not set
# CONFIG_SOUND_TRIDENT is not set
# CONFIG_SOUND_MSNDCLAS is not set
# CONFIG_SOUND_MSNDPIN is not set
# CONFIG_SOUND_VIA82CXXX is not set
CONFIG_AC97_BUS=m
#
# HID Devices
#
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
#
# USB support
#
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB_ARCH_HAS_EHCI=y
@ -1090,37 +928,9 @@ CONFIG_USB_ARCH_HAS_EHCI=y
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# MMC/SD Card support
#
# CONFIG_MMC is not set
#
# LED devices
#
# CONFIG_NEW_LEDS is not set
#
# LED drivers
#
#
# LED Triggers
#
#
# InfiniBand support
#
# CONFIG_INFINIBAND is not set
#
# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
#
#
# Real Time Clock
#
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
@ -1134,17 +944,27 @@ CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# RTC drivers
# SPI RTC drivers
#
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_M48T86 is not set
CONFIG_RTC_DRV_SH=y
# CONFIG_RTC_DRV_TEST is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_SH=y
#
# DMA Engine support
#
@ -1159,12 +979,9 @@ CONFIG_RTC_DRV_SH=y
#
#
# Auxiliary Display support
#
#
# Virtualization
# Userspace I/O
#
# CONFIG_UIO is not set
#
# File systems
@ -1247,7 +1064,6 @@ CONFIG_RAMFS=y
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
# CONFIG_9P_FS is not set
#
# Partition Types
@ -1321,7 +1137,6 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_SH_STANDARD_BIOS is not set
CONFIG_EARLY_SCIF_CONSOLE=y
@ -1334,10 +1149,6 @@ CONFIG_EARLY_PRINTK=y
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
#
@ -1346,8 +1157,11 @@ CONFIG_EARLY_PRINTK=y
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

1167
arch/sh/configs/rts7751r2dplus_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

227
arch/sh/configs/se7206_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.22-rc4
# Fri Jun 15 19:37:46 2007
# Linux kernel version: 2.6.23-rc4
# Thu Sep 13 16:40:16 2007
#
CONFIG_SUPERH=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
@ -17,25 +17,22 @@ CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_NO_VIRT_TO_BUS=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SYSVIPC is not set
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_UTS_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
@ -60,23 +57,17 @@ CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_SLAB=y
# CONFIG_SLUB is not set
CONFIG_SLUB_DEBUG=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
CONFIG_TINY_SHMEM=y
CONFIG_BASE_SMALL=1
#
# Loadable module support
#
# CONFIG_MODULES is not set
#
# Block layer
#
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
@ -98,7 +89,6 @@ CONFIG_CPU_SH2=y
CONFIG_CPU_SH2A=y
# CONFIG_CPU_SUBTYPE_SH7619 is not set
CONFIG_CPU_SUBTYPE_SH7206=y
# CONFIG_CPU_SUBTYPE_SH7300 is not set
# CONFIG_CPU_SUBTYPE_SH7705 is not set
# CONFIG_CPU_SUBTYPE_SH7706 is not set
# CONFIG_CPU_SUBTYPE_SH7707 is not set
@ -106,6 +96,7 @@ CONFIG_CPU_SUBTYPE_SH7206=y
# CONFIG_CPU_SUBTYPE_SH7709 is not set
# CONFIG_CPU_SUBTYPE_SH7710 is not set
# CONFIG_CPU_SUBTYPE_SH7712 is not set
# CONFIG_CPU_SUBTYPE_SH7720 is not set
# CONFIG_CPU_SUBTYPE_SH7750 is not set
# CONFIG_CPU_SUBTYPE_SH7091 is not set
# CONFIG_CPU_SUBTYPE_SH7750R is not set
@ -119,7 +110,7 @@ CONFIG_CPU_SUBTYPE_SH7206=y
# CONFIG_CPU_SUBTYPE_SH7770 is not set
# CONFIG_CPU_SUBTYPE_SH7780 is not set
# CONFIG_CPU_SUBTYPE_SH7785 is not set
# CONFIG_CPU_SUBTYPE_SH73180 is not set
# CONFIG_CPU_SUBTYPE_SHX3 is not set
# CONFIG_CPU_SUBTYPE_SH7343 is not set
# CONFIG_CPU_SUBTYPE_SH7722 is not set
@ -136,15 +127,16 @@ CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_MAX_ACTIVE_REGIONS=1
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PAGE_SIZE_64KB is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_FLATMEM_MANUAL is not set
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM=y
CONFIG_HAVE_MEMORY_PRESENT=y
CONFIG_SPARSEMEM_STATIC=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
@ -155,7 +147,9 @@ CONFIG_NR_QUICK=2
# Cache configuration
#
# CONFIG_SH_DIRECT_MAPPED is not set
# CONFIG_SH_WRITETHROUGH is not set
CONFIG_CACHE_WRITEBACK=y
# CONFIG_CACHE_WRITETHROUGH is not set
# CONFIG_CACHE_OFF is not set
#
# Processor features
@ -163,8 +157,6 @@ CONFIG_NR_QUICK=2
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_CPU_BIG_ENDIAN=y
# CONFIG_SH_FPU_EMU is not set
# CONFIG_SH_DSP is not set
CONFIG_CPU_HAS_IPR_IRQ=y
#
# Board support
@ -185,12 +177,23 @@ CONFIG_SH_CLK_MD=6
#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_TABLE=y
# CONFIG_CPU_FREQ_DEBUG is not set
CONFIG_CPU_FREQ_STAT=y
# CONFIG_CPU_FREQ_STAT_DETAILS is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
# CONFIG_SH_CPU_FREQ is not set
#
# DMA support
#
# CONFIG_SH_DMA is not set
#
# Companion Chips
@ -199,17 +202,17 @@ CONFIG_SH_CLK_MD=6
#
# Additional SuperH Device Drivers
#
# CONFIG_HEARTBEAT is not set
CONFIG_HEARTBEAT=y
# CONFIG_PUSH_SWITCH is not set
#
# Kernel features
#
CONFIG_HZ_100=y
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=100
CONFIG_HZ_1000=y
CONFIG_HZ=1000
# CONFIG_KEXEC is not set
# CONFIG_CRASH_DUMP is not set
CONFIG_PREEMPT_NONE=y
@ -221,11 +224,13 @@ CONFIG_PREEMPT_NONE=y
#
CONFIG_ZERO_PAGE_OFFSET=0x00001000
CONFIG_BOOT_LINK_OFFSET=0x00800000
# CONFIG_CMDLINE_BOOL is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttySC3,115200 earlyprintk=serial ignore_loglevel"
#
# Bus options
#
# CONFIG_CF_ENABLER is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
#
@ -315,6 +320,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
@ -325,11 +331,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
#
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
#
# Connector - unified userspace <-> kernelspace linker
#
# CONFIG_CONNECTOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
@ -411,31 +415,16 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=4
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNPACPI is not set
#
# Block devices
#
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
#
# Misc devices
#
# CONFIG_BLINK is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_IDE is not set
#
@ -443,27 +432,18 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=4
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Network device support
#
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_PHYLIB is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_STNIC is not set
@ -483,15 +463,7 @@ CONFIG_NETDEV_10000=y
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
@ -499,6 +471,7 @@ CONFIG_NETDEV_10000=y
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
@ -546,19 +519,11 @@ CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_UNIX98_PTYS is not set
# CONFIG_LEGACY_PTYS is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
@ -567,11 +532,8 @@ CONFIG_SERIAL_CORE_CONSOLE=y
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
#
@ -596,25 +558,21 @@ CONFIG_DAB=y
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=y
# CONFIG_FB is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# HID Devices
#
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
#
# USB support
#
# CONFIG_USB_ARCH_HAS_HCD is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@ -625,31 +583,7 @@ CONFIG_HID=y
#
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
#
# LED devices
#
# CONFIG_NEW_LEDS is not set
#
# LED drivers
#
#
# LED Triggers
#
#
# InfiniBand support
#
#
# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
#
#
# Real Time Clock
#
# CONFIG_RTC_CLASS is not set
#
@ -665,6 +599,11 @@ CONFIG_HID=y
# DMA Devices
#
#
# Userspace I/O
#
# CONFIG_UIO is not set
#
# File systems
#
@ -736,7 +675,6 @@ CONFIG_RAMFS=y
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
# CONFIG_9P_FS is not set
#
# Partition Types
@ -752,12 +690,12 @@ CONFIG_MSDOS_PARTITION=y
#
# Distributed Lock Manager
#
# CONFIG_DLM is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
CONFIG_PROFILING=y
# CONFIG_OPROFILE is not set
#
# Kernel hacking
@ -768,19 +706,41 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
CONFIG_SLUB_DEBUG_ON=y
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
CONFIG_DEBUG_SPINLOCK_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
CONFIG_FRAME_POINTER=y
CONFIG_FORCED_INLINING=y
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SH_STANDARD_BIOS is not set
# CONFIG_EARLY_SCIF_CONSOLE is not set
CONFIG_EARLY_SCIF_CONSOLE=y
CONFIG_EARLY_SCIF_CONSOLE_PORT=0xfffe9800
CONFIG_EARLY_PRINTK=y
# CONFIG_DEBUG_BOOTMEM is not set
CONFIG_DEBUG_STACKOVERFLOW=y
CONFIG_DEBUG_STACK_USAGE=y
# CONFIG_4KSTACKS is not set
#
# Security options
#
# CONFIG_KEYS is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
#
@ -791,6 +751,7 @@ CONFIG_BITREVERSE=y
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_HAS_IOMEM=y

450
arch/sh/configs/shx3_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.22-rc4
# Wed Jun 20 14:09:27 2007
# Linux kernel version: 2.6.23-rc7
# Fri Sep 21 19:07:30 2007
#
CONFIG_SUPERH=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
@ -13,32 +13,33 @@ CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_SYS_SUPPORTS_SMP=y
CONFIG_SYS_SUPPORTS_NUMA=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_NO_VIRT_TO_BUS=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# Code maturity level options
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_IPC_NS is not set
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
# CONFIG_UTS_NS is not set
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
# CONFIG_AUDIT is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
@ -63,34 +64,26 @@ CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLAB is not set
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_SLOB=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
#
# Block layer
#
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
@ -113,7 +106,6 @@ CONFIG_CPU_SH4A=y
CONFIG_CPU_SHX3=y
# CONFIG_CPU_SUBTYPE_SH7619 is not set
# CONFIG_CPU_SUBTYPE_SH7206 is not set
# CONFIG_CPU_SUBTYPE_SH7300 is not set
# CONFIG_CPU_SUBTYPE_SH7705 is not set
# CONFIG_CPU_SUBTYPE_SH7706 is not set
# CONFIG_CPU_SUBTYPE_SH7707 is not set
@ -121,6 +113,7 @@ CONFIG_CPU_SHX3=y
# CONFIG_CPU_SUBTYPE_SH7709 is not set
# CONFIG_CPU_SUBTYPE_SH7710 is not set
# CONFIG_CPU_SUBTYPE_SH7712 is not set
# CONFIG_CPU_SUBTYPE_SH7720 is not set
# CONFIG_CPU_SUBTYPE_SH7750 is not set
# CONFIG_CPU_SUBTYPE_SH7091 is not set
# CONFIG_CPU_SUBTYPE_SH7750R is not set
@ -135,7 +128,6 @@ CONFIG_CPU_SHX3=y
# CONFIG_CPU_SUBTYPE_SH7780 is not set
# CONFIG_CPU_SUBTYPE_SH7785 is not set
CONFIG_CPU_SUBTYPE_SHX3=y
# CONFIG_CPU_SUBTYPE_SH73180 is not set
# CONFIG_CPU_SUBTYPE_SH7343 is not set
# CONFIG_CPU_SUBTYPE_SH7722 is not set
@ -148,12 +140,15 @@ CONFIG_PAGE_OFFSET=0x80000000
CONFIG_MEMORY_START=0x0c000000
CONFIG_MEMORY_SIZE=0x04000000
CONFIG_VSYSCALL=y
# CONFIG_NUMA is not set
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_MAX_ACTIVE_REGIONS=1
CONFIG_MAX_ACTIVE_REGIONS=6
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_MEMORY_PROBE=y
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PAGE_SIZE_64KB is not set
@ -163,12 +158,14 @@ CONFIG_HUGETLB_PAGE_SIZE_64K=y
# CONFIG_HUGETLB_PAGE_SIZE_4MB is not set
# CONFIG_HUGETLB_PAGE_SIZE_64MB is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_FLATMEM_MANUAL is not set
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM=y
CONFIG_HAVE_MEMORY_PRESENT=y
CONFIG_SPARSEMEM_STATIC=y
CONFIG_MEMORY_HOTPLUG=y
CONFIG_MEMORY_HOTPLUG_SPARSE=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
@ -178,24 +175,25 @@ CONFIG_NR_QUICK=2
# Cache configuration
#
# CONFIG_SH_DIRECT_MAPPED is not set
# CONFIG_SH_WRITETHROUGH is not set
# CONFIG_CACHE_WRITEBACK is not set
# CONFIG_CACHE_WRITETHROUGH is not set
CONFIG_CACHE_OFF=y
#
# Processor features
#
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_CPU_BIG_ENDIAN is not set
# CONFIG_SH_FPU is not set
# CONFIG_SH_FPU_EMU is not set
CONFIG_SH_DSP=y
CONFIG_SH_FPU=y
CONFIG_SH_STORE_QUEUES=y
CONFIG_CPU_HAS_INTEVT=y
CONFIG_CPU_HAS_INTC2_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
CONFIG_CPU_HAS_FPU=y
#
# Board support
#
CONFIG_SH_X3PROTO=y
#
# Timer and clock configuration
@ -204,13 +202,25 @@ CONFIG_SH_TMU=y
CONFIG_SH_TIMER_IRQ=16
CONFIG_SH_PCLK_FREQ=50000000
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_TABLE=y
# CONFIG_CPU_FREQ_DEBUG is not set
CONFIG_CPU_FREQ_STAT=y
# CONFIG_CPU_FREQ_STAT_DETAILS is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_USERSPACE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=m
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_SH_CPU_FREQ=y
#
# DMA support
@ -237,6 +247,7 @@ CONFIG_HZ_250=y
CONFIG_HZ=250
CONFIG_KEXEC=y
# CONFIG_CRASH_DUMP is not set
# CONFIG_SMP is not set
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
@ -249,7 +260,7 @@ CONFIG_ZERO_PAGE_OFFSET=0x00001000
CONFIG_BOOT_LINK_OFFSET=0x00800000
# CONFIG_UBC_WAKEUP is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttySC0,115200 ip=192.168.1.2:::255.255.255.0 root=/dev/nfs nfsroot=192.168.1.1:/exports/devel/rfs/mobiler noaliencache earlyprintk=bios ignore_loglevel"
CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=bios ignore_loglevel"
#
# Bus options
@ -265,12 +276,106 @@ CONFIG_CMDLINE="console=ttySC0,115200 ip=192.168.1.2:::255.255.255.0 root=/dev/n
# Executable file formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_BINFMT_MISC=y
#
# Networking
#
# CONFIG_NET is not set
CONFIG_NET=y
#
# Networking options
#
# CONFIG_PACKET is not set
# CONFIG_UNIX is not set
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
CONFIG_INET_TUNNEL=m
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=m
# CONFIG_IPV6_PRIVACY is not set
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
# CONFIG_INET6_AH is not set
# CONFIG_INET6_ESP is not set
# CONFIG_INET6_IPCOMP is not set
# CONFIG_IPV6_MIP6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
CONFIG_INET6_XFRM_MODE_TRANSPORT=m
CONFIG_INET6_XFRM_MODE_TUNNEL=m
CONFIG_INET6_XFRM_MODE_BEET=m
# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
CONFIG_IPV6_SIT=m
# CONFIG_IPV6_TUNNEL is not set
# CONFIG_IPV6_MULTIPLE_TABLES is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
@ -285,37 +390,21 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
#
# Connector - unified userspace <-> kernelspace linker
#
# CONFIG_CONNECTOR is not set
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNPACPI is not set
#
# Block devices
#
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
#
# Misc devices
#
# CONFIG_BLINK is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_IDE is not set
#
@ -323,6 +412,7 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
@ -351,73 +441,54 @@ CONFIG_SCSI_WAIT_SCAN=m
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
#
# SCSI low-level drivers
#
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_SCSI_DEBUG is not set
CONFIG_ATA=y
# CONFIG_ATA_NONSTANDARD is not set
CONFIG_PATA_PLATFORM=y
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_STNIC is not set
CONFIG_SMC91X=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# ISDN subsystem
#
#
# Telephony Support
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
# CONFIG_INPUT is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
@ -442,19 +513,18 @@ CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
#
# IPMI
# Watchdog Device Drivers
#
# CONFIG_IPMI_HANDLER is not set
# CONFIG_WATCHDOG is not set
CONFIG_HW_RANDOM=y
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_SH_WDT is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
@ -463,11 +533,8 @@ CONFIG_HW_RANDOM=y
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
#
@ -479,6 +546,7 @@ CONFIG_HW_RANDOM=y
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
# CONFIG_DAB is not set
#
@ -491,24 +559,18 @@ CONFIG_HW_RANDOM=y
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
# CONFIG_FB is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# HID Devices
#
# CONFIG_HID is not set
#
# USB support
#
# CONFIG_USB_ARCH_HAS_HCD is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@ -517,68 +579,32 @@ CONFIG_HW_RANDOM=y
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
CONFIG_USB_GADGET_SELECTED=y
# CONFIG_USB_GADGET_AMD5536UDC is not set
# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_PXA2XX is not set
CONFIG_USB_GADGET_M66592=y
CONFIG_USB_M66592=y
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
# CONFIG_USB_GADGET_S3C2410 is not set
# CONFIG_USB_GADGET_AT91 is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
CONFIG_USB_GADGET_DUALSPEED=y
# CONFIG_USB_ZERO is not set
# CONFIG_USB_ETH is not set
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FILE_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_MMC is not set
#
# LED devices
#
# CONFIG_NEW_LEDS is not set
#
# LED drivers
#
#
# LED Triggers
#
#
# InfiniBand support
#
#
# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
#
#
# Real Time Clock
#
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
#
# SPI RTC drivers
#
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_SH=y
# CONFIG_RTC_CLASS is not set
#
# DMA Engine support
@ -593,6 +619,11 @@ CONFIG_RTC_DRV_SH=y
# DMA Devices
#
#
# Userspace I/O
#
CONFIG_UIO=m
#
# File systems
#
@ -612,6 +643,7 @@ CONFIG_FS_MBCACHE=y
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
@ -666,6 +698,17 @@ CONFIG_RAMFS=y
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
# CONFIG_NFS_FS is not set
# CONFIG_NFSD is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
@ -677,6 +720,11 @@ CONFIG_MSDOS_PARTITION=y
#
# CONFIG_NLS is not set
#
# Distributed Lock Manager
#
# CONFIG_DLM is not set
#
# Profiling support
#
@ -687,31 +735,28 @@ CONFIG_PROFILING=y
# Kernel hacking
#
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_TIME is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_SOFTLOCKUP=y
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
CONFIG_DEBUG_SLAB=y
CONFIG_DEBUG_SLAB_LEAK=y
CONFIG_DEBUG_PREEMPT=y
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_LOCK_ALLOC=y
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
CONFIG_LOCKDEP=y
CONFIG_DEBUG_LOCKDEP=y
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
CONFIG_STACKTRACE=y
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_INFO is not set
@ -735,10 +780,6 @@ CONFIG_DEBUG_STACK_USAGE=y
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
#
@ -749,6 +790,7 @@ CONFIG_BITREVERSE=y
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y

1
arch/sh/drivers/dma/Kconfig
View File

@ -12,6 +12,7 @@ config SH_DMA
config NR_ONCHIP_DMA_CHANNELS
int
depends on SH_DMA
default "6" if CPU_SUBTYPE_SH7720
default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
default "12" if CPU_SUBTYPE_SH7780
default "4"

13
arch/sh/drivers/dma/dma-sh.c
View File

@ -24,13 +24,19 @@ static int dmte_irq_map[] = {
DMTE1_IRQ,
DMTE2_IRQ,
DMTE3_IRQ,
#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
defined(CONFIG_CPU_SUBTYPE_SH7760) || \
defined(CONFIG_CPU_SUBTYPE_SH7709) || \
defined(CONFIG_CPU_SUBTYPE_SH7780)
DMTE4_IRQ,
DMTE5_IRQ,
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
defined(CONFIG_CPU_SUBTYPE_SH7760) || \
defined(CONFIG_CPU_SUBTYPE_SH7780)
DMTE6_IRQ,
DMTE7_IRQ,
DMTE7_IRQ,
#endif
};
@ -196,7 +202,8 @@ static int sh_dmac_get_dma_residue(struct dma_channel *chan)
return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan);
}
#ifdef CONFIG_CPU_SUBTYPE_SH7780
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7780)
#define dmaor_read_reg() ctrl_inw(DMAOR)
#define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
#else

72
arch/sh/drivers/heartbeat.c
View File

@ -24,24 +24,44 @@
#include <linux/sched.h>
#include <linux/timer.h>
#include <linux/io.h>
#include <asm/heartbeat.h>
#define DRV_NAME "heartbeat"
#define DRV_VERSION "0.1.0"
#define DRV_VERSION "0.1.1"
struct heartbeat_data {
void __iomem *base;
unsigned char bit_pos[8];
struct timer_list timer;
};
static unsigned char default_bit_pos[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
static inline void heartbeat_toggle_bit(struct heartbeat_data *hd,
unsigned bit, unsigned int inverted)
{
unsigned int new;
new = (1 << hd->bit_pos[bit]);
if (inverted)
new = ~new;
switch (hd->regsize) {
case 32:
iowrite32(new, hd->base);
break;
case 16:
iowrite16(new, hd->base);
break;
default:
iowrite8(new, hd->base);
break;
}
}
static void heartbeat_timer(unsigned long data)
{
struct heartbeat_data *hd = (struct heartbeat_data *)data;
static unsigned bit = 0, up = 1;
ctrl_outw(1 << hd->bit_pos[bit], (unsigned long)hd->base);
heartbeat_toggle_bit(hd, bit, hd->flags & HEARTBEAT_INVERTED);
bit += up;
if ((bit == 0) || (bit == ARRAY_SIZE(hd->bit_pos)-1))
if ((bit == 0) || (bit == (hd->nr_bits)-1))
up = -up;
mod_timer(&hd->timer, jiffies + (110 - ((300 << FSHIFT) /
@ -64,21 +84,31 @@ static int heartbeat_drv_probe(struct platform_device *pdev)
return -EINVAL;
}
hd = kmalloc(sizeof(struct heartbeat_data), GFP_KERNEL);
if (unlikely(!hd))
return -ENOMEM;
if (pdev->dev.platform_data) {
memcpy(hd->bit_pos, pdev->dev.platform_data,
ARRAY_SIZE(hd->bit_pos));
hd = pdev->dev.platform_data;
} else {
int i;
for (i = 0; i < ARRAY_SIZE(hd->bit_pos); i++)
hd->bit_pos[i] = i;
hd = kzalloc(sizeof(struct heartbeat_data), GFP_KERNEL);
if (unlikely(!hd))
return -ENOMEM;
}
hd->base = (void __iomem *)(unsigned long)res->start;
hd->base = ioremap_nocache(res->start, res->end - res->start + 1);
if (!unlikely(hd->base)) {
dev_err(&pdev->dev, "ioremap failed\n");
if (!pdev->dev.platform_data)
kfree(hd);
return -ENXIO;
}
if (!hd->nr_bits) {
hd->bit_pos = default_bit_pos;
hd->nr_bits = ARRAY_SIZE(default_bit_pos);
}
if (!hd->regsize)
hd->regsize = 8; /* default access size */
setup_timer(&hd->timer, heartbeat_timer, (unsigned long)hd);
platform_set_drvdata(pdev, hd);
@ -91,10 +121,12 @@ static int heartbeat_drv_remove(struct platform_device *pdev)
struct heartbeat_data *hd = platform_get_drvdata(pdev);
del_timer_sync(&hd->timer);
iounmap(hd->base);
platform_set_drvdata(pdev, NULL);
kfree(hd);
if (!pdev->dev.platform_data)
kfree(hd);
return 0;
}

8
arch/sh/drivers/pci/ops-rts7751r2d.c
View File

@ -19,10 +19,10 @@
#include "pci-sh4.h"
static u8 rts7751r2d_irq_tab[] __initdata = {
IRQ_PCISLOT1,
IRQ_PCISLOT2,
IRQ_PCMCIA,
IRQ_PCIETH,
IRQ_PCI_INTA,
IRQ_PCI_INTB,
IRQ_PCI_INTC,
IRQ_PCI_INTD,
};
int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)

13
arch/sh/drivers/pci/pci-sh7780.c
View File

@ -79,19 +79,6 @@ static int __init sh7780_pci_init(void)
ctrl_outl(0xAAAA0000, INTC_ICR1);
/* INTPRI: priority=3(all) */
ctrl_outl(0x33333333, INTC_INTPRI);
} else {
/* INTC SH-4 Mode */
ctrl_outl(0x00200000, INTC_ICR0);
/* enable PCIINTA - PCIINTD */
ctrl_outl(0x00078000, INTC_INT2MSKCR);
/* disable IRL4-7 Interrupt */
ctrl_outl(0x40000000, INTC_INTMSK1);
/* disable IRL4-7 Interrupt */
ctrl_outl(0x0000fffe, INTC_INTMSK2);
/* enable IRL0-3 Interrupt */
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
/* enable IRL0-3 Interrupt */
ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
}
if ((ret = sh4_pci_check_direct()) != 0)

2
arch/sh/kernel/cpu/clock.c
View File

@ -83,6 +83,8 @@ static void propagate_rate(struct clk *clk)
continue;
if (likely(clkp->ops && clkp->ops->recalc))
clkp->ops->recalc(clkp);
if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
propagate_rate(clkp);
}
}

27
arch/sh/kernel/cpu/init.c
View File

@ -22,6 +22,7 @@
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/ubc.h>
#include <asm/smp.h>
/*
* Generic wrapper for command line arguments to disable on-chip
@ -143,12 +144,15 @@ static void __init cache_init(void)
flags &= ~CCR_CACHE_EMODE;
#endif
#ifdef CONFIG_SH_WRITETHROUGH
/* Turn on Write-through caching */
#if defined(CONFIG_CACHE_WRITETHROUGH)
/* Write-through */
flags |= CCR_CACHE_WT;
#else
/* .. or default to Write-back */
#elif defined(CONFIG_CACHE_WRITEBACK)
/* Write-back */
flags |= CCR_CACHE_CB;
#else
/* Off */
flags &= ~CCR_CACHE_ENABLE;
#endif
ctrl_outl(flags, CCR);
@ -213,8 +217,11 @@ static void __init dsp_init(void)
* Each processor family is still responsible for doing its own probing
* and cache configuration in detect_cpu_and_cache_system().
*/
asmlinkage void __init sh_cpu_init(void)
asmlinkage void __cpuinit sh_cpu_init(void)
{
current_thread_info()->cpu = hard_smp_processor_id();
/* First, probe the CPU */
detect_cpu_and_cache_system();
@ -224,9 +231,10 @@ asmlinkage void __init sh_cpu_init(void)
/* Init the cache */
cache_init();
shm_align_mask = max_t(unsigned long,
current_cpu_data.dcache.way_size - 1,
PAGE_SIZE - 1);
if (raw_smp_processor_id() == 0)
shm_align_mask = max_t(unsigned long,
current_cpu_data.dcache.way_size - 1,
PAGE_SIZE - 1);
/* Disable the FPU */
if (fpu_disabled) {
@ -265,6 +273,7 @@ asmlinkage void __init sh_cpu_init(void)
* like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB. So ..
* we wake it up and hope that all is well.
*/
ubc_wakeup();
if (raw_smp_processor_id() == 0)
ubc_wakeup();
speculative_execution_init();
}

4
arch/sh/kernel/cpu/irq/Makefile
View File

@ -1,9 +1,7 @@
#
# Makefile for the Linux/SuperH CPU-specifc IRQ handlers.
#
obj-y += imask.o
obj-y += imask.o intc.o
obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o
obj-$(CONFIG_CPU_HAS_MASKREG_IRQ) += maskreg.o
obj-$(CONFIG_CPU_HAS_INTC_IRQ) += intc.o
obj-$(CONFIG_CPU_HAS_INTC2_IRQ) += intc2.o

578
arch/sh/kernel/cpu/irq/intc.c
View File

@ -20,145 +20,258 @@
#include <linux/module.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>
#define _INTC_MK(fn, idx, bit, value) \
((fn) << 24 | ((value) << 16) | ((idx) << 8) | (bit))
#define _INTC_FN(h) (h >> 24)
#define _INTC_VALUE(h) ((h >> 16) & 0xff)
#define _INTC_IDX(h) ((h >> 8) & 0xff)
#define _INTC_BIT(h) (h & 0xff)
#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
((addr_e) << 16) | ((addr_d << 24)))
#define _INTC_PTR(desc, member, data) \
(desc->member + _INTC_IDX(data))
#define _INTC_SHIFT(h) (h & 0x1f)
#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
#define _INTC_FN(h) ((h >> 9) & 0xf)
#define _INTC_MODE(h) ((h >> 13) & 0x7)
#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
static inline struct intc_desc *get_intc_desc(unsigned int irq)
struct intc_handle_int {
unsigned int irq;
unsigned long handle;
};
struct intc_desc_int {
unsigned long *reg;
#ifdef CONFIG_SMP
unsigned long *smp;
#endif
unsigned int nr_reg;
struct intc_handle_int *prio;
unsigned int nr_prio;
struct intc_handle_int *sense;
unsigned int nr_sense;
struct irq_chip chip;
};
#ifdef CONFIG_SMP
#define IS_SMP(x) x.smp
#define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
#define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
#else
#define IS_SMP(x) 0
#define INTC_REG(d, x, c) (d->reg[(x)])
#define SMP_NR(d, x) 1
#endif
static unsigned int intc_prio_level[NR_IRQS]; /* for now */
static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
{
struct irq_chip *chip = get_irq_chip(irq);
return (void *)((char *)chip - offsetof(struct intc_desc, chip));
return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
}
static inline unsigned int set_field(unsigned int value,
unsigned int field_value,
unsigned int width,
unsigned int shift)
unsigned int handle)
{
unsigned int width = _INTC_WIDTH(handle);
unsigned int shift = _INTC_SHIFT(handle);
value &= ~(((1 << width) - 1) << shift);
value |= field_value << shift;
return value;
}
static inline unsigned int set_prio_field(struct intc_desc *desc,
unsigned int value,
unsigned int priority,
unsigned int data)
static void write_8(unsigned long addr, unsigned long h, unsigned long data)
{
unsigned int width = _INTC_PTR(desc, prio_regs, data)->field_width;
return set_field(value, priority, width, _INTC_BIT(data));
ctrl_outb(set_field(0, data, h), addr);
}
static void disable_prio_16(struct intc_desc *desc, unsigned int data)
static void write_16(unsigned long addr, unsigned long h, unsigned long data)
{
unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
ctrl_outw(set_prio_field(desc, ctrl_inw(addr), 0, data), addr);
ctrl_outw(set_field(0, data, h), addr);
}
static void enable_prio_16(struct intc_desc *desc, unsigned int data)
static void write_32(unsigned long addr, unsigned long h, unsigned long data)
{
unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
unsigned int prio = _INTC_VALUE(data);
ctrl_outw(set_prio_field(desc, ctrl_inw(addr), prio, data), addr);
ctrl_outl(set_field(0, data, h), addr);
}
static void disable_prio_32(struct intc_desc *desc, unsigned int data)
static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
{
unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
ctrl_outl(set_prio_field(desc, ctrl_inl(addr), 0, data), addr);
ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
}
static void enable_prio_32(struct intc_desc *desc, unsigned int data)
static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
{
unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
unsigned int prio = _INTC_VALUE(data);
ctrl_outl(set_prio_field(desc, ctrl_inl(addr), prio, data), addr);
ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
}
static void disable_mask_8(struct intc_desc *desc, unsigned int data)
static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
{
ctrl_outb(1 << _INTC_BIT(data),
_INTC_PTR(desc, mask_regs, data)->set_reg);
ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
}
static void enable_mask_8(struct intc_desc *desc, unsigned int data)
{
ctrl_outb(1 << _INTC_BIT(data),
_INTC_PTR(desc, mask_regs, data)->clr_reg);
}
enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
static void disable_mask_32(struct intc_desc *desc, unsigned int data)
{
ctrl_outl(1 << _INTC_BIT(data),
_INTC_PTR(desc, mask_regs, data)->set_reg);
}
static void enable_mask_32(struct intc_desc *desc, unsigned int data)
{
ctrl_outl(1 << _INTC_BIT(data),
_INTC_PTR(desc, mask_regs, data)->clr_reg);
}
enum { REG_FN_ERROR=0,
REG_FN_MASK_8, REG_FN_MASK_32,
REG_FN_PRIO_16, REG_FN_PRIO_32 };
static struct {
void (*enable)(struct intc_desc *, unsigned int);
void (*disable)(struct intc_desc *, unsigned int);
} intc_reg_fns[] = {
[REG_FN_MASK_8] = { enable_mask_8, disable_mask_8 },
[REG_FN_MASK_32] = { enable_mask_32, disable_mask_32 },
[REG_FN_PRIO_16] = { enable_prio_16, disable_prio_16 },
[REG_FN_PRIO_32] = { enable_prio_32, disable_prio_32 },
static void (*intc_reg_fns[])(unsigned long addr,
unsigned long h,
unsigned long data) = {
[REG_FN_WRITE_BASE + 0] = write_8,
[REG_FN_WRITE_BASE + 1] = write_16,
[REG_FN_WRITE_BASE + 3] = write_32,
[REG_FN_MODIFY_BASE + 0] = modify_8,
[REG_FN_MODIFY_BASE + 1] = modify_16,
[REG_FN_MODIFY_BASE + 3] = modify_32,
};
enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
MODE_PRIO_REG, /* Priority value written to enable interrupt */
MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
};
static void intc_mode_field(unsigned long addr,
unsigned long handle,
void (*fn)(unsigned long,
unsigned long,
unsigned long),
unsigned int irq)
{
fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
}
static void intc_mode_zero(unsigned long addr,
unsigned long handle,
void (*fn)(unsigned long,
unsigned long,
unsigned long),
unsigned int irq)
{
fn(addr, handle, 0);
}
static void intc_mode_prio(unsigned long addr,
unsigned long handle,
void (*fn)(unsigned long,
unsigned long,
unsigned long),
unsigned int irq)
{
fn(addr, handle, intc_prio_level[irq]);
}
static void (*intc_enable_fns[])(unsigned long addr,
unsigned long handle,
void (*fn)(unsigned long,
unsigned long,
unsigned long),
unsigned int irq) = {
[MODE_ENABLE_REG] = intc_mode_field,
[MODE_MASK_REG] = intc_mode_zero,
[MODE_DUAL_REG] = intc_mode_field,
[MODE_PRIO_REG] = intc_mode_prio,
[MODE_PCLR_REG] = intc_mode_prio,
};
static void (*intc_disable_fns[])(unsigned long addr,
unsigned long handle,
void (*fn)(unsigned long,
unsigned long,
unsigned long),
unsigned int irq) = {
[MODE_ENABLE_REG] = intc_mode_zero,
[MODE_MASK_REG] = intc_mode_field,
[MODE_DUAL_REG] = intc_mode_field,
[MODE_PRIO_REG] = intc_mode_zero,
[MODE_PCLR_REG] = intc_mode_field,
};
static inline void _intc_enable(unsigned int irq, unsigned long handle)
{
struct intc_desc_int *d = get_intc_desc(irq);
unsigned long addr;
unsigned int cpu;
for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
[_INTC_FN(handle)], irq);
}
}
static void intc_enable(unsigned int irq)
{
struct intc_desc *desc = get_intc_desc(irq);
unsigned int data = (unsigned int) get_irq_chip_data(irq);
intc_reg_fns[_INTC_FN(data)].enable(desc, data);
_intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
}
static void intc_disable(unsigned int irq)
{
struct intc_desc *desc = get_intc_desc(irq);
unsigned int data = (unsigned int) get_irq_chip_data(irq);
struct intc_desc_int *d = get_intc_desc(irq);
unsigned long handle = (unsigned long) get_irq_chip_data(irq);
unsigned long addr;
unsigned int cpu;
intc_reg_fns[_INTC_FN(data)].disable(desc, data);
for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
[_INTC_FN(handle)], irq);
}
}
static void set_sense_16(struct intc_desc *desc, unsigned int data)
static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
unsigned int nr_hp,
unsigned int irq)
{
unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
unsigned int bit = _INTC_BIT(data);
unsigned int value = _INTC_VALUE(data);
int i;
ctrl_outw(set_field(ctrl_inw(addr), value, width, bit), addr);
/* this doesn't scale well, but...
*
* this function should only be used for cerain uncommon
* operations such as intc_set_priority() and intc_set_sense()
* and in those rare cases performance doesn't matter that much.
* keeping the memory footprint low is more important.
*
* one rather simple way to speed this up and still keep the
* memory footprint down is to make sure the array is sorted
* and then perform a bisect to lookup the irq.
*/
for (i = 0; i < nr_hp; i++) {
if ((hp + i)->irq != irq)
continue;
return hp + i;
}
return NULL;
}
static void set_sense_32(struct intc_desc *desc, unsigned int data)
int intc_set_priority(unsigned int irq, unsigned int prio)
{
unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
unsigned int bit = _INTC_BIT(data);
unsigned int value = _INTC_VALUE(data);
struct intc_desc_int *d = get_intc_desc(irq);
struct intc_handle_int *ihp;
ctrl_outl(set_field(ctrl_inl(addr), value, width, bit), addr);
if (!intc_prio_level[irq] || prio <= 1)
return -EINVAL;
ihp = intc_find_irq(d->prio, d->nr_prio, irq);
if (ihp) {
if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
return -EINVAL;
intc_prio_level[irq] = prio;
/*
* only set secondary masking method directly
* primary masking method is using intc_prio_level[irq]
* priority level will be set during next enable()
*/
if (_INTC_FN(ihp->handle) != REG_FN_ERR)
_intc_enable(irq, ihp->handle);
}
return 0;
}
#define VALID(x) (x | 0x80)
@ -172,79 +285,38 @@ static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
static int intc_set_sense(unsigned int irq, unsigned int type)
{
struct intc_desc *desc = get_intc_desc(irq);
struct intc_desc_int *d = get_intc_desc(irq);
unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
unsigned int i, j, data, bit;
intc_enum enum_id = 0;
struct intc_handle_int *ihp;
unsigned long addr;
for (i = 0; i < desc->nr_vectors; i++) {
struct intc_vect *vect = desc->vectors + i;
if (evt2irq(vect->vect) != irq)
continue;
enum_id = vect->enum_id;
break;
}
if (!enum_id || !value)
if (!value)
return -EINVAL;
value ^= VALID(0);
for (i = 0; i < desc->nr_sense_regs; i++) {
struct intc_sense_reg *sr = desc->sense_regs + i;
for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
if (sr->enum_ids[j] != enum_id)
continue;
bit = sr->reg_width - ((j + 1) * sr->field_width);
data = _INTC_MK(0, i, bit, value);
switch(sr->reg_width) {
case 16:
set_sense_16(desc, data);
break;
case 32:
set_sense_32(desc, data);
break;
}
return 0;
}
ihp = intc_find_irq(d->sense, d->nr_sense, irq);
if (ihp) {
addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
}
return -EINVAL;
return 0;
}
static unsigned int __init intc_find_mask_handler(unsigned int width)
static unsigned int __init intc_get_reg(struct intc_desc_int *d,
unsigned long address)
{
switch (width) {
case 8:
return REG_FN_MASK_8;
case 32:
return REG_FN_MASK_32;
unsigned int k;
for (k = 0; k < d->nr_reg; k++) {
if (d->reg[k] == address)
return k;
}
BUG();
return REG_FN_ERROR;
return 0;
}
static unsigned int __init intc_find_prio_handler(unsigned int width)
{
switch (width) {
case 16:
return REG_FN_PRIO_16;
case 32:
return REG_FN_PRIO_32;
}
BUG();
return REG_FN_ERROR;
}
static intc_enum __init intc_grp_id(struct intc_desc *desc, intc_enum enum_id)
static intc_enum __init intc_grp_id(struct intc_desc *desc,
intc_enum enum_id)
{
struct intc_group *g = desc->groups;
unsigned int i, j;
@ -289,10 +361,12 @@ static unsigned int __init intc_prio_value(struct intc_desc *desc,
}
static unsigned int __init intc_mask_data(struct intc_desc *desc,
struct intc_desc_int *d,
intc_enum enum_id, int do_grps)
{
struct intc_mask_reg *mr = desc->mask_regs;
unsigned int i, j, fn;
unsigned int i, j, fn, mode;
unsigned long reg_e, reg_d;
for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
mr = desc->mask_regs + i;
@ -301,25 +375,46 @@ static unsigned int __init intc_mask_data(struct intc_desc *desc,
if (mr->enum_ids[j] != enum_id)
continue;
fn = intc_find_mask_handler(mr->reg_width);
if (fn == REG_FN_ERROR)
return 0;
if (mr->set_reg && mr->clr_reg) {
fn = REG_FN_WRITE_BASE;
mode = MODE_DUAL_REG;
reg_e = mr->clr_reg;
reg_d = mr->set_reg;
} else {
fn = REG_FN_MODIFY_BASE;
if (mr->set_reg) {
mode = MODE_ENABLE_REG;
reg_e = mr->set_reg;
reg_d = mr->set_reg;
} else {
mode = MODE_MASK_REG;
reg_e = mr->clr_reg;
reg_d = mr->clr_reg;
}
}
return _INTC_MK(fn, i, (mr->reg_width - 1) - j, 0);
fn += (mr->reg_width >> 3) - 1;
return _INTC_MK(fn, mode,
intc_get_reg(d, reg_e),
intc_get_reg(d, reg_d),
1,
(mr->reg_width - 1) - j);
}
}
if (do_grps)
return intc_mask_data(desc, intc_grp_id(desc, enum_id), 0);
return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
return 0;
}
static unsigned int __init intc_prio_data(struct intc_desc *desc,
struct intc_desc_int *d,
intc_enum enum_id, int do_grps)
{
struct intc_prio_reg *pr = desc->prio_regs;
unsigned int i, j, fn, bit, prio;
unsigned int i, j, fn, mode, bit;
unsigned long reg_e, reg_d;
for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
pr = desc->prio_regs + i;
@ -328,28 +423,72 @@ static unsigned int __init intc_prio_data(struct intc_desc *desc,
if (pr->enum_ids[j] != enum_id)
continue;
fn = intc_find_prio_handler(pr->reg_width);
if (fn == REG_FN_ERROR)
return 0;
if (pr->set_reg && pr->clr_reg) {
fn = REG_FN_WRITE_BASE;
mode = MODE_PCLR_REG;
reg_e = pr->set_reg;
reg_d = pr->clr_reg;
} else {
fn = REG_FN_MODIFY_BASE;
mode = MODE_PRIO_REG;
if (!pr->set_reg)
BUG();
reg_e = pr->set_reg;
reg_d = pr->set_reg;
}
prio = intc_prio_value(desc, enum_id, 1);
fn += (pr->reg_width >> 3) - 1;
bit = pr->reg_width - ((j + 1) * pr->field_width);
BUG_ON(bit < 0);
return _INTC_MK(fn, i, bit, prio);
return _INTC_MK(fn, mode,
intc_get_reg(d, reg_e),
intc_get_reg(d, reg_d),
pr->field_width, bit);
}
}
if (do_grps)
return intc_prio_data(desc, intc_grp_id(desc, enum_id), 0);
return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
return 0;
}
static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id,
static unsigned int __init intc_sense_data(struct intc_desc *desc,
struct intc_desc_int *d,
intc_enum enum_id)
{
struct intc_sense_reg *sr = desc->sense_regs;
unsigned int i, j, fn, bit;
for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
sr = desc->sense_regs + i;
for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
if (sr->enum_ids[j] != enum_id)
continue;
fn = REG_FN_MODIFY_BASE;
fn += (sr->reg_width >> 3) - 1;
bit = sr->reg_width - ((j + 1) * sr->field_width);
BUG_ON(bit < 0);
return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
0, sr->field_width, bit);
}
}
return 0;
}
static void __init intc_register_irq(struct intc_desc *desc,
struct intc_desc_int *d,
intc_enum enum_id,
unsigned int irq)
{
struct intc_handle_int *hp;
unsigned int data[2], primary;
/* Prefer single interrupt source bitmap over other combinations:
@ -359,15 +498,15 @@ static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id,
* 4. priority, multiple interrupt sources (groups)
*/
data[0] = intc_mask_data(desc, enum_id, 0);
data[1] = intc_prio_data(desc, enum_id, 0);
data[0] = intc_mask_data(desc, d, enum_id, 0);
data[1] = intc_prio_data(desc, d, enum_id, 0);
primary = 0;
if (!data[0] && data[1])
primary = 1;
data[0] = data[0] ? data[0] : intc_mask_data(desc, enum_id, 1);
data[1] = data[1] ? data[1] : intc_prio_data(desc, enum_id, 1);
data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
if (!data[primary])
primary ^= 1;
@ -375,31 +514,118 @@ static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id,
BUG_ON(!data[primary]); /* must have primary masking method */
disable_irq_nosync(irq);
set_irq_chip_and_handler_name(irq, &desc->chip,
set_irq_chip_and_handler_name(irq, &d->chip,
handle_level_irq, "level");
set_irq_chip_data(irq, (void *)data[primary]);
/* record the desired priority level */
intc_prio_level[irq] = intc_prio_value(desc, enum_id, 1);
/* enable secondary masking method if present */
if (data[!primary])
intc_reg_fns[_INTC_FN(data[!primary])].enable(desc,
data[!primary]);
_intc_enable(irq, data[!primary]);
/* add irq to d->prio list if priority is available */
if (data[1]) {
hp = d->prio + d->nr_prio;
hp->irq = irq;
hp->handle = data[1];
if (primary) {
/*
* only secondary priority should access registers, so
* set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
*/
hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
}
d->nr_prio++;
}
/* add irq to d->sense list if sense is available */
data[0] = intc_sense_data(desc, d, enum_id);
if (data[0]) {
(d->sense + d->nr_sense)->irq = irq;
(d->sense + d->nr_sense)->handle = data[0];
d->nr_sense++;
}
/* irq should be disabled by default */
desc->chip.mask(irq);
d->chip.mask(irq);
}
static unsigned int __init save_reg(struct intc_desc_int *d,
unsigned int cnt,
unsigned long value,
unsigned int smp)
{
if (value) {
d->reg[cnt] = value;
#ifdef CONFIG_SMP
d->smp[cnt] = smp;
#endif
return 1;
}
return 0;
}
void __init register_intc_controller(struct intc_desc *desc)
{
unsigned int i;
unsigned int i, k, smp;
struct intc_desc_int *d;
desc->chip.mask = intc_disable;
desc->chip.unmask = intc_enable;
desc->chip.mask_ack = intc_disable;
desc->chip.set_type = intc_set_sense;
d = alloc_bootmem(sizeof(*d));
d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
#ifdef CONFIG_SMP
d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
#endif
k = 0;
if (desc->mask_regs) {
for (i = 0; i < desc->nr_mask_regs; i++) {
smp = IS_SMP(desc->mask_regs[i]);
k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
}
}
if (desc->prio_regs) {
d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
for (i = 0; i < desc->nr_prio_regs; i++) {
smp = IS_SMP(desc->prio_regs[i]);
k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
}
}
if (desc->sense_regs) {
d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
for (i = 0; i < desc->nr_sense_regs; i++) {
k += save_reg(d, k, desc->sense_regs[i].reg, 0);
}
}
BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
d->chip.name = desc->name;
d->chip.mask = intc_disable;
d->chip.unmask = intc_enable;
d->chip.mask_ack = intc_disable;
d->chip.set_type = intc_set_sense;
for (i = 0; i < desc->nr_vectors; i++) {
struct intc_vect *vect = desc->vectors + i;
intc_register_irq(desc, vect->enum_id, evt2irq(vect->vect));
intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
}
}

86
arch/sh/kernel/cpu/irq/intc2.c
View File

@ -1,86 +0,0 @@
/*
* Interrupt handling for INTC2-based IRQ.
*
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
* Copyright (C) 2005, 2006 Paul Mundt (lethal@linux-sh.org)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* These are the "new Hitachi style" interrupts, as present on the
* Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <asm/smp.h>
static inline struct intc2_desc *get_intc2_desc(unsigned int irq)
{
struct irq_chip *chip = get_irq_chip(irq);
return (void *)((char *)chip - offsetof(struct intc2_desc, chip));
}
static void disable_intc2_irq(unsigned int irq)
{
struct intc2_data *p = get_irq_chip_data(irq);
struct intc2_desc *d = get_intc2_desc(irq);
ctrl_outl(1 << p->msk_shift, d->msk_base + p->msk_offset +
(hard_smp_processor_id() * 4));
}
static void enable_intc2_irq(unsigned int irq)
{
struct intc2_data *p = get_irq_chip_data(irq);
struct intc2_desc *d = get_intc2_desc(irq);
ctrl_outl(1 << p->msk_shift, d->mskclr_base + p->msk_offset +
(hard_smp_processor_id() * 4));
}
/*
* Setup an INTC2 style interrupt.
* NOTE: Unlike IPR interrupts, parameters are not shifted by this code,
* allowing the use of the numbers straight out of the datasheet.
* For example:
* PIO1 which is INTPRI00[19,16] and INTMSK00[13]
* would be: ^ ^ ^ ^
* | | | |
* { 84, 0, 16, 0, 13 },
*
* in the intc2_data table.
*/
void register_intc2_controller(struct intc2_desc *desc)
{
int i;
desc->chip.mask = disable_intc2_irq;
desc->chip.unmask = enable_intc2_irq;
desc->chip.mask_ack = disable_intc2_irq;
for (i = 0; i < desc->nr_irqs; i++) {
unsigned long ipr, flags;
struct intc2_data *p = desc->intc2_data + i;
disable_irq_nosync(p->irq);
if (desc->prio_base) {
/* Set the priority level */
local_irq_save(flags);
ipr = ctrl_inl(desc->prio_base + p->ipr_offset);
ipr &= ~(0xf << p->ipr_shift);
ipr |= p->priority << p->ipr_shift;
ctrl_outl(ipr, desc->prio_base + p->ipr_offset);
local_irq_restore(flags);
}
set_irq_chip_and_handler_name(p->irq, &desc->chip,
handle_level_irq, "level");
set_irq_chip_data(p->irq, p);
disable_intc2_irq(p->irq);
}
}

19
arch/sh/kernel/cpu/sh2/probe.c
View File

@ -10,26 +10,25 @@
* for more details.
*/
#include <linux/init.h>
#include <linux/smp.h>
#include <asm/processor.h>
#include <asm/cache.h>
int __init detect_cpu_and_cache_system(void)
{
#if defined(CONFIG_CPU_SUBTYPE_SH7619)
current_cpu_data.type = CPU_SH7619;
current_cpu_data.dcache.ways = 4;
current_cpu_data.dcache.way_incr = (1<<12);
current_cpu_data.dcache.sets = 256;
current_cpu_data.dcache.entry_shift = 4;
current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
current_cpu_data.dcache.flags = 0;
boot_cpu_data.type = CPU_SH7619;
boot_cpu_data.dcache.ways = 4;
boot_cpu_data.dcache.way_incr = (1<<12);
boot_cpu_data.dcache.sets = 256;
boot_cpu_data.dcache.entry_shift = 4;
boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
boot_cpu_data.dcache.flags = 0;
#endif
/*
* SH-2 doesn't have separate caches
*/
current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
current_cpu_data.icache = current_cpu_data.dcache;
boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
boot_cpu_data.icache = boot_cpu_data.dcache;
return 0;
}

93
arch/sh/kernel/cpu/sh2/setup-sh7619.c
View File

@ -12,6 +12,61 @@
#include <linux/serial.h>
#include <asm/sci.h>
enum {
UNUSED = 0,
/* interrupt sources */
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
WDT, EDMAC, CMT0, CMT1,
SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
HIF_HIFI, HIF_HIFBI,
DMAC0, DMAC1, DMAC2, DMAC3,
SIOF,
/* interrupt groups */
SCIF0, SCIF1, SCIF2,
};
static struct intc_vect vectors[] __initdata = {
INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
INTC_IRQ(IRQ4, 80), INTC_IRQ(IRQ5, 81),
INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83),
INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85),
INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87),
INTC_IRQ(SCIF0_ERI, 88), INTC_IRQ(SCIF0_RXI, 89),
INTC_IRQ(SCIF0_BRI, 90), INTC_IRQ(SCIF0_TXI, 91),
INTC_IRQ(SCIF1_ERI, 92), INTC_IRQ(SCIF1_RXI, 93),
INTC_IRQ(SCIF1_BRI, 94), INTC_IRQ(SCIF1_TXI, 95),
INTC_IRQ(SCIF2_ERI, 96), INTC_IRQ(SCIF2_RXI, 97),
INTC_IRQ(SCIF2_BRI, 98), INTC_IRQ(SCIF2_TXI, 99),
INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101),
INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105),
INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107),
INTC_IRQ(SIOF, 108),
};
static struct intc_group groups[] __initdata = {
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
};
static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
{ 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
{ 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } },
{ 0xf8080002, 0, 16, 4, /* IPRD */ { SCIF0, SCIF1, SCIF2 } },
{ 0xf8080004, 0, 16, 4, /* IPRE */ { HIF_HIFI, HIF_HIFBI } },
{ 0xf8080006, 0, 16, 4, /* IPRF */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
{ 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, groups,
NULL, NULL, prio_registers, NULL);
static struct plat_sci_port sci_platform_data[] = {
{
.mapbase = 0xf8400000,
@ -52,43 +107,7 @@ static int __init sh7619_devices_setup(void)
}
__initcall(sh7619_devices_setup);
static struct ipr_data ipr_irq_table[] = {
{ 86, 0, 4, 2 }, /* CMI0 */
{ 88, 1, 12, 3 }, /* SCIF0_ERI */
{ 89, 1, 12, 3 }, /* SCIF0_RXI */
{ 90, 1, 12, 3 }, /* SCIF0_BRI */
{ 91, 1, 12, 3 }, /* SCIF0_TXI */
{ 92, 1, 8, 3 }, /* SCIF1_ERI */
{ 93, 1, 8, 3 }, /* SCIF1_RXI */
{ 94, 1, 8, 3 }, /* SCIF1_BRI */
{ 95, 1, 8, 3 }, /* SCIF1_TXI */
{ 96, 1, 4, 3 }, /* SCIF2_ERI */
{ 97, 1, 4, 3 }, /* SCIF2_RXI */
{ 98, 1, 4, 3 }, /* SCIF2_BRI */
{ 99, 1, 4, 3 }, /* SCIF2_TXI */
};
static unsigned long ipr_offsets[] = {
0xf8080000, /* IPRC */
0xf8080002, /* IPRD */
0xf8080004, /* IPRE */
0xf8080006, /* IPRF */
0xf8080008, /* IPRG */
};
static struct ipr_desc ipr_irq_desc = {
.ipr_offsets = ipr_offsets,
.nr_offsets = ARRAY_SIZE(ipr_offsets),
.ipr_data = ipr_irq_table,
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
.chip = {
.name = "IPR-sh7619",
},
};
void __init plat_irq_setup(void)
{
register_ipr_controller(&ipr_irq_desc);
register_intc_controller(&intc_desc);
}

18
arch/sh/kernel/cpu/sh2a/probe.c
View File

@ -17,15 +17,15 @@
int __init detect_cpu_and_cache_system(void)
{
/* Just SH7206 for now .. */
current_cpu_data.type = CPU_SH7206;
current_cpu_data.flags |= CPU_HAS_OP32;
boot_cpu_data.type = CPU_SH7206;
boot_cpu_data.flags |= CPU_HAS_OP32;
current_cpu_data.dcache.ways = 4;
current_cpu_data.dcache.way_incr = (1 << 11);
current_cpu_data.dcache.sets = 128;
current_cpu_data.dcache.entry_shift = 4;
current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
current_cpu_data.dcache.flags = 0;
boot_cpu_data.dcache.ways = 4;
boot_cpu_data.dcache.way_incr = (1 << 11);
boot_cpu_data.dcache.sets = 128;
boot_cpu_data.dcache.entry_shift = 4;
boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
boot_cpu_data.dcache.flags = 0;
/*
* The icache is the same as the dcache as far as this setup is
@ -33,7 +33,7 @@ int __init detect_cpu_and_cache_system(void)
* lacks the U bit that the dcache has, none of this has any bearing
* on the cache info.
*/
current_cpu_data.icache = current_cpu_data.dcache;
boot_cpu_data.icache = boot_cpu_data.dcache;
return 0;
}

217
arch/sh/kernel/cpu/sh2a/setup-sh7206.c
View File

@ -12,27 +12,184 @@
#include <linux/serial.h>
#include <asm/sci.h>
enum {
UNUSED = 0,
/* interrupt sources */
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
ADC_ADI0, ADC_ADI1,
DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI,
DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI,
DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI,
DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI,
CMT0, CMT1, BSC, WDT,
MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
POE2_OEI1, POE2_OEI2,
MTU2S_TGI3A, MTU2S_TGI3B, MTU2S_TGI3C, MTU2S_TGI3D, MTU2S_TCI3V,
MTU2S_TGI4A, MTU2S_TGI4B, MTU2S_TGI4C, MTU2S_TGI4D, MTU2S_TCI4V,
MTU2S_TGI5U, MTU2S_TGI5V, MTU2S_TGI5W,
POE2_OEI3,
IIC3_STPI, IIC3_NAKI, IIC3_RXI, IIC3_TXI, IIC3_TEI,
SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
/* interrupt groups */
PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
IIC3, SCIF0, SCIF1, SCIF2, SCIF3,
};
static struct intc_vect vectors[] __initdata = {
INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109),
INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113),
INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117),
INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121),
INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125),
INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129),
INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133),
INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137),
INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
INTC_IRQ(MTU2_TGI0A, 156), INTC_IRQ(MTU2_TGI0B, 157),
INTC_IRQ(MTU2_TGI0C, 158), INTC_IRQ(MTU2_TGI0D, 159),
INTC_IRQ(MTU2_TCI0V, 160),
INTC_IRQ(MTU2_TGI0E, 161), INTC_IRQ(MTU2_TGI0F, 162),
INTC_IRQ(MTU2_TGI1A, 164), INTC_IRQ(MTU2_TGI1B, 165),
INTC_IRQ(MTU2_TCI1V, 168), INTC_IRQ(MTU2_TCI1U, 169),
INTC_IRQ(MTU2_TGI2A, 172), INTC_IRQ(MTU2_TGI2B, 173),
INTC_IRQ(MTU2_TCI2V, 176), INTC_IRQ(MTU2_TCI2U, 177),
INTC_IRQ(MTU2_TGI3A, 180), INTC_IRQ(MTU2_TGI3B, 181),
INTC_IRQ(MTU2_TGI3C, 182), INTC_IRQ(MTU2_TGI3D, 183),
INTC_IRQ(MTU2_TCI3V, 184),
INTC_IRQ(MTU2_TGI4A, 188), INTC_IRQ(MTU2_TGI4B, 189),
INTC_IRQ(MTU2_TGI4C, 190), INTC_IRQ(MTU2_TGI4D, 191),
INTC_IRQ(MTU2_TCI4V, 192),
INTC_IRQ(MTU2_TGI5U, 196), INTC_IRQ(MTU2_TGI5V, 197),
INTC_IRQ(MTU2_TGI5W, 198),
INTC_IRQ(POE2_OEI1, 200), INTC_IRQ(POE2_OEI2, 201),
INTC_IRQ(MTU2S_TGI3A, 204), INTC_IRQ(MTU2S_TGI3B, 205),
INTC_IRQ(MTU2S_TGI3C, 206), INTC_IRQ(MTU2S_TGI3D, 207),
INTC_IRQ(MTU2S_TCI3V, 208),
INTC_IRQ(MTU2S_TGI4A, 212), INTC_IRQ(MTU2S_TGI4B, 213),
INTC_IRQ(MTU2S_TGI4C, 214), INTC_IRQ(MTU2S_TGI4D, 215),
INTC_IRQ(MTU2S_TCI4V, 216),
INTC_IRQ(MTU2S_TGI5U, 220), INTC_IRQ(MTU2S_TGI5V, 221),
INTC_IRQ(MTU2S_TGI5W, 222),
INTC_IRQ(POE2_OEI3, 224),
INTC_IRQ(IIC3_STPI, 228), INTC_IRQ(IIC3_NAKI, 229),
INTC_IRQ(IIC3_RXI, 230), INTC_IRQ(IIC3_TXI, 231),
INTC_IRQ(IIC3_TEI, 232),
INTC_IRQ(SCIF0_BRI, 240), INTC_IRQ(SCIF0_ERI, 241),
INTC_IRQ(SCIF0_RXI, 242), INTC_IRQ(SCIF0_TXI, 243),
INTC_IRQ(SCIF1_BRI, 244), INTC_IRQ(SCIF1_ERI, 245),
INTC_IRQ(SCIF1_RXI, 246), INTC_IRQ(SCIF1_TXI, 247),
INTC_IRQ(SCIF2_BRI, 248), INTC_IRQ(SCIF2_ERI, 249),
INTC_IRQ(SCIF2_RXI, 250), INTC_IRQ(SCIF2_TXI, 251),
INTC_IRQ(SCIF3_BRI, 252), INTC_IRQ(SCIF3_ERI, 253),
INTC_IRQ(SCIF3_RXI, 254), INTC_IRQ(SCIF3_TXI, 255),
};
static struct intc_group groups[] __initdata = {
INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
PINT4, PINT5, PINT6, PINT7),
INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI),
INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI),
INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI),
INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI),
INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI),
INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI),
INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI),
INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI),
INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B),
INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U),
INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B),
INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U),
INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
INTC_GROUP(MTU5, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
INTC_GROUP(POE2_12, POE2_OEI1, POE2_OEI2),
INTC_GROUP(MTU3S_ABCD, MTU2S_TGI3A, MTU2S_TGI3B,
MTU2S_TGI3C, MTU2S_TGI3D),
INTC_GROUP(MTU4S_ABCD, MTU2S_TGI4A, MTU2S_TGI4B,
MTU2S_TGI4C, MTU2S_TGI4D),
INTC_GROUP(MTU5S, MTU2S_TGI5U, MTU2S_TGI5V, MTU2S_TGI5W),
INTC_GROUP(IIC3, IIC3_STPI, IIC3_NAKI, IIC3_RXI, IIC3_TXI, IIC3_TEI),
INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
};
static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } },
{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF,
MTU1_AB, MTU1_VU } },
{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU,
MTU3_ABCD, MTU2_TCI3V } },
{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V,
MTU5, POE2_12 } },
{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V,
MTU4S_ABCD, MTU2S_TCI4V } },
{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } },
{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
};
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xfffe0808, 0, 16, /* PINTER */
{ 0, 0, 0, 0, 0, 0, 0, 0,
PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
NULL, mask_registers, prio_registers, NULL);
static struct plat_sci_port sci_platform_data[] = {
{
.mapbase = 0xfffe8000,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 241, 242, 243, 240},
.irqs = { 241, 242, 243, 240 },
}, {
.mapbase = 0xfffe8800,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 247, 244, 245, 246},
.irqs = { 245, 246, 247, 244 },
}, {
.mapbase = 0xfffe9000,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 249, 250, 251, 248},
.irqs = { 249, 250, 251, 248 },
}, {
.mapbase = 0xfffe9800,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 253, 254, 255, 252},
.irqs = { 253, 254, 255, 252 },
}, {
.flags = 0,
}
@ -57,57 +214,7 @@ static int __init sh7206_devices_setup(void)
}
__initcall(sh7206_devices_setup);
static struct ipr_data ipr_irq_table[] = {
{ 140, 7, 12, 2 }, /* CMI0 */
{ 164, 8, 4, 2 }, /* MTU2_TGI1A */
{ 240, 13, 12, 3 }, /* SCIF0_BRI */
{ 241, 13, 12, 3 }, /* SCIF0_ERI */
{ 242, 13, 12, 3 }, /* SCIF0_RXI */
{ 243, 13, 12, 3 }, /* SCIF0_TXI */
{ 244, 13, 8, 3 }, /* SCIF1_BRI */
{ 245, 13, 8, 3 }, /* SCIF1_ERI */
{ 246, 13, 8, 3 }, /* SCIF1_RXI */
{ 247, 13, 8, 3 }, /* SCIF1_TXI */
{ 248, 13, 4, 3 }, /* SCIF2_BRI */
{ 249, 13, 4, 3 }, /* SCIF2_ERI */
{ 250, 13, 4, 3 }, /* SCIF2_RXI */
{ 251, 13, 4, 3 }, /* SCIF2_TXI */
{ 252, 13, 0, 3 }, /* SCIF3_BRI */
{ 253, 13, 0, 3 }, /* SCIF3_ERI */
{ 254, 13, 0, 3 }, /* SCIF3_RXI */
{ 255, 13, 0, 3 }, /* SCIF3_TXI */
};
static unsigned long ipr_offsets[] = {
0xfffe0818, /* IPR01 */
0xfffe081a, /* IPR02 */
0, /* unused */
0, /* unused */
0xfffe0820, /* IPR05 */
0xfffe0c00, /* IPR06 */
0xfffe0c02, /* IPR07 */
0xfffe0c04, /* IPR08 */
0xfffe0c06, /* IPR09 */
0xfffe0c08, /* IPR10 */
0xfffe0c0a, /* IPR11 */
0xfffe0c0c, /* IPR12 */
0xfffe0c0e, /* IPR13 */
0xfffe0c10, /* IPR14 */
};
static struct ipr_desc ipr_irq_desc = {
.ipr_offsets = ipr_offsets,
.nr_offsets = ARRAY_SIZE(ipr_offsets),
.ipr_data = ipr_irq_table,
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
.chip = {
.name = "IPR-sh7206",
},
};
void __init plat_irq_setup(void)
{
register_ipr_controller(&ipr_irq_desc);
register_intc_controller(&intc_desc);
}

10
arch/sh/kernel/cpu/sh3/Makefile
View File

@ -6,12 +6,13 @@ obj-y := ex.o probe.o entry.o
# CPU subtype setup
obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o
obj-$(CONFIG_CPU_SUBTYPE_SH7706) += setup-sh7709.o
obj-$(CONFIG_CPU_SUBTYPE_SH7707) += setup-sh7709.o
obj-$(CONFIG_CPU_SUBTYPE_SH7708) += setup-sh7708.o
obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh7709.o
obj-$(CONFIG_CPU_SUBTYPE_SH7706) += setup-sh770x.o
obj-$(CONFIG_CPU_SUBTYPE_SH7707) += setup-sh770x.o
obj-$(CONFIG_CPU_SUBTYPE_SH7708) += setup-sh770x.o
obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh770x.o
obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o
obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o
obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o
# Primary on-chip clocks (common)
clock-$(CONFIG_CPU_SH3) := clock-sh3.o
@ -19,5 +20,6 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7705) := clock-sh7705.o
clock-$(CONFIG_CPU_SUBTYPE_SH7706) := clock-sh7706.o
clock-$(CONFIG_CPU_SUBTYPE_SH7709) := clock-sh7709.o
clock-$(CONFIG_CPU_SUBTYPE_SH7710) := clock-sh7710.o
clock-$(CONFIG_CPU_SUBTYPE_SH7720) := clock-sh7710.o
obj-y += $(clock-y)

48
arch/sh/kernel/cpu/sh3/probe.c
View File

@ -50,44 +50,47 @@ int __init detect_cpu_and_cache_system(void)
back_to_P1();
current_cpu_data.dcache.ways = 4;
current_cpu_data.dcache.entry_shift = 4;
current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
current_cpu_data.dcache.flags = 0;
boot_cpu_data.dcache.ways = 4;
boot_cpu_data.dcache.entry_shift = 4;
boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
boot_cpu_data.dcache.flags = 0;
/*
* 7709A/7729 has 16K cache (256-entry), while 7702 has only
* 2K(direct) 7702 is not supported (yet)
*/
if (data0 == data1 && data2 == data3) { /* Shadow */
current_cpu_data.dcache.way_incr = (1 << 11);
current_cpu_data.dcache.entry_mask = 0x7f0;
current_cpu_data.dcache.sets = 128;
current_cpu_data.type = CPU_SH7708;
boot_cpu_data.dcache.way_incr = (1 << 11);
boot_cpu_data.dcache.entry_mask = 0x7f0;
boot_cpu_data.dcache.sets = 128;
boot_cpu_data.type = CPU_SH7708;
current_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC;
boot_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC;
} else { /* 7709A or 7729 */
current_cpu_data.dcache.way_incr = (1 << 12);
current_cpu_data.dcache.entry_mask = 0xff0;
current_cpu_data.dcache.sets = 256;
current_cpu_data.type = CPU_SH7729;
boot_cpu_data.dcache.way_incr = (1 << 12);
boot_cpu_data.dcache.entry_mask = 0xff0;
boot_cpu_data.dcache.sets = 256;
boot_cpu_data.type = CPU_SH7729;
#if defined(CONFIG_CPU_SUBTYPE_SH7706)
current_cpu_data.type = CPU_SH7706;
boot_cpu_data.type = CPU_SH7706;
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7710)
current_cpu_data.type = CPU_SH7710;
boot_cpu_data.type = CPU_SH7710;
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7712)
current_cpu_data.type = CPU_SH7712;
boot_cpu_data.type = CPU_SH7712;
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7720)
boot_cpu_data.type = CPU_SH7720;
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
current_cpu_data.type = CPU_SH7705;
boot_cpu_data.type = CPU_SH7705;
#if defined(CONFIG_SH7705_CACHE_32KB)
current_cpu_data.dcache.way_incr = (1 << 13);
current_cpu_data.dcache.entry_mask = 0x1ff0;
current_cpu_data.dcache.sets = 512;
boot_cpu_data.dcache.way_incr = (1 << 13);
boot_cpu_data.dcache.entry_mask = 0x1ff0;
boot_cpu_data.dcache.sets = 512;
ctrl_outl(CCR_CACHE_32KB, CCR3);
#else
ctrl_outl(CCR_CACHE_16KB, CCR3);
@ -98,9 +101,8 @@ int __init detect_cpu_and_cache_system(void)
/*
* SH-3 doesn't have separate caches
*/
current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
current_cpu_data.icache = current_cpu_data.dcache;
boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
boot_cpu_data.icache = boot_cpu_data.dcache;
return 0;
}

172
arch/sh/kernel/cpu/sh3/setup-sh7705.c
View File

@ -1,7 +1,7 @@
/*
* SH7705 Setup
*
* Copyright (C) 2006 Paul Mundt
* Copyright (C) 2006, 2007 Paul Mundt
* Copyright (C) 2007 Nobuhiro Iwamatsu
*
* This file is subject to the terms and conditions of the GNU General Public
@ -10,8 +10,90 @@
*/
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/serial.h>
#include <asm/sci.h>
#include <asm/rtc.h>
enum {
UNUSED = 0,
/* interrupt sources */
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
PINT07, PINT815,
DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
ADC_ADI,
USB_USI0, USB_USI1,
TPU0, TPU1, TPU2, TPU3,
TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
RTC_ATI, RTC_PRI, RTC_CUI,
WDT,
REF_RCMI,
/* interrupt groups */
RTC, TMU2, DMAC, USB, SCIF2, SCIF0,
};
static struct intc_vect vectors[] __initdata = {
INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
INTC_VECT(SCIF0_TXI, 0x8e0),
INTC_VECT(SCIF2_ERI, 0x900), INTC_VECT(SCIF2_RXI, 0x920),
INTC_VECT(SCIF2_TXI, 0x960),
INTC_VECT(ADC_ADI, 0x980),
INTC_VECT(USB_USI0, 0xa20), INTC_VECT(USB_USI1, 0xa40),
INTC_VECT(TPU0, 0xc00), INTC_VECT(TPU1, 0xc20),
INTC_VECT(TPU3, 0xc80), INTC_VECT(TPU1, 0xca0),
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
INTC_VECT(RTC_CUI, 0x4c0),
INTC_VECT(WDT, 0x560),
INTC_VECT(REF_RCMI, 0x580),
};
static struct intc_group groups[] __initdata = {
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
INTC_GROUP(USB, USB_USI0, USB_USI1),
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
};
static struct intc_prio priorities[] __initdata = {
INTC_PRIO(DMAC, 7),
INTC_PRIO(SCIF2, 3),
INTC_PRIO(SCIF0, 3),
};
static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
{ 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, IRQ5, IRQ4 } },
{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, SCIF0, SCIF2, ADC_ADI } },
{ 0xa4080000, 0, 16, 4, /* IPRF */ { 0, 0, USB } },
{ 0xa4080002, 0, 16, 4, /* IPRG */ { TPU0, TPU1 } },
{ 0xa4080004, 0, 16, 4, /* IPRH */ { TPU2, TPU3 } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, groups,
priorities, NULL, prio_registers, NULL);
static struct intc_vect vectors_irq[] __initdata = {
INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
};
static DECLARE_INTC_DESC(intc_desc_irq, "sh7705-irq", vectors_irq, NULL,
priorities, NULL, prio_registers, NULL);
static struct plat_sci_port sci_platform_data[] = {
{
@ -37,8 +119,43 @@ static struct platform_device sci_device = {
},
};
static struct resource rtc_resources[] = {
[0] = {
.start = 0xfffffec0,
.end = 0xfffffec0 + 0x1e,
.flags = IORESOURCE_IO,
},
[1] = {
.start = 20,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = 21,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = 22,
.flags = IORESOURCE_IRQ,
},
};
static struct sh_rtc_platform_info rtc_info = {
.capabilities = RTC_CAP_4_DIGIT_YEAR,
};
static struct platform_device rtc_device = {
.name = "sh-rtc",
.id = -1,
.num_resources = ARRAY_SIZE(rtc_resources),
.resource = rtc_resources,
.dev = {
.platform_data = &rtc_info,
},
};
static struct platform_device *sh7705_devices[] __initdata = {
&sci_device,
&rtc_device,
};
static int __init sh7705_devices_setup(void)
@ -48,51 +165,16 @@ static int __init sh7705_devices_setup(void)
}
__initcall(sh7705_devices_setup);
static struct ipr_data ipr_irq_table[] = {
/* IRQ, IPR-idx, shift, priority */
{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
{ 17, 0, 8, 2 }, /* TMU1 TUNI */
{ 18, 0, 4, 2 }, /* TMU2 TUNI */
{ 27, 1, 12, 2 }, /* WDT ITI */
{ 20, 0, 0, 2 }, /* RTC ATI (alarm) */
{ 21, 0, 0, 2 }, /* RTC PRI (period) */
{ 22, 0, 0, 2 }, /* RTC CUI (carry) */
{ 48, 4, 12, 7 }, /* DMAC DMTE0 */
{ 49, 4, 12, 7 }, /* DMAC DMTE1 */
{ 50, 4, 12, 7 }, /* DMAC DMTE2 */
{ 51, 4, 12, 7 }, /* DMAC DMTE3 */
{ 52, 4, 8, 3 }, /* SCIF0 ERI */
{ 53, 4, 8, 3 }, /* SCIF0 RXI */
{ 55, 4, 8, 3 }, /* SCIF0 TXI */
{ 56, 4, 4, 3 }, /* SCIF1 ERI */
{ 57, 4, 4, 3 }, /* SCIF1 RXI */
{ 59, 4, 4, 3 }, /* SCIF1 TXI */
};
static unsigned long ipr_offsets[] = {
0xFFFFFEE2, /* 0: IPRA */
0xFFFFFEE4, /* 1: IPRB */
0xA4000016, /* 2: IPRC */
0xA4000018, /* 3: IPRD */
0xA400001A, /* 4: IPRE */
0xA4080000, /* 5: IPRF */
0xA4080002, /* 6: IPRG */
0xA4080004, /* 7: IPRH */
};
static struct ipr_desc ipr_irq_desc = {
.ipr_offsets = ipr_offsets,
.nr_offsets = ARRAY_SIZE(ipr_offsets),
.ipr_data = ipr_irq_table,
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
.chip = {
.name = "IPR-sh7705",
},
};
void __init plat_irq_setup_pins(int mode)
{
if (mode == IRQ_MODE_IRQ) {
register_intc_controller(&intc_desc_irq);
return;
}
BUG();
}
void __init plat_irq_setup(void)
{
register_ipr_controller(&ipr_irq_desc);
register_intc_controller(&intc_desc);
}

43
arch/sh/kernel/cpu/sh3/setup-sh7708.c
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@ -1,43 +0,0 @@
/*
* SH7708 Setup
*
* Copyright (C) 2006 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <asm/sci.h>
static struct plat_sci_port sci_platform_data[] = {
{
.mapbase = 0xfffffe80,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCI,
.irqs = { 23, 24, 25, 0 },
}, {
.flags = 0,
}
};
static struct platform_device sci_device = {
.name = "sh-sci",
.id = -1,
.dev = {
.platform_data = sci_platform_data,
},
};
static struct platform_device *sh7708_devices[] __initdata = {
&sci_device,
};
static int __init sh7708_devices_setup(void)
{
return platform_add_devices(sh7708_devices,
ARRAY_SIZE(sh7708_devices));
}
__initcall(sh7708_devices_setup);

145
arch/sh/kernel/cpu/sh3/setup-sh7709.c
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@ -1,145 +0,0 @@
/*
* SH7707/SH7709 Setup
*
* Copyright (C) 2006 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <asm/sci.h>
static struct resource rtc_resources[] = {
[0] = {
.start = 0xfffffec0,
.end = 0xfffffec0 + 0x1e,
.flags = IORESOURCE_IO,
},
[1] = {
.start = 20,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = 21,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = 22,
.flags = IORESOURCE_IRQ,
},
};
static struct plat_sci_port sci_platform_data[] = {
{
.mapbase = 0xfffffe80,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCI,
.irqs = { 23, 24, 25, 0 },
}, {
.mapbase = 0xa4000150,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 56, 57, 59, 58 },
}, {
.mapbase = 0xa4000140,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_IRDA,
.irqs = { 52, 53, 55, 54 },
}, {
.flags = 0,
}
};
static struct platform_device sci_device = {
.name = "sh-sci",
.id = -1,
.dev = {
.platform_data = sci_platform_data,
},
};
static struct platform_device rtc_device = {
.name = "sh-rtc",
.id = -1,
.num_resources = ARRAY_SIZE(rtc_resources),
.resource = rtc_resources,
};
static struct platform_device *sh7709_devices[] __initdata = {
&sci_device,
&rtc_device,
};
static int __init sh7709_devices_setup(void)
{
return platform_add_devices(sh7709_devices,
ARRAY_SIZE(sh7709_devices));
}
__initcall(sh7709_devices_setup);
static struct ipr_data ipr_irq_table[] = {
{ 16, 0, 12, 2 }, /* TMU TUNI0 */
{ 17, 0, 8, 4 }, /* TMU TUNI1 */
{ 18, 0, 4, 1 }, /* TMU TUNI1 */
{ 19, 0, 4, 1 }, /* TMU TUNI1 */
{ 20, 0, 0, 2 }, /* RTC CUI */
{ 21, 0, 0, 2 }, /* RTC CUI */
{ 22, 0, 0, 2 }, /* RTC CUI */
{ 23, 1, 4, 3 }, /* SCI */
{ 24, 1, 4, 3 }, /* SCI */
{ 25, 1, 4, 3 }, /* SCI */
{ 26, 1, 4, 3 }, /* SCI */
{ 27, 1, 12, 3 }, /* WDT ITI */
{ 32, 2, 0, 1 }, /* IRQ 0 */
{ 33, 2, 4, 1 }, /* IRQ 1 */
{ 34, 2, 8, 1 }, /* IRQ 2 APM */
{ 35, 2, 12, 1 }, /* IRQ 3 TOUCHSCREEN */
{ 36, 3, 0, 1 }, /* IRQ 4 */
{ 37, 3, 4, 1 }, /* IRQ 5 */
{ 48, 4, 12, 7 }, /* DMA */
{ 49, 4, 12, 7 }, /* DMA */
{ 50, 4, 12, 7 }, /* DMA */
{ 51, 4, 12, 7 }, /* DMA */
{ 52, 4, 8, 3 }, /* IRDA */
{ 53, 4, 8, 3 }, /* IRDA */
{ 54, 4, 8, 3 }, /* IRDA */
{ 55, 4, 8, 3 }, /* IRDA */
{ 56, 4, 4, 3 }, /* SCIF */
{ 57, 4, 4, 3 }, /* SCIF */
{ 58, 4, 4, 3 }, /* SCIF */
{ 59, 4, 4, 3 }, /* SCIF */
};
static unsigned long ipr_offsets[] = {
0xfffffee2, /* 0: IPRA */
0xfffffee4, /* 1: IPRB */
0xa4000016, /* 2: IPRC */
0xa4000018, /* 3: IPRD */
0xa400001a, /* 4: IPRE */
};
static struct ipr_desc ipr_irq_desc = {
.ipr_offsets = ipr_offsets,
.nr_offsets = ARRAY_SIZE(ipr_offsets),
.ipr_data = ipr_irq_table,
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
.chip = {
.name = "IPR-sh7709",
},
};
void __init plat_irq_setup(void)
{
register_ipr_controller(&ipr_irq_desc);
}

224
arch/sh/kernel/cpu/sh3/setup-sh770x.c Normal file
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@ -0,0 +1,224 @@
/*
* SH3 Setup code for SH7706, SH7707, SH7708, SH7709
*
* Copyright (C) 2007 Magnus Damm
*
* Based on setup-sh7709.c
*
* Copyright (C) 2006 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <asm/sci.h>
enum {
UNUSED = 0,
/* interrupt sources */
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
PINT07, PINT815,
DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI,
ADC_ADI,
LCDC, PCC0, PCC1,
TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
RTC_ATI, RTC_PRI, RTC_CUI,
WDT,
REF_RCMI, REF_ROVI,
/* interrupt groups */
RTC, REF, TMU2, DMAC, SCI, SCIF2, SCIF0,
};
static struct intc_vect vectors[] __initdata = {
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
INTC_VECT(RTC_CUI, 0x4c0),
INTC_VECT(SCI_ERI, 0x4e0), INTC_VECT(SCI_RXI, 0x500),
INTC_VECT(SCI_TXI, 0x520), INTC_VECT(SCI_TEI, 0x540),
INTC_VECT(WDT, 0x560),
INTC_VECT(REF_RCMI, 0x580),
INTC_VECT(REF_ROVI, 0x5a0),
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
INTC_VECT(ADC_ADI, 0x980),
INTC_VECT(SCIF2_ERI, 0x900), INTC_VECT(SCIF2_RXI, 0x920),
INTC_VECT(SCIF2_BRI, 0x940), INTC_VECT(SCIF2_TXI, 0x960),
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707)
INTC_VECT(LCDC, 0x9a0),
INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0),
#endif
};
static struct intc_group groups[] __initdata = {
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
INTC_GROUP(REF, REF_RCMI, REF_ROVI),
INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
INTC_GROUP(SCI, SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI),
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
};
static struct intc_prio priorities[] __initdata = {
INTC_PRIO(DMAC, 7),
INTC_PRIO(SCI, 3),
INTC_PRIO(SCIF2, 3),
INTC_PRIO(SCIF0, 3),
};
static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
{ 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
{ 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
{ 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707)
{ 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
#endif
};
static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups,
priorities, NULL, prio_registers, NULL);
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
static struct intc_vect vectors_irq[] __initdata = {
INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
};
static DECLARE_INTC_DESC(intc_desc_irq, "sh770x-irq", vectors_irq, NULL,
priorities, NULL, prio_registers, NULL);
#endif
static struct resource rtc_resources[] = {
[0] = {
.start = 0xfffffec0,
.end = 0xfffffec0 + 0x1e,
.flags = IORESOURCE_IO,
},
[1] = {
.start = 20,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = 21,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = 22,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device rtc_device = {
.name = "sh-rtc",
.id = -1,
.num_resources = ARRAY_SIZE(rtc_resources),
.resource = rtc_resources,
};
static struct plat_sci_port sci_platform_data[] = {
{
.mapbase = 0xfffffe80,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCI,
.irqs = { 23, 24, 25, 0 },
},
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
{
.mapbase = 0xa4000150,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 56, 57, 59, 58 },
},
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
{
.mapbase = 0xa4000140,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_IRDA,
.irqs = { 52, 53, 55, 54 },
},
#endif
{
.flags = 0,
}
};
static struct platform_device sci_device = {
.name = "sh-sci",
.id = -1,
.dev = {
.platform_data = sci_platform_data,
},
};
static struct platform_device *sh770x_devices[] __initdata = {
&sci_device,
&rtc_device,
};
static int __init sh770x_devices_setup(void)
{
return platform_add_devices(sh770x_devices,
ARRAY_SIZE(sh770x_devices));
}
__initcall(sh770x_devices_setup);
#define INTC_ICR1 0xa4000010UL
#define INTC_ICR1_IRQLVL (1<<14)
void __init plat_irq_setup_pins(int mode)
{
if (mode == IRQ_MODE_IRQ) {
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709)
ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
register_intc_controller(&intc_desc_irq);
return;
#endif
}
BUG();
}
void __init plat_irq_setup(void)
{
register_intc_controller(&intc_desc);
}

200
arch/sh/kernel/cpu/sh3/setup-sh7710.c
View File

@ -1,7 +1,7 @@
/*
* SH7710 Setup
* SH3 Setup code for SH7710, SH7712
*
* Copyright (C) 2006 Paul Mundt
* Copyright (C) 2006, 2007 Paul Mundt
* Copyright (C) 2007 Nobuhiro Iwamatsu
*
* This file is subject to the terms and conditions of the GNU General Public
@ -10,8 +10,140 @@
*/
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/serial.h>
#include <asm/sci.h>
#include <asm/rtc.h>
enum {
UNUSED = 0,
/* interrupt sources */
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
DMAC_DEI4, DMAC_DEI5,
IPSEC,
EDMAC0, EDMAC1, EDMAC2,
SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI,
SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI,
TMU0, TMU1, TMU2,
RTC_ATI, RTC_PRI, RTC_CUI,
WDT,
REF,
/* interrupt groups */
RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1,
};
static struct intc_vect vectors[] __initdata = {
INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
INTC_VECT(SCIF1_ERI, 0x900), INTC_VECT(SCIF1_RXI, 0x920),
INTC_VECT(SCIF1_BRI, 0x940), INTC_VECT(SCIF1_TXI, 0x960),
INTC_VECT(DMAC_DEI4, 0xb80), INTC_VECT(DMAC_DEI5, 0xba0),
#ifdef CONFIG_CPU_SUBTYPE_SH7710
INTC_VECT(IPSEC, 0xbe0),
#endif
INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
INTC_VECT(EDMAC2, 0xc40),
INTC_VECT(SIOF0_ERI, 0xe00), INTC_VECT(SIOF0_TXI, 0xe20),
INTC_VECT(SIOF0_RXI, 0xe40), INTC_VECT(SIOF0_CCI, 0xe60),
INTC_VECT(SIOF1_ERI, 0xe80), INTC_VECT(SIOF1_TXI, 0xea0),
INTC_VECT(SIOF1_RXI, 0xec0), INTC_VECT(SIOF1_CCI, 0xee0),
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
INTC_VECT(TMU2, 0x440),
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
INTC_VECT(RTC_CUI, 0x4c0),
INTC_VECT(WDT, 0x560),
INTC_VECT(REF, 0x580),
};
static struct intc_group groups[] __initdata = {
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
INTC_GROUP(DMAC2, DMAC_DEI4, DMAC_DEI5),
INTC_GROUP(SIOF0, SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI),
INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI),
};
static struct intc_prio priorities[] __initdata = {
INTC_PRIO(DMAC1, 7),
INTC_PRIO(DMAC2, 7),
INTC_PRIO(SCIF0, 3),
INTC_PRIO(SCIF1, 3),
INTC_PRIO(SIOF0, 3),
INTC_PRIO(SIOF1, 3),
INTC_PRIO(EDMAC0, 5),
INTC_PRIO(EDMAC1, 5),
INTC_PRIO(EDMAC2, 5),
};
static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
{ 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
{ 0xa4080000, 0, 16, 4, /* IPRF */ { 0, DMAC2 } },
#ifdef CONFIG_CPU_SUBTYPE_SH7710
{ 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC } },
#endif
{ 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
{ 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
{ 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,
priorities, NULL, prio_registers, NULL);
static struct intc_vect vectors_irq[] __initdata = {
INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
};
static DECLARE_INTC_DESC(intc_desc_irq, "sh7710-irq", vectors_irq, NULL,
priorities, NULL, prio_registers, NULL);
static struct resource rtc_resources[] = {
[0] = {
.start = 0xa413fec0,
.end = 0xa413fec0 + 0x1e,
.flags = IORESOURCE_IO,
},
[1] = {
.start = 20,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = 21,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = 22,
.flags = IORESOURCE_IRQ,
},
};
static struct sh_rtc_platform_info rtc_info = {
.capabilities = RTC_CAP_4_DIGIT_YEAR,
};
static struct platform_device rtc_device = {
.name = "sh-rtc",
.id = -1,
.num_resources = ARRAY_SIZE(rtc_resources),
.resource = rtc_resources,
.dev = {
.platform_data = &rtc_info,
},
};
static struct plat_sci_port sci_platform_data[] = {
{
@ -20,7 +152,7 @@ static struct plat_sci_port sci_platform_data[] = {
.type = PORT_SCIF,
.irqs = { 52, 53, 55, 54 },
}, {
.mapbase = 0xa4420000,
.mapbase = 0xa4410000,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 56, 57, 59, 58 },
@ -40,6 +172,7 @@ static struct platform_device sci_device = {
static struct platform_device *sh7710_devices[] __initdata = {
&sci_device,
&rtc_device,
};
static int __init sh7710_devices_setup(void)
@ -49,59 +182,16 @@ static int __init sh7710_devices_setup(void)
}
__initcall(sh7710_devices_setup);
static struct ipr_data ipr_irq_table[] = {
/* IRQ, IPR-idx, shift, priority */
{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
{ 17, 0, 8, 2 }, /* TMU1 TUNI */
{ 18, 0, 4, 2 }, /* TMU2 TUNI */
{ 27, 1, 12, 2 }, /* WDT ITI */
{ 20, 0, 0, 2 }, /* RTC ATI (alarm) */
{ 21, 0, 0, 2 }, /* RTC PRI (period) */
{ 22, 0, 0, 2 }, /* RTC CUI (carry) */
{ 48, 4, 12, 7 }, /* DMAC DMTE0 */
{ 49, 4, 12, 7 }, /* DMAC DMTE1 */
{ 50, 4, 12, 7 }, /* DMAC DMTE2 */
{ 51, 4, 12, 7 }, /* DMAC DMTE3 */
{ 52, 4, 8, 3 }, /* SCIF0 ERI */
{ 53, 4, 8, 3 }, /* SCIF0 RXI */
{ 54, 4, 8, 3 }, /* SCIF0 BRI */
{ 55, 4, 8, 3 }, /* SCIF0 TXI */
{ 56, 4, 4, 3 }, /* SCIF1 ERI */
{ 57, 4, 4, 3 }, /* SCIF1 RXI */
{ 58, 4, 4, 3 }, /* SCIF1 BRI */
{ 59, 4, 4, 3 }, /* SCIF1 TXI */
{ 76, 5, 8, 7 }, /* DMAC DMTE4 */
{ 77, 5, 8, 7 }, /* DMAC DMTE5 */
{ 80, 6, 12, 5 }, /* EDMAC EINT0 */
{ 81, 6, 8, 5 }, /* EDMAC EINT1 */
{ 82, 6, 4, 5 }, /* EDMAC EINT2 */
};
static unsigned long ipr_offsets[] = {
0xA414FEE2, /* 0: IPRA */
0xA414FEE4, /* 1: IPRB */
0xA4140016, /* 2: IPRC */
0xA4140018, /* 3: IPRD */
0xA414001A, /* 4: IPRE */
0xA4080000, /* 5: IPRF */
0xA4080002, /* 6: IPRG */
0xA4080004, /* 7: IPRH */
0xA4080006, /* 8: IPRI */
};
static struct ipr_desc ipr_irq_desc = {
.ipr_offsets = ipr_offsets,
.nr_offsets = ARRAY_SIZE(ipr_offsets),
.ipr_data = ipr_irq_table,
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
.chip = {
.name = "IPR-sh7710",
},
};
void __init plat_irq_setup_pins(int mode)
{
if (mode == IRQ_MODE_IRQ) {
register_intc_controller(&intc_desc_irq);
return;
}
BUG();
}
void __init plat_irq_setup(void)
{
register_ipr_controller(&ipr_irq_desc);
register_intc_controller(&intc_desc);
}

210
arch/sh/kernel/cpu/sh3/setup-sh7720.c Normal file
View File

@ -0,0 +1,210 @@
/*
* SH7720 Setup
*
* Copyright (C) 2007 Markus Brunner, Mark Jonas
*
* Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c:
*
* Copyright (C) 2006 Paul Mundt
* Copyright (C) 2006 Jamie Lenehan
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/io.h>
#include <asm/sci.h>
#include <asm/rtc.h>
#define INTC_ICR1 0xA4140010UL
#define INTC_ICR_IRLM 0x4000
#define INTC_ICR_IRQ (~INTC_ICR_IRLM)
static struct resource rtc_resources[] = {
[0] = {
.start = 0xa413fec0,
.end = 0xa413fec0 + 0x28 - 1,
.flags = IORESOURCE_IO,
},
[1] = {
/* Period IRQ */
.start = 21,
.flags = IORESOURCE_IRQ,
},
[2] = {
/* Carry IRQ */
.start = 22,
.flags = IORESOURCE_IRQ,
},
[3] = {
/* Alarm IRQ */
.start = 20,
.flags = IORESOURCE_IRQ,
},
};
static struct sh_rtc_platform_info rtc_info = {
.capabilities = RTC_CAP_4_DIGIT_YEAR,
};
static struct platform_device rtc_device = {
.name = "sh-rtc",
.id = -1,
.num_resources = ARRAY_SIZE(rtc_resources),
.resource = rtc_resources,
.dev = {
.platform_data = &rtc_info,
},
};
static struct plat_sci_port sci_platform_data[] = {
{
.mapbase = 0xa4430000,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 },
}, {
.mapbase = 0xa4438000,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 81, 81, 81, 81 },
}, {
.flags = 0,
}
};
static struct platform_device sci_device = {
.name = "sh-sci",
.id = -1,
.dev = {
.platform_data = sci_platform_data,
},
};
static struct platform_device *sh7720_devices[] __initdata = {
&rtc_device,
&sci_device,
};
static int __init sh7720_devices_setup(void)
{
return platform_add_devices(sh7720_devices,
ARRAY_SIZE(sh7720_devices));
}
__initcall(sh7720_devices_setup);
enum {
UNUSED = 0,
/* interrupt sources */
TMU0, TMU1, TMU2, RTC_ATI, RTC_PRI, RTC_CUI,
WDT, REF_RCMI, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND,
IRQ0, IRQ1, IRQ2, IRQ3,
USBF_SPD, TMU_SUNI, IRQ5, IRQ4,
DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3, LCDC, SSL,
ADC, DMAC2_DEI4, DMAC2_DEI5, USBFI0, USBFI1, CMT,
SCIF0, SCIF1,
PINT07, PINT815, TPU0, TPU1, TPU2, TPU3, IIC,
SIOF0, SIOF1, MMCI0, MMCI1, MMCI2, MMCI3, PCC,
USBHI, AFEIF,
H_UDI,
/* interrupt groups */
TMU, RTC, SIM, DMAC1, USBFI, DMAC2, USB, TPU, MMC,
};
static struct intc_vect vectors[] __initdata = {
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
INTC_VECT(TMU2, 0x440), INTC_VECT(RTC_ATI, 0x480),
INTC_VECT(RTC_PRI, 0x4a0), INTC_VECT(RTC_CUI, 0x4c0),
INTC_VECT(SIM_ERI, 0x4e0), INTC_VECT(SIM_RXI, 0x500),
INTC_VECT(SIM_TXI, 0x520), INTC_VECT(SIM_TEND, 0x540),
INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580),
/* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0),
INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1_DEI0, 0x800),
INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840),
INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900),
INTC_VECT(SSL, 0x980), INTC_VECT(USBFI0, 0xa20),
INTC_VECT(USBFI1, 0xa40), INTC_VECT(USBHI, 0xa60),
INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0),
INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00),
INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80),
INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00),
INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU0, 0xd80),
INTC_VECT(TPU1, 0xda0), INTC_VECT(TPU2, 0xdc0),
INTC_VECT(TPU3, 0xde0), INTC_VECT(IIC, 0xe00),
INTC_VECT(MMCI0, 0xe80), INTC_VECT(MMCI1, 0xea0),
INTC_VECT(MMCI2, 0xec0), INTC_VECT(MMCI3, 0xee0),
INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60),
INTC_VECT(AFEIF, 0xfe0),
};
static struct intc_group groups[] __initdata = {
INTC_GROUP(TMU, TMU0, TMU1, TMU2),
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND),
INTC_GROUP(DMAC1, DMAC1_DEI0, DMAC1_DEI1, DMAC1_DEI2, DMAC1_DEI3),
INTC_GROUP(USBFI, USBFI0, USBFI1),
INTC_GROUP(DMAC2, DMAC2_DEI4, DMAC2_DEI5),
INTC_GROUP(TPU, TPU0, TPU1, TPU2, TPU3),
INTC_GROUP(MMC, MMCI0, MMCI1, MMCI2, MMCI3),
};
static struct intc_prio priorities[] __initdata = {
INTC_PRIO(SCIF0, 2),
INTC_PRIO(SCIF1, 2),
INTC_PRIO(DMAC1, 1),
INTC_PRIO(DMAC2, 1),
INTC_PRIO(RTC, 2),
INTC_PRIO(TMU, 2),
INTC_PRIO(TPU, 2),
};
static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
{ 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
{ 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
{ 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
{ 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
{ 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
{ 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
{ 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } },
{ 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, groups,
priorities, NULL, prio_registers, NULL);
static struct intc_sense_reg sense_registers[] __initdata = {
{ INTC_ICR1, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
};
static struct intc_vect vectors_irq[] __initdata = {
INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
};
static DECLARE_INTC_DESC(intc_irq_desc, "sh7720-irq", vectors_irq,
NULL, priorities, NULL, prio_registers, sense_registers);
void __init plat_irq_setup_pins(int mode)
{
switch (mode) {
case IRQ_MODE_IRQ:
ctrl_outw(ctrl_inw(INTC_ICR1) & INTC_ICR_IRQ, INTC_ICR1);
register_intc_controller(&intc_irq_desc);
break;
default:
BUG();
}
}
void __init plat_irq_setup(void)
{
register_intc_controller(&intc_desc);
}

178
arch/sh/kernel/cpu/sh4/probe.c
View File

@ -3,7 +3,7 @@
*
* CPU Subtype Probing for SH-4.
*
* Copyright (C) 2001 - 2006 Paul Mundt
* Copyright (C) 2001 - 2007 Paul Mundt
* Copyright (C) 2003 Richard Curnow
*
* This file is subject to the terms and conditions of the GNU General Public
@ -12,7 +12,6 @@
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/smp.h>
#include <asm/processor.h>
#include <asm/cache.h>
@ -36,37 +35,34 @@ int __init detect_cpu_and_cache_system(void)
/*
* Setup some sane SH-4 defaults for the icache
*/
current_cpu_data.icache.way_incr = (1 << 13);
current_cpu_data.icache.entry_shift = 5;
current_cpu_data.icache.sets = 256;
current_cpu_data.icache.ways = 1;
current_cpu_data.icache.linesz = L1_CACHE_BYTES;
boot_cpu_data.icache.way_incr = (1 << 13);
boot_cpu_data.icache.entry_shift = 5;
boot_cpu_data.icache.sets = 256;
boot_cpu_data.icache.ways = 1;
boot_cpu_data.icache.linesz = L1_CACHE_BYTES;
/*
* And again for the dcache ..
*/
current_cpu_data.dcache.way_incr = (1 << 14);
current_cpu_data.dcache.entry_shift = 5;
current_cpu_data.dcache.sets = 512;
current_cpu_data.dcache.ways = 1;
current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
boot_cpu_data.dcache.way_incr = (1 << 14);
boot_cpu_data.dcache.entry_shift = 5;
boot_cpu_data.dcache.sets = 512;
boot_cpu_data.dcache.ways = 1;
boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
/*
* Setup some generic flags we can probe
* (L2 and DSP detection only work on SH-4A)
* Setup some generic flags we can probe on SH-4A parts
*/
if (((pvr >> 16) & 0xff) == 0x10) {
if ((cvr & 0x02000000) == 0)
current_cpu_data.flags |= CPU_HAS_L2_CACHE;
if ((cvr & 0x10000000) == 0)
current_cpu_data.flags |= CPU_HAS_DSP;
boot_cpu_data.flags |= CPU_HAS_DSP;
current_cpu_data.flags |= CPU_HAS_LLSC;
boot_cpu_data.flags |= CPU_HAS_LLSC;
}
/* FPU detection works for everyone */
if ((cvr & 0x20000000) == 1)
current_cpu_data.flags |= CPU_HAS_FPU;
boot_cpu_data.flags |= CPU_HAS_FPU;
/* Mask off the upper chip ID */
pvr &= 0xffff;
@ -77,140 +73,140 @@ int __init detect_cpu_and_cache_system(void)
*/
switch (pvr) {
case 0x205:
current_cpu_data.type = CPU_SH7750;
current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
boot_cpu_data.type = CPU_SH7750;
boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
CPU_HAS_PERF_COUNTER;
break;
case 0x206:
current_cpu_data.type = CPU_SH7750S;
current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
boot_cpu_data.type = CPU_SH7750S;
boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
CPU_HAS_PERF_COUNTER;
break;
case 0x1100:
current_cpu_data.type = CPU_SH7751;
current_cpu_data.flags |= CPU_HAS_FPU;
boot_cpu_data.type = CPU_SH7751;
boot_cpu_data.flags |= CPU_HAS_FPU;
break;
case 0x2001:
case 0x2004:
current_cpu_data.type = CPU_SH7770;
current_cpu_data.icache.ways = 4;
current_cpu_data.dcache.ways = 4;
boot_cpu_data.type = CPU_SH7770;
boot_cpu_data.icache.ways = 4;
boot_cpu_data.dcache.ways = 4;
current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
break;
case 0x2006:
case 0x200A:
if (prr == 0x61)
current_cpu_data.type = CPU_SH7781;
boot_cpu_data.type = CPU_SH7781;
else
current_cpu_data.type = CPU_SH7780;
boot_cpu_data.type = CPU_SH7780;
current_cpu_data.icache.ways = 4;
current_cpu_data.dcache.ways = 4;
boot_cpu_data.icache.ways = 4;
boot_cpu_data.dcache.ways = 4;
current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
CPU_HAS_LLSC;
break;
case 0x3000:
case 0x3003:
case 0x3009:
current_cpu_data.type = CPU_SH7343;
current_cpu_data.icache.ways = 4;
current_cpu_data.dcache.ways = 4;
current_cpu_data.flags |= CPU_HAS_LLSC;
boot_cpu_data.type = CPU_SH7343;
boot_cpu_data.icache.ways = 4;
boot_cpu_data.dcache.ways = 4;
boot_cpu_data.flags |= CPU_HAS_LLSC;
break;
case 0x3004:
case 0x3007:
current_cpu_data.type = CPU_SH7785;
current_cpu_data.icache.ways = 4;
current_cpu_data.dcache.ways = 4;
current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
boot_cpu_data.type = CPU_SH7785;
boot_cpu_data.icache.ways = 4;
boot_cpu_data.dcache.ways = 4;
boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
CPU_HAS_LLSC;
break;
case 0x3008:
if (prr == 0xa0) {
current_cpu_data.type = CPU_SH7722;
current_cpu_data.icache.ways = 4;
current_cpu_data.dcache.ways = 4;
current_cpu_data.flags |= CPU_HAS_LLSC;
boot_cpu_data.type = CPU_SH7722;
boot_cpu_data.icache.ways = 4;
boot_cpu_data.dcache.ways = 4;
boot_cpu_data.flags |= CPU_HAS_LLSC;
}
break;
case 0x4000: /* 1st cut */
case 0x4001: /* 2nd cut */
current_cpu_data.type = CPU_SHX3;
current_cpu_data.icache.ways = 4;
current_cpu_data.dcache.ways = 4;
current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
boot_cpu_data.type = CPU_SHX3;
boot_cpu_data.icache.ways = 4;
boot_cpu_data.dcache.ways = 4;
boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
CPU_HAS_LLSC;
break;
case 0x8000:
current_cpu_data.type = CPU_ST40RA;
current_cpu_data.flags |= CPU_HAS_FPU;
boot_cpu_data.type = CPU_ST40RA;
boot_cpu_data.flags |= CPU_HAS_FPU;
break;
case 0x8100:
current_cpu_data.type = CPU_ST40GX1;
current_cpu_data.flags |= CPU_HAS_FPU;
boot_cpu_data.type = CPU_ST40GX1;
boot_cpu_data.flags |= CPU_HAS_FPU;
break;
case 0x700:
current_cpu_data.type = CPU_SH4_501;
current_cpu_data.icache.ways = 2;
current_cpu_data.dcache.ways = 2;
boot_cpu_data.type = CPU_SH4_501;
boot_cpu_data.icache.ways = 2;
boot_cpu_data.dcache.ways = 2;
break;
case 0x600:
current_cpu_data.type = CPU_SH4_202;
current_cpu_data.icache.ways = 2;
current_cpu_data.dcache.ways = 2;
current_cpu_data.flags |= CPU_HAS_FPU;
boot_cpu_data.type = CPU_SH4_202;
boot_cpu_data.icache.ways = 2;
boot_cpu_data.dcache.ways = 2;
boot_cpu_data.flags |= CPU_HAS_FPU;
break;
case 0x500 ... 0x501:
switch (prr) {
case 0x10:
current_cpu_data.type = CPU_SH7750R;
boot_cpu_data.type = CPU_SH7750R;
break;
case 0x11:
current_cpu_data.type = CPU_SH7751R;
boot_cpu_data.type = CPU_SH7751R;
break;
case 0x50 ... 0x5f:
current_cpu_data.type = CPU_SH7760;
boot_cpu_data.type = CPU_SH7760;
break;
}
current_cpu_data.icache.ways = 2;
current_cpu_data.dcache.ways = 2;
boot_cpu_data.icache.ways = 2;
boot_cpu_data.dcache.ways = 2;
current_cpu_data.flags |= CPU_HAS_FPU;
boot_cpu_data.flags |= CPU_HAS_FPU;
break;
default:
current_cpu_data.type = CPU_SH_NONE;
boot_cpu_data.type = CPU_SH_NONE;
break;
}
#ifdef CONFIG_SH_DIRECT_MAPPED
current_cpu_data.icache.ways = 1;
current_cpu_data.dcache.ways = 1;
boot_cpu_data.icache.ways = 1;
boot_cpu_data.dcache.ways = 1;
#endif
#ifdef CONFIG_CPU_HAS_PTEA
current_cpu_data.flags |= CPU_HAS_PTEA;
boot_cpu_data.flags |= CPU_HAS_PTEA;
#endif
/*
* On anything that's not a direct-mapped cache, look to the CVR
* for I/D-cache specifics.
*/
if (current_cpu_data.icache.ways > 1) {
if (boot_cpu_data.icache.ways > 1) {
size = sizes[(cvr >> 20) & 0xf];
current_cpu_data.icache.way_incr = (size >> 1);
current_cpu_data.icache.sets = (size >> 6);
boot_cpu_data.icache.way_incr = (size >> 1);
boot_cpu_data.icache.sets = (size >> 6);
}
/* And the rest of the D-cache */
if (current_cpu_data.dcache.ways > 1) {
if (boot_cpu_data.dcache.ways > 1) {
size = sizes[(cvr >> 16) & 0xf];
current_cpu_data.dcache.way_incr = (size >> 1);
current_cpu_data.dcache.sets = (size >> 6);
boot_cpu_data.dcache.way_incr = (size >> 1);
boot_cpu_data.dcache.sets = (size >> 6);
}
/*
@ -218,7 +214,7 @@ int __init detect_cpu_and_cache_system(void)
*
* SH-4A's have an optional PIPT L2.
*/
if (current_cpu_data.flags & CPU_HAS_L2_CACHE) {
if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
/*
* Size calculation is much more sensible
* than it is for the L1.
@ -229,22 +225,22 @@ int __init detect_cpu_and_cache_system(void)
BUG_ON(!size);
current_cpu_data.scache.way_incr = (1 << 16);
current_cpu_data.scache.entry_shift = 5;
current_cpu_data.scache.ways = 4;
current_cpu_data.scache.linesz = L1_CACHE_BYTES;
boot_cpu_data.scache.way_incr = (1 << 16);
boot_cpu_data.scache.entry_shift = 5;
boot_cpu_data.scache.ways = 4;
boot_cpu_data.scache.linesz = L1_CACHE_BYTES;
current_cpu_data.scache.entry_mask =
(current_cpu_data.scache.way_incr -
current_cpu_data.scache.linesz);
boot_cpu_data.scache.entry_mask =
(boot_cpu_data.scache.way_incr -
boot_cpu_data.scache.linesz);
current_cpu_data.scache.sets = size /
(current_cpu_data.scache.linesz *
current_cpu_data.scache.ways);
boot_cpu_data.scache.sets = size /
(boot_cpu_data.scache.linesz *
boot_cpu_data.scache.ways);
current_cpu_data.scache.way_size =
(current_cpu_data.scache.sets *
current_cpu_data.scache.linesz);
boot_cpu_data.scache.way_size =
(boot_cpu_data.scache.sets *
boot_cpu_data.scache.linesz);
}
return 0;

54
arch/sh/kernel/cpu/sh4/setup-sh7750.c
View File

@ -104,7 +104,7 @@ enum {
DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
};
static struct intc_vect vectors[] = {
static struct intc_vect vectors[] __initdata = {
INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
@ -118,7 +118,7 @@ static struct intc_vect vectors[] = {
INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
};
static struct intc_group groups[] = {
static struct intc_group groups[] __initdata = {
INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
@ -126,20 +126,20 @@ static struct intc_group groups[] = {
INTC_GROUP(REF, REF_RCMI, REF_ROVI),
};
static struct intc_prio priorities[] = {
static struct intc_prio priorities[] __initdata = {
INTC_PRIO(SCIF, 3),
INTC_PRIO(SCI1, 3),
INTC_PRIO(DMAC, 7),
};
static struct intc_prio_reg prio_registers[] = {
{ 0xffd00004, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xffd00008, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
{ 0xffd0000c, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
{ 0xffd00010, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
{ 0xfe080000, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
TMU4, TMU3,
PCIC1, PCIC0_PCISERR } },
static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
TMU4, TMU3,
PCIC1, PCIC0_PCISERR } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
@ -150,13 +150,13 @@ static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
defined(CONFIG_CPU_SUBTYPE_SH7751) || \
defined(CONFIG_CPU_SUBTYPE_SH7091)
static struct intc_vect vectors_dma4[] = {
static struct intc_vect vectors_dma4[] __initdata = {
INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
INTC_VECT(DMAC_DMAE, 0x6c0),
};
static struct intc_group groups_dma4[] = {
static struct intc_group groups_dma4[] __initdata = {
INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
DMAC_DMTE3, DMAC_DMAE),
};
@ -168,7 +168,7 @@ static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
/* SH7750R and SH7751R both have 8-channel DMA controllers */
#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
static struct intc_vect vectors_dma8[] = {
static struct intc_vect vectors_dma8[] __initdata = {
INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
@ -176,7 +176,7 @@ static struct intc_vect vectors_dma8[] = {
INTC_VECT(DMAC_DMAE, 0x6c0),
};
static struct intc_group groups_dma8[] = {
static struct intc_group groups_dma8[] __initdata = {
INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
@ -191,11 +191,11 @@ static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
defined(CONFIG_CPU_SUBTYPE_SH7751) || \
defined(CONFIG_CPU_SUBTYPE_SH7751R)
static struct intc_vect vectors_tmu34[] = {
static struct intc_vect vectors_tmu34[] __initdata = {
INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
};
static struct intc_mask_reg mask_registers[] = {
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, TMU4, TMU3,
@ -210,7 +210,7 @@ static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
#endif
/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
static struct intc_vect vectors_irlm[] = {
static struct intc_vect vectors_irlm[] __initdata = {
INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
};
@ -220,14 +220,14 @@ static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
/* SH7751 and SH7751R both have PCI */
#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
static struct intc_vect vectors_pci[] = {
static struct intc_vect vectors_pci[] __initdata = {
INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
};
static struct intc_group groups_pci[] = {
static struct intc_group groups_pci[] __initdata = {
INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
};
@ -282,13 +282,19 @@ void __init plat_irq_setup(void)
#define INTC_ICR 0xffd00000UL
#define INTC_ICR_IRLM (1<<7)
/* enable individual interrupt mode for external interupts */
void __init ipr_irq_enable_irlm(void)
void __init plat_irq_setup_pins(int mode)
{
#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
return;
#endif
register_intc_controller(&intc_desc_irlm);
ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
switch (mode) {
case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
register_intc_controller(&intc_desc_irlm);
break;
default:
BUG();
}
}

253
arch/sh/kernel/cpu/sh4/setup-sh7760.c
View File

@ -12,6 +12,136 @@
#include <linux/serial.h>
#include <asm/sci.h>
enum {
UNUSED = 0,
/* interrupt sources */
IRL0, IRL1, IRL2, IRL3,
HUDI, GPIOI,
DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
DMAC_DMAE,
IRQ4, IRQ5, IRQ6, IRQ7,
HCAN20, HCAN21,
SSI0, SSI1,
HAC0, HAC1,
I2C0, I2C1,
USB, LCDC,
DMABRG0, DMABRG1, DMABRG2,
SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
HSPI,
MMCIF0, MMCIF1, MMCIF2, MMCIF3,
MFI, ADC, CMT,
TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
WDT,
REF_RCMI, REF_ROVI,
/* interrupt groups */
DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF,
};
static struct intc_vect vectors[] __initdata = {
INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
INTC_VECT(DMAC_DMAE, 0x6c0),
INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0),
INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0),
INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0),
INTC_VECT(DMABRG2, 0xac0),
INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20),
INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60),
INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0),
INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0),
INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20),
INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60),
INTC_VECT(HSPI, 0xc80),
INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20),
INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60),
INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
INTC_VECT(WDT, 0x560),
INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
};
static struct intc_group groups[] __initdata = {
INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
INTC_GROUP(REF, REF_RCMI, REF_ROVI),
};
static struct intc_prio priorities[] __initdata = {
INTC_PRIO(SCIF0, 3),
INTC_PRIO(SCIF1, 3),
INTC_PRIO(SCIF2, 3),
INTC_PRIO(SIM, 3),
INTC_PRIO(DMAC, 7),
INTC_PRIO(DMABRG, 13),
};
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
{ IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
0, DMABRG0, DMABRG1, DMABRG2,
SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, } },
{ 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */
{ 0, 0, 0, 0, 0, 0, 0, 0,
SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
HSPI, MMCIF0, MMCIF1, MMCIF2,
MMCIF3, 0, 0, 0, 0, 0, 0, 0,
0, MFI, 0, 0, 0, 0, ADC, CMT, } },
};
static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
{ 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
HAC0, HAC1, I2C0, I2C1 } },
{ 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
SCIF1, SCIF2, SIM, HSPI } },
{ 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
MFI, 0, ADC, CMT } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups,
priorities, mask_registers, prio_registers, NULL);
static struct intc_vect vectors_irq[] __initdata = {
INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
};
static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
priorities, mask_registers, prio_registers, NULL);
static struct plat_sci_port sci_platform_data[] = {
{
.mapbase = 0xfe600000,
@ -28,6 +158,11 @@ static struct plat_sci_port sci_platform_data[] = {
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 76, 77, 79, 78 },
}, {
.mapbase = 0xfe480000,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCI,
.irqs = { 80, 81, 82, 0 },
}, {
.flags = 0,
}
@ -52,114 +187,18 @@ static int __init sh7760_devices_setup(void)
}
__initcall(sh7760_devices_setup);
static struct intc2_data intc2_irq_table[] = {
{48, 0, 28, 0, 31, 3}, /* IRQ 4 */
{49, 0, 24, 0, 30, 3}, /* IRQ 3 */
{50, 0, 20, 0, 29, 3}, /* IRQ 2 */
{51, 0, 16, 0, 28, 3}, /* IRQ 1 */
{56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */
{57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */
{58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */
{59, 4, 16, 0, 22, 3}, /* I2S_CHAN1 */
{60, 4, 12, 0, 21, 3}, /* AC97_CHAN0 */
{61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */
{62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */
{63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */
{52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */
{53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */
{54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */
{55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */
{64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */
{65, 8, 24, 0, 16, 3}, /* LCDC */
{68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */
{69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */
{70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */
{72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */
{73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */
{74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */
{75, 8, 12, 0, 4, 3}, /* SCIF1_TXI_IRQ */
{76, 8, 8, 0, 3, 3}, /* SCIF2_ERI_IRQ */
{77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */
{78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */
{79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */
{80, 8, 4, 4, 23, 3}, /* SIM_ERI */
{81, 8, 4, 4, 22, 3}, /* SIM_RXI */
{82, 8, 4, 4, 21, 3}, /* SIM_TXI */
{83, 8, 4, 4, 20, 3}, /* SIM_TEI */
{84, 8, 0, 4, 19, 3}, /* HSPII */
{88, 12, 20, 4, 18, 3}, /* MMCI0 */
{89, 12, 20, 4, 17, 3}, /* MMCI1 */
{90, 12, 20, 4, 16, 3}, /* MMCI2 */
{91, 12, 20, 4, 15, 3}, /* MMCI3 */
{92, 12, 12, 4, 6, 3}, /* MFI */
{108,12, 4, 4, 1, 3}, /* ADC */
{109,12, 0, 4, 0, 3}, /* CMTI */
};
static struct intc2_desc intc2_irq_desc __read_mostly = {
.prio_base = 0xfe080000,
.msk_base = 0xfe080040,
.mskclr_base = 0xfe080060,
.intc2_data = intc2_irq_table,
.nr_irqs = ARRAY_SIZE(intc2_irq_table),
.chip = {
.name = "INTC2-sh7760",
},
};
static struct ipr_data ipr_irq_table[] = {
/* IRQ, IPR-idx, shift, priority */
{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
{ 17, 0, 8, 2 }, /* TMU1 TUNI */
{ 18, 0, 4, 2 }, /* TMU2 TUNI */
{ 19, 0, 4, 2 }, /* TMU2 TIPCI */
{ 27, 1, 12, 2 }, /* WDT ITI */
{ 28, 1, 8, 2 }, /* REF RCMI */
{ 29, 1, 8, 2 }, /* REF ROVI */
{ 32, 2, 0, 7 }, /* HUDI */
{ 33, 2, 12, 7 }, /* GPIOI */
{ 34, 2, 8, 7 }, /* DMAC DMTE0 */
{ 35, 2, 8, 7 }, /* DMAC DMTE1 */
{ 36, 2, 8, 7 }, /* DMAC DMTE2 */
{ 37, 2, 8, 7 }, /* DMAC DMTE3 */
{ 38, 2, 8, 7 }, /* DMAC DMAE */
{ 44, 2, 8, 7 }, /* DMAC DMTE4 */
{ 45, 2, 8, 7 }, /* DMAC DMTE5 */
{ 46, 2, 8, 7 }, /* DMAC DMTE6 */
{ 47, 2, 8, 7 }, /* DMAC DMTE7 */
/* these here are only valid if INTC_ICR bit 7 is set to 1!
* XXX: maybe CONFIG_SH_IRLMODE symbol? SH7751 could use it too */
#if 0
{ 2, 3, 12, 3 }, /* IRL0 */
{ 5, 3, 8, 3 }, /* IRL1 */
{ 8, 3, 4, 3 }, /* IRL2 */
{ 11, 3, 0, 3 }, /* IRL3 */
#endif
};
static unsigned long ipr_offsets[] = {
0xffd00004UL, /* 0: IPRA */
0xffd00008UL, /* 1: IPRB */
0xffd0000cUL, /* 2: IPRC */
0xffd00010UL, /* 3: IPRD */
};
static struct ipr_desc ipr_irq_desc = {
.ipr_offsets = ipr_offsets,
.nr_offsets = ARRAY_SIZE(ipr_offsets),
.ipr_data = ipr_irq_table,
.nr_irqs = ARRAY_SIZE(ipr_irq_table),
.chip = {
.name = "IPR-sh7760",
},
};
void __init plat_irq_setup_pins(int mode)
{
switch (mode) {
case IRQ_MODE_IRQ:
register_intc_controller(&intc_desc_irq);
break;
default:
BUG();
}
}
void __init plat_irq_setup(void)
{
register_intc2_controller(&intc2_irq_desc);
register_ipr_controller(&ipr_irq_desc);
register_intc_controller(&intc_desc);
}

4
arch/sh/kernel/cpu/sh4/sq.c
View File

@ -58,11 +58,11 @@ do { \
*/
void sq_flush_range(unsigned long start, unsigned int len)
{
volatile unsigned long *sq = (unsigned long *)start;
unsigned long *sq = (unsigned long *)start;
/* Flush the queues */
for (len >>= 5; len--; sq += 8)
prefetchw((void *)sq);
prefetchw(sq);
/* Wait for completion */
store_queue_barrier();

6
arch/sh/kernel/cpu/sh4a/Makefile
View File

@ -10,6 +10,9 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
# SMP setup
smp-$(CONFIG_CPU_SUBTYPE_SHX3) := smp-shx3.o
# Primary on-chip clocks (common)
clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
@ -18,4 +21,5 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
obj-y += $(clock-y)
obj-y += $(clock-y)
obj-$(CONFIG_SMP) += $(smp-y)

4
arch/sh/kernel/cpu/sh4a/setup-sh7343.c
View File

@ -41,3 +41,7 @@ static int __init sh7343_devices_setup(void)
ARRAY_SIZE(sh7343_devices));
}
__initcall(sh7343_devices_setup);
void __init plat_irq_setup(void)
{
}

38
arch/sh/kernel/cpu/sh4a/setup-sh7722.c
View File

@ -84,7 +84,7 @@ enum {
SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
};
static struct intc_vect vectors[] = {
static struct intc_vect vectors[] __initdata = {
INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
@ -117,7 +117,7 @@ static struct intc_vect vectors[] = {
INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
};
static struct intc_group groups[] = {
static struct intc_group groups[] __initdata = {
INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
@ -130,7 +130,7 @@ static struct intc_group groups[] = {
INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
};
static struct intc_prio priorities[] = {
static struct intc_prio priorities[] __initdata = {
INTC_PRIO(SCIF0, 3),
INTC_PRIO(SCIF1, 3),
INTC_PRIO(SCIF2, 3),
@ -138,7 +138,7 @@ static struct intc_prio priorities[] = {
INTC_PRIO(TMU1, 2),
};
static struct intc_mask_reg mask_registers[] = {
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
{ } },
{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
@ -168,24 +168,24 @@ static struct intc_mask_reg mask_registers[] = {
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};
static struct intc_prio_reg prio_registers[] = {
{ 0xa4080000, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
{ 0xa4080004, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
{ 0xa4080008, 16, 4, /* IPRC */ { } },
{ 0xa408000c, 16, 4, /* IPRD */ { } },
{ 0xa4080010, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
{ 0xa4080014, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
{ 0xa4080018, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
{ 0xa408001c, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
{ 0xa4080020, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
{ 0xa4080024, 16, 4, /* IPRJ */ { 0, 0, SIU } },
{ 0xa4080028, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
{ 0xa408002c, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
{ 0xa4140010, 32, 4, /* INTPRI00 */
static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
{ 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};
static struct intc_sense_reg sense_registers[] = {
static struct intc_sense_reg sense_registers[] __initdata = {
{ 0xa414001c, 16, 2, /* ICR1 */
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

4
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
View File

@ -51,3 +51,7 @@ static int __init sh7770_devices_setup(void)
ARRAY_SIZE(sh7770_devices));
}
__initcall(sh7770_devices_setup);
void __init plat_irq_setup(void)
{
}

91
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
View File

@ -10,6 +10,7 @@
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/io.h>
#include <asm/sci.h>
static struct resource rtc_resources[] = {
@ -114,7 +115,7 @@ enum {
PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO,
};
static struct intc_vect vectors[] = {
static struct intc_vect vectors[] __initdata = {
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
INTC_VECT(RTC_CUI, 0x4c0),
INTC_VECT(WDT, 0x560),
@ -150,7 +151,7 @@ static struct intc_vect vectors[] = {
INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
};
static struct intc_group groups[] = {
static struct intc_group groups[] __initdata = {
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
@ -167,12 +168,12 @@ static struct intc_group groups[] = {
INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
};
static struct intc_prio priorities[] = {
static struct intc_prio priorities[] __initdata = {
INTC_PRIO(SCIF0, 3),
INTC_PRIO(SCIF1, 3),
};
static struct intc_mask_reg mask_registers[] = {
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
{ 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
@ -180,16 +181,18 @@ static struct intc_mask_reg mask_registers[] = {
HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
};
static struct intc_prio_reg prio_registers[] = {
{ 0xffd40000, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, TMU2, TMU2_TICPI } },
{ 0xffd40004, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
{ 0xffd40008, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
{ 0xffd4000c, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
{ 0xffd40010, 32, 8, /* INT2PRI4 */ { CMT, HAC, PCISERR, PCIINTA, } },
{ 0xffd40014, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
PCIINTD, PCIC5 } },
{ 0xffd40018, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
{ 0xffd4001c, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
TMU2, TMU2_TICPI } },
{ 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
{ 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
{ 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
{ 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
PCISERR, PCIINTA, } },
{ 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
PCIINTD, PCIC5 } },
{ 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
{ 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities,
@ -197,24 +200,24 @@ static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities,
/* Support for external interrupt pins in IRQ mode */
static struct intc_vect irq_vectors[] = {
static struct intc_vect irq_vectors[] __initdata = {
INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
};
static struct intc_mask_reg irq_mask_registers[] = {
static struct intc_mask_reg irq_mask_registers[] __initdata = {
{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};
static struct intc_prio_reg irq_prio_registers[] = {
{ 0xffd00010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
IRQ4, IRQ5, IRQ6, IRQ7 } },
static struct intc_prio_reg irq_prio_registers[] __initdata = {
{ 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
IRQ4, IRQ5, IRQ6, IRQ7 } },
};
static struct intc_sense_reg irq_sense_registers[] = {
static struct intc_sense_reg irq_sense_registers[] __initdata = {
{ 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
IRQ4, IRQ5, IRQ6, IRQ7 } },
};
@ -225,7 +228,7 @@ static DECLARE_INTC_DESC(intc_irq_desc, "sh7780-irq", irq_vectors,
/* External interrupt pins in IRL mode */
static struct intc_vect irl_vectors[] = {
static struct intc_vect irl_vectors[] __initdata = {
INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
@ -236,16 +239,16 @@ static struct intc_vect irl_vectors[] = {
INTC_VECT(IRL_HHHL, 0x3c0),
};
static struct intc_mask_reg irl3210_mask_registers[] = {
{ 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
{ IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
};
static struct intc_mask_reg irl7654_mask_registers[] = {
{ 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
@ -259,8 +262,28 @@ static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
NULL, NULL, irl3210_mask_registers, NULL, NULL);
#define INTC_ICR0 0xffd00000
#define INTC_INTMSK0 0xffd00044
#define INTC_INTMSK1 0xffd00048
#define INTC_INTMSK2 0xffd40080
#define INTC_INTMSKCLR1 0xffd00068
#define INTC_INTMSKCLR2 0xffd40084
void __init plat_irq_setup(void)
{
/* disable IRQ7-0 */
ctrl_outl(0xff000000, INTC_INTMSK0);
/* disable IRL3-0 + IRL7-4 */
ctrl_outl(0xc0000000, INTC_INTMSK1);
ctrl_outl(0xfffefffe, INTC_INTMSK2);
/* select IRL mode for IRL3-0 + IRL7-4 */
ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
/* disable holding function, ie enable "SH-4 Mode" */
ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
register_intc_controller(&intc_desc);
}
@ -268,12 +291,28 @@ void __init plat_irq_setup_pins(int mode)
{
switch (mode) {
case IRQ_MODE_IRQ:
/* select IRQ mode for IRL3-0 + IRL7-4 */
ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
register_intc_controller(&intc_irq_desc);
break;
case IRQ_MODE_IRL7654:
register_intc_controller(&intc_irl7654_desc);
/* enable IRL7-4 but don't provide any masking */
ctrl_outl(0x40000000, INTC_INTMSKCLR1);
ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
break;
case IRQ_MODE_IRL3210:
/* enable IRL0-3 but don't provide any masking */
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
break;
case IRQ_MODE_IRL7654_MASK:
/* enable IRL7-4 and mask using cpu intc controller */
ctrl_outl(0x40000000, INTC_INTMSKCLR1);
register_intc_controller(&intc_irl7654_desc);
break;
case IRQ_MODE_IRL3210_MASK:
/* enable IRL0-3 and mask using cpu intc controller */
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
register_intc_controller(&intc_irl3210_desc);
break;
default:

300
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
View File

@ -10,6 +10,9 @@
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/io.h>
#include <linux/mm.h>
#include <asm/mmzone.h>
#include <asm/sci.h>
static struct plat_sci_port sci_platform_data[] = {
@ -72,46 +75,281 @@ static int __init sh7785_devices_setup(void)
}
__initcall(sh7785_devices_setup);
static struct intc2_data intc2_irq_table[] = {
{ 28, 0, 24, 0, 0, 2 }, /* TMU0 */
enum {
UNUSED = 0,
{ 40, 8, 24, 0, 2, 3 }, /* SCIF0 ERI */
{ 41, 8, 24, 0, 2, 3 }, /* SCIF0 RXI */
{ 42, 8, 24, 0, 2, 3 }, /* SCIF0 BRI */
{ 43, 8, 24, 0, 2, 3 }, /* SCIF0 TXI */
/* interrupt sources */
{ 44, 8, 16, 0, 3, 3 }, /* SCIF1 ERI */
{ 45, 8, 16, 0, 3, 3 }, /* SCIF1 RXI */
{ 46, 8, 16, 0, 3, 3 }, /* SCIF1 BRI */
{ 47, 8, 16, 0, 3, 3 }, /* SCIF1 TXI */
IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
{ 64, 0x14, 8, 0, 14, 2 }, /* PCIC0 */
{ 65, 0x14, 0, 0, 15, 2 }, /* PCIC1 */
{ 66, 0x18, 24, 0, 16, 2 }, /* PCIC2 */
{ 67, 0x18, 16, 0, 17, 2 }, /* PCIC3 */
{ 68, 0x18, 8, 0, 18, 2 }, /* PCIC4 */
IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
{ 60, 8, 8, 0, 4, 3 }, /* SCIF2 ERI, RXI, BRI, TXI */
{ 60, 8, 0, 0, 5, 3 }, /* SCIF3 ERI, RXI, BRI, TXI */
{ 60, 12, 24, 0, 6, 3 }, /* SCIF4 ERI, RXI, BRI, TXI */
{ 60, 12, 16, 0, 7, 3 }, /* SCIF5 ERI, RXI, BRI, TXI */
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
WDT,
TMU0, TMU1, TMU2, TMU2_TICPI,
HUDI,
DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
HSPI,
SCIF2, SCIF3, SCIF4, SCIF5,
PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
SIOF,
MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
DU,
GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI,
TMU3, TMU4, TMU5,
SSI0, SSI1,
HAC0, HAC1,
FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
GPIOI0, GPIOI1, GPIOI2, GPIOI3,
/* interrupt groups */
TMU012, DMAC0, SCIF0, SCIF1, DMAC1,
PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO
};
static struct intc2_desc intc2_irq_desc __read_mostly = {
.prio_base = 0xffd40000,
.msk_base = 0xffd40038,
.mskclr_base = 0xffd4003c,
.intc2_data = intc2_irq_table,
.nr_irqs = ARRAY_SIZE(intc2_irq_table),
.chip = {
.name = "INTC2-sh7785",
},
static struct intc_vect vectors[] __initdata = {
INTC_VECT(WDT, 0x560),
INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
INTC_VECT(HUDI, 0x600),
INTC_VECT(DMAC0_DMINT0, 0x620), INTC_VECT(DMAC0_DMINT1, 0x640),
INTC_VECT(DMAC0_DMINT2, 0x660), INTC_VECT(DMAC0_DMINT3, 0x680),
INTC_VECT(DMAC0_DMINT4, 0x6a0), INTC_VECT(DMAC0_DMINT5, 0x6c0),
INTC_VECT(DMAC0_DMAE, 0x6e0),
INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
INTC_VECT(DMAC1_DMINT6, 0x880), INTC_VECT(DMAC1_DMINT7, 0x8a0),
INTC_VECT(DMAC1_DMINT8, 0x8c0), INTC_VECT(DMAC1_DMINT9, 0x8e0),
INTC_VECT(DMAC1_DMINT10, 0x900), INTC_VECT(DMAC1_DMINT11, 0x920),
INTC_VECT(DMAC1_DMAE, 0x940),
INTC_VECT(HSPI, 0x960),
INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
INTC_VECT(SIOF, 0xc00),
INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
INTC_VECT(DU, 0xd80),
INTC_VECT(GDTA_GACLI, 0xda0), INTC_VECT(GDTA_GAMCI, 0xdc0),
INTC_VECT(GDTA_GAERI, 0xde0),
INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
INTC_VECT(TMU5, 0xe40),
INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20),
INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60),
INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0),
INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
};
static struct intc_group groups[] __initdata = {
INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE),
INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
INTC_GROUP(GDTA, GDTA_GACLI, GDTA_GAMCI, GDTA_GAERI),
INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
FLCTL_FLTRQ0, FLCTL_FLTRQ1),
INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
};
static struct intc_prio priorities[] __initdata = {
INTC_PRIO(SCIF0, 3),
INTC_PRIO(SCIF1, 3),
INTC_PRIO(SCIF2, 3),
INTC_PRIO(SCIF3, 3),
INTC_PRIO(SCIF4, 3),
INTC_PRIO(SCIF5, 3),
};
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
{ IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
{ 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
};
static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
IRQ4, IRQ5, IRQ6, IRQ7 } },
{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
TMU2, TMU2_TICPI } },
{ 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
{ 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
SCIF2, SCIF3 } },
{ 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
{ 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
{ 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
PCISERR, PCIINTA } },
{ 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
PCIINTD, PCIC5 } },
{ 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
{ 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
{ 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups, priorities,
mask_registers, prio_registers, NULL);
/* Support for external interrupt pins in IRQ mode */
static struct intc_vect vectors_irq0123[] __initdata = {
INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
};
static struct intc_vect vectors_irq4567[] __initdata = {
INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
};
static struct intc_sense_reg sense_registers[] __initdata = {
{ 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
IRQ4, IRQ5, IRQ6, IRQ7 } },
};
static DECLARE_INTC_DESC(intc_desc_irq0123, "sh7785-irq0123", vectors_irq0123,
NULL, NULL, mask_registers, prio_registers,
sense_registers);
static DECLARE_INTC_DESC(intc_desc_irq4567, "sh7785-irq4567", vectors_irq4567,
NULL, NULL, mask_registers, prio_registers,
sense_registers);
/* External interrupt pins in IRL mode */
static struct intc_vect vectors_irl0123[] __initdata = {
INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
INTC_VECT(IRL0_HHHL, 0x3c0),
};
static struct intc_vect vectors_irl4567[] __initdata = {
INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
INTC_VECT(IRL4_HHHL, 0xcc0),
};
static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
NULL, NULL, mask_registers, NULL, NULL);
static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
NULL, NULL, mask_registers, NULL, NULL);
#define INTC_ICR0 0xffd00000
#define INTC_INTMSK0 0xffd00044
#define INTC_INTMSK1 0xffd00048
#define INTC_INTMSK2 0xffd40080
#define INTC_INTMSKCLR1 0xffd00068
#define INTC_INTMSKCLR2 0xffd40084
void __init plat_irq_setup(void)
{
register_intc2_controller(&intc2_irq_desc);
/* disable IRQ3-0 + IRQ7-4 */
ctrl_outl(0xff000000, INTC_INTMSK0);
/* disable IRL3-0 + IRL7-4 */
ctrl_outl(0xc0000000, INTC_INTMSK1);
ctrl_outl(0xfffefffe, INTC_INTMSK2);
/* select IRL mode for IRL3-0 + IRL7-4 */
ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
/* disable holding function, ie enable "SH-4 Mode" */
ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
register_intc_controller(&intc_desc);
}
void __init plat_irq_setup_pins(int mode)
{
switch (mode) {
case IRQ_MODE_IRQ7654:
/* select IRQ mode for IRL7-4 */
ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
register_intc_controller(&intc_desc_irq4567);
break;
case IRQ_MODE_IRQ3210:
/* select IRQ mode for IRL3-0 */
ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
register_intc_controller(&intc_desc_irq0123);
break;
case IRQ_MODE_IRL7654:
/* enable IRL7-4 but don't provide any masking */
ctrl_outl(0x40000000, INTC_INTMSKCLR1);
ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
break;
case IRQ_MODE_IRL3210:
/* enable IRL0-3 but don't provide any masking */
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
break;
case IRQ_MODE_IRL7654_MASK:
/* enable IRL7-4 and mask using cpu intc controller */
ctrl_outl(0x40000000, INTC_INTMSKCLR1);
register_intc_controller(&intc_desc_irl4567);
break;
case IRQ_MODE_IRL3210_MASK:
/* enable IRL0-3 and mask using cpu intc controller */
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
register_intc_controller(&intc_desc_irl0123);
break;
default:
BUG();
}
}
void __init plat_mem_setup(void)
{
/* Register the URAM space as Node 1 */
setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
}

238
arch/sh/kernel/cpu/sh4a/setup-shx3.c
View File

@ -11,6 +11,7 @@
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/io.h>
#include <asm/mmzone.h>
#include <asm/sci.h>
static struct plat_sci_port sci_platform_data[] = {
@ -58,28 +59,229 @@ static int __init shx3_devices_setup(void)
}
__initcall(shx3_devices_setup);
static struct intc2_data intc2_irq_table[] = {
{ 16, 0, 0, 0, 1, 2 }, /* TMU0 */
{ 40, 4, 0, 0x20, 0, 3 }, /* SCIF0 ERI */
{ 41, 4, 0, 0x20, 1, 3 }, /* SCIF0 RXI */
{ 42, 4, 0, 0x20, 2, 3 }, /* SCIF0 BRI */
{ 43, 4, 0, 0x20, 3, 3 }, /* SCIF0 TXI */
enum {
UNUSED = 0,
/* interrupt sources */
IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
IRL_HHLL, IRL_HHLH, IRL_HHHL,
IRQ0, IRQ1, IRQ2, IRQ3,
HUDII,
TMU0, TMU1, TMU2, TMU3, TMU4, TMU5,
PCII0, PCII1, PCII2, PCII3, PCII4,
PCII5, PCII6, PCII7, PCII8, PCII9,
SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI,
DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
DU,
DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
IIC, VIN0, VIN1, VCORE0, ATAPI,
DTU0_TEND, DTU0_AE, DTU0_TMISS,
DTU1_TEND, DTU1_AE, DTU1_TMISS,
DTU2_TEND, DTU2_AE, DTU2_TMISS,
DTU3_TEND, DTU3_AE, DTU3_TMISS,
FE0, FE1,
GPIO0, GPIO1, GPIO2, GPIO3,
PAM, IRM,
INTICI0, INTICI1, INTICI2, INTICI3,
INTICI4, INTICI5, INTICI6, INTICI7,
/* interrupt groups */
IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3,
};
static struct intc2_desc intc2_irq_desc __read_mostly = {
.prio_base = 0xfe410000,
.msk_base = 0xfe410820,
.mskclr_base = 0xfe410850,
.intc2_data = intc2_irq_table,
.nr_irqs = ARRAY_SIZE(intc2_irq_table),
.chip = {
.name = "INTC2-SHX3",
},
static struct intc_vect vectors[] __initdata = {
INTC_VECT(HUDII, 0x3e0),
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460),
INTC_VECT(TMU4, 0x480), INTC_VECT(TMU5, 0x4a0),
INTC_VECT(PCII0, 0x500), INTC_VECT(PCII1, 0x520),
INTC_VECT(PCII2, 0x540), INTC_VECT(PCII3, 0x560),
INTC_VECT(PCII4, 0x580), INTC_VECT(PCII5, 0x5a0),
INTC_VECT(PCII6, 0x5c0), INTC_VECT(PCII7, 0x5e0),
INTC_VECT(PCII8, 0x600), INTC_VECT(PCII9, 0x620),
INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
INTC_VECT(SCIF2_ERI, 0x800), INTC_VECT(SCIF2_RXI, 0x820),
INTC_VECT(SCIF2_BRI, 0x840), INTC_VECT(SCIF2_TXI, 0x860),
INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0),
INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0),
INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920),
INTC_VECT(DMAC0_DMINT2, 0x940), INTC_VECT(DMAC0_DMINT3, 0x960),
INTC_VECT(DMAC0_DMINT4, 0x980), INTC_VECT(DMAC0_DMINT5, 0x9a0),
INTC_VECT(DMAC0_DMAE, 0x9c0),
INTC_VECT(DU, 0x9e0),
INTC_VECT(DMAC1_DMINT6, 0xa00), INTC_VECT(DMAC1_DMINT7, 0xa20),
INTC_VECT(DMAC1_DMINT8, 0xa40), INTC_VECT(DMAC1_DMINT9, 0xa60),
INTC_VECT(DMAC1_DMINT10, 0xa80), INTC_VECT(DMAC1_DMINT11, 0xaa0),
INTC_VECT(DMAC1_DMAE, 0xac0),
INTC_VECT(IIC, 0xae0),
INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20),
INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60),
INTC_VECT(DTU0_TEND, 0xc00), INTC_VECT(DTU0_AE, 0xc20),
INTC_VECT(DTU0_TMISS, 0xc40),
INTC_VECT(DTU1_TEND, 0xc60), INTC_VECT(DTU1_AE, 0xc80),
INTC_VECT(DTU1_TMISS, 0xca0),
INTC_VECT(DTU2_TEND, 0xcc0), INTC_VECT(DTU2_AE, 0xce0),
INTC_VECT(DTU2_TMISS, 0xd00),
INTC_VECT(DTU3_TEND, 0xd20), INTC_VECT(DTU3_AE, 0xd40),
INTC_VECT(DTU3_TMISS, 0xd60),
INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20),
INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
INTC_VECT(PAM, 0xec0), INTC_VECT(IRM, 0xee0),
INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
};
static struct intc_group groups[] __initdata = {
INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
IRL_HHLL, IRL_HHLH, IRL_HHHL),
INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI),
INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS),
INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS),
INTC_GROUP(DTU2, DTU2_TEND, DTU2_AE, DTU2_TMISS),
INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS),
};
static struct intc_prio priorities[] __initdata = {
INTC_PRIO(SCIF0, 3),
INTC_PRIO(SCIF1, 3),
INTC_PRIO(SCIF2, 3),
INTC_PRIO(SCIF3, 3),
};
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
{ IRQ0, IRQ1, IRQ2, IRQ3 } },
{ 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */
{ IRL } },
{ 0xfe410820, 0xfe410850, 32, /* CnINT2MSK0 / CnINT2MSKCLR0 */
{ FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } },
{ 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
{ 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2,
PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11,
DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7,
DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4,
DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } },
{ 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI,
SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI,
SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI,
SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } },
};
static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
{ 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
TMU3, TMU2, TMU1, TMU0 } },
{ 0xfe410804, 0, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0,
SCIF3, SCIF2,
SCIF1, SCIF0 } },
{ 0xfe410808, 0, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0,
PCII56789, PCII4,
PCII3, PCII2,
PCII1, PCII0 } },
{ 0xfe41080c, 0, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0,
VIN1, VIN0, IIC, DU} },
{ 0xfe410810, 0, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
GPIO2, GPIO1, GPIO0, IRM } },
{ 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
{ INTICI7, INTICI6, INTICI5, INTICI4,
INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 4) },
};
static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups, priorities,
mask_registers, prio_registers, NULL);
/* Support for external interrupt pins in IRQ mode */
static struct intc_vect vectors_irq[] __initdata = {
INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
};
static struct intc_sense_reg sense_registers[] __initdata = {
{ 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
};
static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
priorities, mask_registers, prio_registers,
sense_registers);
/* External interrupt pins in IRL mode */
static struct intc_vect vectors_irl[] __initdata = {
INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
INTC_VECT(IRL_HHHL, 0x3c0),
};
static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
priorities, mask_registers, prio_registers, NULL);
void __init plat_irq_setup_pins(int mode)
{
switch (mode) {
case IRQ_MODE_IRQ:
register_intc_controller(&intc_desc_irq);
break;
case IRQ_MODE_IRL3210:
register_intc_controller(&intc_desc_irl);
break;
default:
BUG();
}
}
void __init plat_irq_setup(void)
{
register_intc2_controller(&intc2_irq_desc);
register_intc_controller(&intc_desc);
}
void __init plat_mem_setup(void)
{
unsigned int nid = 1;
/* Register CPU#0 URAM space as Node 1 */
setup_bootmem_node(nid++, 0x145f0000, 0x14610000); /* CPU0 */
#if 0
/* XXX: Not yet.. */
setup_bootmem_node(nid++, 0x14df0000, 0x14e10000); /* CPU1 */
setup_bootmem_node(nid++, 0x155f0000, 0x15610000); /* CPU2 */
setup_bootmem_node(nid++, 0x15df0000, 0x15e10000); /* CPU3 */
#endif
setup_bootmem_node(nid++, 0x16000000, 0x16020000); /* CSM */
}

120
arch/sh/kernel/cpu/sh4a/smp-shx3.c Normal file
View File

@ -0,0 +1,120 @@
/*
* SH-X3 SMP
*
* Copyright (C) 2007 Paul Mundt
* Copyright (C) 2007 Magnus Damm
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/cpumask.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/io.h>
void __init plat_smp_setup(void)
{
unsigned int cpu = 0;
int i, num;
cpus_clear(cpu_possible_map);
cpu_set(cpu, cpu_possible_map);
__cpu_number_map[0] = 0;
__cpu_logical_map[0] = 0;
/*
* Do this stupidly for now.. we don't have an easy way to probe
* for the total number of cores.
*/
for (i = 1, num = 0; i < NR_CPUS; i++) {
cpu_set(i, cpu_possible_map);
__cpu_number_map[i] = ++num;
__cpu_logical_map[num] = i;
}
printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
}
void __init plat_prepare_cpus(unsigned int max_cpus)
{
}
#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
#define STBCR_MSTP 0x00000001
#define STBCR_RESET 0x00000002
#define STBCR_LTSLP 0x80000000
#define STBCR_AP_VAL (STBCR_RESET | STBCR_LTSLP)
void plat_start_cpu(unsigned int cpu, unsigned long entry_point)
{
ctrl_outl(entry_point, RESET_REG(cpu));
if (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP))
ctrl_outl(STBCR_MSTP, STBCR_REG(cpu));
while (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP))
;
/* Start up secondary processor by sending a reset */
ctrl_outl(STBCR_AP_VAL, STBCR_REG(cpu));
}
int plat_smp_processor_id(void)
{
return ctrl_inl(0xff000048); /* CPIDR */
}
void plat_send_ipi(unsigned int cpu, unsigned int message)
{
unsigned long addr = 0xfe410070 + (cpu * 4);
BUG_ON(cpu >= 4);
BUG_ON(message >= SMP_MSG_NR);
ctrl_outl(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
}
struct ipi_data {
void (*handler)(void *);
void *arg;
unsigned int message;
};
static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
{
struct ipi_data *id = arg;
unsigned int cpu = hard_smp_processor_id();
unsigned int offs = 4 * cpu;
unsigned int x;
x = ctrl_inl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
x &= (1 << (id->message << 2));
ctrl_outl(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
id->handler(id->arg);
return IRQ_HANDLED;
}
static struct ipi_data ipi_handlers[SMP_MSG_NR];
int plat_register_ipi_handler(unsigned int message,
void (*handler)(void *), void *arg)
{
struct ipi_data *id = &ipi_handlers[message];
BUG_ON(SMP_MSG_NR >= 8);
BUG_ON(message >= SMP_MSG_NR);
id->handler = handler;
id->arg = arg;
id->message = message;
return request_irq(104 + message, ipi_interrupt_handler, 0, "IPI", id);
}

3
arch/sh/kernel/cpufreq.c
View File

@ -77,8 +77,6 @@ static int sh_cpufreq_target(struct cpufreq_policy *policy,
static int sh_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
printk(KERN_INFO "cpufreq: SuperH CPU frequency driver.\n");
if (!cpu_online(policy->cpu))
return -ENODEV;
@ -143,6 +141,7 @@ static struct cpufreq_driver sh_cpufreq_driver = {
static int __init sh_cpufreq_module_init(void)
{
printk(KERN_INFO "cpufreq: SuperH CPU frequency driver.\n");
return cpufreq_register_driver(&sh_cpufreq_driver);
}

49
arch/sh/kernel/early_printk.c
View File

@ -3,7 +3,7 @@
*
* Copyright (C) 1999, 2000 Niibe Yutaka
* Copyright (C) 2002 M. R. Brown
* Copyright (C) 2004 - 2006 Paul Mundt
* Copyright (C) 2004 - 2007 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
@ -13,6 +13,7 @@
#include <linux/tty.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/delay.h>
#ifdef CONFIG_SH_STANDARD_BIOS
#include <asm/sh_bios.h>
@ -62,6 +63,16 @@ static struct console bios_console = {
#include <linux/serial_core.h>
#include "../../../drivers/serial/sh-sci.h"
#if defined(CONFIG_CPU_SUBTYPE_SH7720)
#define EPK_SCSMR_VALUE 0x000
#define EPK_SCBRR_VALUE 0x00C
#define EPK_FIFO_SIZE 64
#define EPK_FIFO_BITS (0x7f00 >> 8)
#else
#define EPK_FIFO_SIZE 16
#define EPK_FIFO_BITS (0x1f00 >> 8)
#endif
static struct uart_port scif_port = {
.mapbase = CONFIG_EARLY_SCIF_CONSOLE_PORT,
.membase = (char __iomem *)CONFIG_EARLY_SCIF_CONSOLE_PORT,
@ -69,7 +80,7 @@ static struct uart_port scif_port = {
static void scif_sercon_putc(int c)
{
while (((sci_in(&scif_port, SCFDR) & 0x1f00 >> 8) == 16))
while (((sci_in(&scif_port, SCFDR) & EPK_FIFO_BITS) >= EPK_FIFO_SIZE))
;
sci_out(&scif_port, SCxTDR, c);
@ -105,7 +116,22 @@ static struct console scif_console = {
.index = -1,
};
#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_STANDARD_BIOS)
#if !defined(CONFIG_SH_STANDARD_BIOS)
#if defined(CONFIG_CPU_SUBTYPE_SH7720)
static void scif_sercon_init(char *s)
{
sci_out(&scif_port, SCSCR, 0x0000); /* clear TE and RE */
sci_out(&scif_port, SCFCR, 0x4006); /* reset */
sci_out(&scif_port, SCSCR, 0x0000); /* select internal clock */
sci_out(&scif_port, SCSMR, EPK_SCSMR_VALUE);
sci_out(&scif_port, SCBRR, EPK_SCBRR_VALUE);
mdelay(1); /* wait 1-bit time */
sci_out(&scif_port, SCFCR, 0x0030); /* TTRG=b'11 */
sci_out(&scif_port, SCSCR, 0x0030); /* TE, RE */
}
#elif defined(CONFIG_CPU_SH4)
#define DEFAULT_BAUD 115200
/*
* Simple SCIF init, primarily aimed at SH7750 and other similar SH-4
@ -146,7 +172,8 @@ static void scif_sercon_init(char *s)
ctrl_outw(0, scif_port.mapbase + 36);
ctrl_outw(0x30, scif_port.mapbase + 8);
}
#endif /* CONFIG_CPU_SH4 && !CONFIG_SH_STANDARD_BIOS */
#endif /* defined(CONFIG_CPU_SUBTYPE_SH7720) */
#endif /* !defined(CONFIG_SH_STANDARD_BIOS) */
#endif /* CONFIG_EARLY_SCIF_CONSOLE */
/*
@ -163,18 +190,13 @@ static struct console *early_console =
#endif
;
static int __initdata keep_early;
static int early_console_initialized;
int __init setup_early_printk(char *buf)
static int __init setup_early_printk(char *buf)
{
int keep_early = 0;
if (!buf)
return 0;
if (early_console_initialized)
return 0;
early_console_initialized = 1;
if (strstr(buf, "keep"))
keep_early = 1;
@ -186,7 +208,8 @@ int __init setup_early_printk(char *buf)
if (!strncmp(buf, "serial", 6)) {
early_console = &scif_console;
#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_STANDARD_BIOS)
#if (defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SUBTYPE_SH7720)) && \
!defined(CONFIG_SH_STANDARD_BIOS)
scif_sercon_init(buf + 6);
#endif
}

2
arch/sh/kernel/entry-common.S
View File

@ -176,7 +176,7 @@ work_notifysig:
jmp @r1
lds r0, pr
work_resched:
#ifndef CONFIG_PREEMPT
#if defined(CONFIG_GUSA) && !defined(CONFIG_PREEMPT)
! gUSA handling
mov.l @(OFF_SP,r15), r0 ! get user space stack pointer
mov r0, r1

18
arch/sh/kernel/head.S
View File

@ -54,8 +54,8 @@ ENTRY(_stext)
mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF
ldc r0, sr
! Initialize global interrupt mask
mov #0, r0
#ifdef CONFIG_CPU_HAS_SR_RB
mov #0, r0
ldc r0, r6_bank
#endif
@ -72,15 +72,18 @@ ENTRY(_stext)
!
mov.l 2f, r0
mov r0, r15 ! Set initial r15 (stack pointer)
mov #(THREAD_SIZE >> 10), r1
shll8 r1 ! r1 = THREAD_SIZE
shll2 r1
sub r1, r0 !
#ifdef CONFIG_CPU_HAS_SR_RB
mov.l 7f, r0
ldc r0, r7_bank ! ... and initial thread_info
#endif
! Clear BSS area
#ifdef CONFIG_SMP
mov.l 3f, r0
cmp/eq #0, r0 ! skip clear if set to zero
bt 10f
#endif
mov.l 3f, r1
add #4, r1
mov.l 4f, r2
@ -89,13 +92,14 @@ ENTRY(_stext)
bf/s 9b ! while (r1 < r2)
mov.l r0,@-r2
10:
! Additional CPU initialization
mov.l 6f, r0
jsr @r0
nop
SYNCO() ! Wait for pending instructions..
! Start kernel
mov.l 5f, r0
jmp @r0
@ -107,8 +111,10 @@ ENTRY(_stext)
#else
1: .long 0x400080F0 ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF
#endif
ENTRY(stack_start)
2: .long init_thread_union+THREAD_SIZE
3: .long __bss_start
4: .long _end
5: .long start_kernel
6: .long sh_cpu_init
7: .long init_thread_union

53
arch/sh/kernel/kgdb_stub.c
View File

@ -150,13 +150,6 @@ struct kgdb_regs trap_registers;
char kgdb_in_gdb_mode;
char in_nmi; /* Set during NMI to prevent reentry */
int kgdb_nofault; /* Boolean to ignore bus errs (i.e. in GDB) */
int kgdb_enabled = 1; /* Default to enabled, cmdline can disable */
/* Exposed for user access */
struct task_struct *kgdb_current;
unsigned int kgdb_g_imask;
int kgdb_trapa_val;
int kgdb_excode;
/* Default values for SCI (can override via kernel args in setup.c) */
#ifndef CONFIG_KGDB_DEFPORT
@ -616,7 +609,7 @@ static short *get_step_address(void)
else
addr = trap_registers.pc + 2;
kgdb_flush_icache_range(addr, addr + 2);
flush_icache_range(addr, addr + 2);
return (short *) addr;
}
@ -639,8 +632,7 @@ static void do_single_step(void)
*addr = STEP_OPCODE;
/* Flush and return */
kgdb_flush_icache_range((long) addr, (long) addr + 2);
return;
flush_icache_range((long) addr, (long) addr + 2);
}
/* Undo a single step */
@ -650,7 +642,7 @@ static void undo_single_step(void)
/* Use stepped_address in case we stopped elsewhere */
if (stepped_opcode != 0) {
*(short*)stepped_address = stepped_opcode;
kgdb_flush_icache_range(stepped_address, stepped_address + 2);
flush_icache_range(stepped_address, stepped_address + 2);
}
stepped_opcode = 0;
}
@ -736,7 +728,7 @@ static void write_mem_msg(int binary)
ebin_to_mem(ptr, (char*)addr, length);
else
hex_to_mem(ptr, (char*)addr, length);
kgdb_flush_icache_range(addr, addr + length);
flush_icache_range(addr, addr + length);
ptr = 0;
send_ok_msg();
}
@ -815,14 +807,10 @@ static void set_regs_msg(void)
/*
* Bring up the ports..
*/
static int kgdb_serial_setup(void)
static int __init kgdb_serial_setup(void)
{
extern int kgdb_console_setup(struct console *co, char *options);
struct console dummy;
kgdb_console_setup(&dummy, 0);
return 0;
return kgdb_console_setup(&dummy, 0);
}
#else
#define kgdb_serial_setup() 0
@ -833,22 +821,6 @@ static void kgdb_command_loop(const int excep_code, const int trapa_value)
{
int sigval;
if (excep_code == NMI_VEC) {
#ifndef CONFIG_KGDB_NMI
printk(KERN_NOTICE "KGDB: Ignoring unexpected NMI?\n");
return;
#else /* CONFIG_KGDB_NMI */
if (!kgdb_enabled) {
kgdb_enabled = 1;
kgdb_init();
}
#endif /* CONFIG_KGDB_NMI */
}
/* Ignore if we're disabled */
if (!kgdb_enabled)
return;
/* Enter GDB mode (e.g. after detach) */
if (!kgdb_in_gdb_mode) {
/* Do serial setup, notify user, issue preemptive ack */
@ -959,18 +931,10 @@ static void handle_exception(struct pt_regs *regs)
/* Get excode for command loop call, user access */
asm("stc r2_bank, %0":"=r"(excep_code));
kgdb_excode = excep_code;
/* Other interesting environment items for reference */
asm("stc r6_bank, %0":"=r"(kgdb_g_imask));
kgdb_current = current;
kgdb_trapa_val = trapa_value;
/* Act on the exception */
kgdb_command_loop(excep_code, trapa_value);
kgdb_current = NULL;
/* Copy back the (maybe modified) registers */
for (count = 0; count < 16; count++)
regs->regs[count] = trap_registers.regs[count];
@ -994,11 +958,8 @@ asmlinkage void kgdb_handle_exception(unsigned long r4, unsigned long r5,
}
/* Initialise the KGDB data structures and serial configuration */
int kgdb_init(void)
int __init kgdb_init(void)
{
if (!kgdb_enabled)
return 1;
in_nmi = 0;
kgdb_nofault = 0;
stepped_opcode = 0;

8
arch/sh/kernel/process.c
View File

@ -19,6 +19,7 @@
#include <linux/tick.h>
#include <linux/reboot.h>
#include <linux/fs.h>
#include <linux/preempt.h>
#include <asm/uaccess.h>
#include <asm/mmu_context.h>
#include <asm/pgalloc.h>
@ -349,12 +350,11 @@ struct task_struct *__switch_to(struct task_struct *prev,
unlazy_fpu(prev, task_pt_regs(prev));
#endif
#ifdef CONFIG_PREEMPT
#if defined(CONFIG_GUSA) && defined(CONFIG_PREEMPT)
{
unsigned long flags;
struct pt_regs *regs;
local_irq_save(flags);
preempt_disable();
regs = task_pt_regs(prev);
if (user_mode(regs) && regs->regs[15] >= 0xc0000000) {
int offset = (int)regs->regs[15];
@ -365,7 +365,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
/* Go to rewind point */
regs->pc = regs->regs[0] + offset;
}
local_irq_restore(flags);
preempt_enable_no_resched();
}
#endif

15
arch/sh/kernel/setup.c
View File

@ -22,6 +22,7 @@
#include <linux/mm.h>
#include <linux/kexec.h>
#include <linux/module.h>
#include <linux/smp.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/page.h>
@ -42,7 +43,13 @@ extern void * __rd_start, * __rd_end;
* This value will be used at the very early stage of serial setup.
* The bigger value means no problem.
*/
struct sh_cpuinfo boot_cpu_data = { CPU_SH_NONE, 10000000, };
struct sh_cpuinfo cpu_data[NR_CPUS] __read_mostly = {
[0] = {
.type = CPU_SH_NONE,
.loops_per_jiffy = 10000000,
},
};
EXPORT_SYMBOL(cpu_data);
/*
* The machine vector. First entry in .machvec.init, or clobbered by
@ -272,6 +279,10 @@ void __init setup_arch(char **cmdline_p)
sh_mv.mv_setup(cmdline_p);
paging_init();
#ifdef CONFIG_SMP
plat_smp_setup();
#endif
}
static const char *cpu_name[] = {
@ -279,7 +290,7 @@ static const char *cpu_name[] = {
[CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
[CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
[CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710",
[CPU_SH7712] = "SH7712",
[CPU_SH7712] = "SH7712", [CPU_SH7720] = "SH7720",
[CPU_SH7729] = "SH7729", [CPU_SH7750] = "SH7750",
[CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R",
[CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R",

18
arch/sh/kernel/sh_ksyms.c
View File

@ -8,7 +8,7 @@
#include <linux/vmalloc.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <asm/sections.h>
#include <asm/semaphore.h>
#include <asm/processor.h>
#include <asm/uaccess.h>
@ -43,7 +43,6 @@ EXPORT_SYMBOL(memcpy);
EXPORT_SYMBOL(memset);
EXPORT_SYMBOL(memmove);
EXPORT_SYMBOL(__copy_user);
EXPORT_SYMBOL(boot_cpu_data);
#ifdef CONFIG_MMU
EXPORT_SYMBOL(get_vm_area);
@ -53,6 +52,7 @@ EXPORT_SYMBOL(get_vm_area);
EXPORT_SYMBOL(__up);
EXPORT_SYMBOL(__down);
EXPORT_SYMBOL(__down_interruptible);
EXPORT_SYMBOL(__down_trylock);
EXPORT_SYMBOL(__udelay);
EXPORT_SYMBOL(__ndelay);
@ -128,7 +128,8 @@ DECLARE_EXPORT(__movstrSI12_i4);
#endif /* __GNUC__ == 4 */
#endif
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \
defined(CONFIG_SH7705_CACHE_32KB))
/* needed by some modules */
EXPORT_SYMBOL(flush_cache_all);
EXPORT_SYMBOL(flush_cache_range);
@ -136,17 +137,11 @@ EXPORT_SYMBOL(flush_dcache_page);
EXPORT_SYMBOL(__flush_purge_region);
#endif
#if defined(CONFIG_MMU) && (defined(CONFIG_CPU_SH4) || \
defined(CONFIG_SH7705_CACHE_32KB))
#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \
(defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB))
EXPORT_SYMBOL(clear_user_page);
#endif
EXPORT_SYMBOL(__down_trylock);
#ifdef CONFIG_SMP
EXPORT_SYMBOL(synchronize_irq);
#endif
EXPORT_SYMBOL(csum_partial);
EXPORT_SYMBOL(csum_partial_copy_generic);
#ifdef CONFIG_IPV6
@ -154,3 +149,4 @@ EXPORT_SYMBOL(csum_ipv6_magic);
#endif
EXPORT_SYMBOL(clear_page);
EXPORT_SYMBOL(__clear_user);
EXPORT_SYMBOL(_ebss);

10
arch/sh/kernel/signal.c
View File

@ -507,13 +507,11 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
ctrl_inw(regs->pc - 4));
break;
}
#ifdef CONFIG_GUSA
} else {
/* gUSA handling */
#ifdef CONFIG_PREEMPT
unsigned long flags;
preempt_disable();
local_irq_save(flags);
#endif
if (regs->regs[15] >= 0xc0000000) {
int offset = (int)regs->regs[15];
@ -524,8 +522,8 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
regs->pc = regs->regs[0] + offset -
instruction_size(ctrl_inw(regs->pc-4));
}
#ifdef CONFIG_PREEMPT
local_irq_restore(flags);
preempt_enable_no_resched();
#endif
}

307
arch/sh/kernel/smp.c
View File

@ -3,69 +3,41 @@
*
* SMP support for the SuperH processors.
*
* Copyright (C) 2002, 2003 Paul Mundt
* Copyright (C) 2002 - 2007 Paul Mundt
* Copyright (C) 2006 - 2007 Akio Idehara
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/err.h>
#include <linux/cache.h>
#include <linux/cpumask.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/threads.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <asm/atomic.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
#include <asm/smp.h>
#include <asm/cacheflush.h>
#include <asm/sections.h>
/*
* This was written with the Sega Saturn (SMP SH-2 7604) in mind,
* but is designed to be usable regardless if there's an MMU
* present or not.
*/
struct sh_cpuinfo cpu_data[NR_CPUS];
extern void per_cpu_trap_init(void);
int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
cpumask_t cpu_possible_map;
EXPORT_SYMBOL(cpu_possible_map);
cpumask_t cpu_online_map;
EXPORT_SYMBOL(cpu_online_map);
static atomic_t cpus_booted = ATOMIC_INIT(0);
/* These are defined by the board-specific code. */
/*
* Cause the function described by call_data to be executed on the passed
* cpu. When the function has finished, increment the finished field of
* call_data.
*/
void __smp_send_ipi(unsigned int cpu, unsigned int action);
/*
* Find the number of available processors
*/
unsigned int __smp_probe_cpus(void);
/*
* Start a particular processor
*/
void __smp_slave_init(unsigned int cpu);
/*
* Run specified function on a particular processor.
*/
@ -73,74 +45,123 @@ void __smp_call_function(unsigned int cpu);
static inline void __init smp_store_cpu_info(unsigned int cpu)
{
cpu_data[cpu].loops_per_jiffy = loops_per_jiffy;
struct sh_cpuinfo *c = cpu_data + cpu;
c->loops_per_jiffy = loops_per_jiffy;
}
void __init smp_prepare_cpus(unsigned int max_cpus)
{
unsigned int cpu = smp_processor_id();
int i;
atomic_set(&cpus_booted, 1);
smp_store_cpu_info(cpu);
for (i = 0; i < __smp_probe_cpus(); i++)
cpu_set(i, cpu_possible_map);
init_new_context(current, &init_mm);
current_thread_info()->cpu = cpu;
plat_prepare_cpus(max_cpus);
#ifndef CONFIG_HOTPLUG_CPU
cpu_present_map = cpu_possible_map;
#endif
}
void __devinit smp_prepare_boot_cpu(void)
{
unsigned int cpu = smp_processor_id();
__cpu_number_map[0] = cpu;
__cpu_logical_map[0] = cpu;
cpu_set(cpu, cpu_online_map);
cpu_set(cpu, cpu_possible_map);
}
int __cpu_up(unsigned int cpu)
asmlinkage void __cpuinit start_secondary(void)
{
struct task_struct *tsk;
unsigned int cpu;
struct mm_struct *mm = &init_mm;
tsk = fork_idle(cpu);
atomic_inc(&mm->mm_count);
atomic_inc(&mm->mm_users);
current->active_mm = mm;
BUG_ON(current->mm);
enter_lazy_tlb(mm, current);
if (IS_ERR(tsk))
panic("Failed forking idle task for cpu %d\n", cpu);
task_thread_info(tsk)->cpu = cpu;
per_cpu_trap_init();
preempt_disable();
local_irq_enable();
calibrate_delay();
cpu = smp_processor_id();
smp_store_cpu_info(cpu);
cpu_set(cpu, cpu_online_map);
return 0;
cpu_idle();
}
int start_secondary(void *unused)
extern struct {
unsigned long sp;
unsigned long bss_start;
unsigned long bss_end;
void *start_kernel_fn;
void *cpu_init_fn;
void *thread_info;
} stack_start;
int __cpuinit __cpu_up(unsigned int cpu)
{
unsigned int cpu;
struct task_struct *tsk;
unsigned long timeout;
cpu = smp_processor_id();
tsk = fork_idle(cpu);
if (IS_ERR(tsk)) {
printk(KERN_ERR "Failed forking idle task for cpu %d\n", cpu);
return PTR_ERR(tsk);
}
atomic_inc(&init_mm.mm_count);
current->active_mm = &init_mm;
/* Fill in data in head.S for secondary cpus */
stack_start.sp = tsk->thread.sp;
stack_start.thread_info = tsk->stack;
stack_start.bss_start = 0; /* don't clear bss for secondary cpus */
stack_start.start_kernel_fn = start_secondary;
smp_store_cpu_info(cpu);
flush_cache_all();
__smp_slave_init(cpu);
preempt_disable();
per_cpu_trap_init();
atomic_inc(&cpus_booted);
plat_start_cpu(cpu, (unsigned long)_stext);
cpu_idle();
return 0;
timeout = jiffies + HZ;
while (time_before(jiffies, timeout)) {
if (cpu_online(cpu))
break;
udelay(10);
}
if (cpu_online(cpu))
return 0;
return -ENOENT;
}
void __init smp_cpus_done(unsigned int max_cpus)
{
smp_mb();
unsigned long bogosum = 0;
int cpu;
for_each_online_cpu(cpu)
bogosum += cpu_data[cpu].loops_per_jiffy;
printk(KERN_INFO "SMP: Total of %d processors activated "
"(%lu.%02lu BogoMIPS).\n", num_online_cpus(),
bogosum / (500000/HZ),
(bogosum / (5000/HZ)) % 100);
}
void smp_send_reschedule(int cpu)
{
__smp_send_ipi(cpu, SMP_MSG_RESCHEDULE);
plat_send_ipi(cpu, SMP_MSG_RESCHEDULE);
}
static void stop_this_cpu(void *unused)
@ -157,7 +178,6 @@ void smp_send_stop(void)
smp_call_function(stop_this_cpu, 0, 1, 0);
}
struct smp_fn_call_struct smp_fn_call = {
.lock = SPIN_LOCK_UNLOCKED,
.finished = ATOMIC_INIT(0),
@ -175,9 +195,6 @@ int smp_call_function(void (*func)(void *info), void *info, int retry, int wait)
unsigned int nr_cpus = atomic_read(&cpus_booted);
int i;
if (nr_cpus < 2)
return 0;
/* Can deadlock when called with interrupts disabled */
WARN_ON(irqs_disabled());
@ -189,7 +206,7 @@ int smp_call_function(void (*func)(void *info), void *info, int retry, int wait)
for (i = 0; i < nr_cpus; i++)
if (i != smp_processor_id())
__smp_call_function(i);
plat_send_ipi(i, SMP_MSG_FUNCTION);
if (wait)
while (atomic_read(&smp_fn_call.finished) != (nr_cpus - 1));
@ -205,3 +222,143 @@ int setup_profiling_timer(unsigned int multiplier)
return 0;
}
static void flush_tlb_all_ipi(void *info)
{
local_flush_tlb_all();
}
void flush_tlb_all(void)
{
on_each_cpu(flush_tlb_all_ipi, 0, 1, 1);
}
static void flush_tlb_mm_ipi(void *mm)
{
local_flush_tlb_mm((struct mm_struct *)mm);
}
/*
* The following tlb flush calls are invoked when old translations are
* being torn down, or pte attributes are changing. For single threaded
* address spaces, a new context is obtained on the current cpu, and tlb
* context on other cpus are invalidated to force a new context allocation
* at switch_mm time, should the mm ever be used on other cpus. For
* multithreaded address spaces, intercpu interrupts have to be sent.
* Another case where intercpu interrupts are required is when the target
* mm might be active on another cpu (eg debuggers doing the flushes on
* behalf of debugees, kswapd stealing pages from another process etc).
* Kanoj 07/00.
*/
void flush_tlb_mm(struct mm_struct *mm)
{
preempt_disable();
if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
smp_call_function(flush_tlb_mm_ipi, (void *)mm, 1, 1);
} else {
int i;
for (i = 0; i < num_online_cpus(); i++)
if (smp_processor_id() != i)
cpu_context(i, mm) = 0;
}
local_flush_tlb_mm(mm);
preempt_enable();
}
struct flush_tlb_data {
struct vm_area_struct *vma;
unsigned long addr1;
unsigned long addr2;
};
static void flush_tlb_range_ipi(void *info)
{
struct flush_tlb_data *fd = (struct flush_tlb_data *)info;
local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
}
void flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
struct mm_struct *mm = vma->vm_mm;
preempt_disable();
if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
struct flush_tlb_data fd;
fd.vma = vma;
fd.addr1 = start;
fd.addr2 = end;
smp_call_function(flush_tlb_range_ipi, (void *)&fd, 1, 1);
} else {
int i;
for (i = 0; i < num_online_cpus(); i++)
if (smp_processor_id() != i)
cpu_context(i, mm) = 0;
}
local_flush_tlb_range(vma, start, end);
preempt_enable();
}
static void flush_tlb_kernel_range_ipi(void *info)
{
struct flush_tlb_data *fd = (struct flush_tlb_data *)info;
local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
}
void flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
struct flush_tlb_data fd;
fd.addr1 = start;
fd.addr2 = end;
on_each_cpu(flush_tlb_kernel_range_ipi, (void *)&fd, 1, 1);
}
static void flush_tlb_page_ipi(void *info)
{
struct flush_tlb_data *fd = (struct flush_tlb_data *)info;
local_flush_tlb_page(fd->vma, fd->addr1);
}
void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
preempt_disable();
if ((atomic_read(&vma->vm_mm->mm_users) != 1) ||
(current->mm != vma->vm_mm)) {
struct flush_tlb_data fd;
fd.vma = vma;
fd.addr1 = page;
smp_call_function(flush_tlb_page_ipi, (void *)&fd, 1, 1);
} else {
int i;
for (i = 0; i < num_online_cpus(); i++)
if (smp_processor_id() != i)
cpu_context(i, vma->vm_mm) = 0;
}
local_flush_tlb_page(vma, page);
preempt_enable();
}
static void flush_tlb_one_ipi(void *info)
{
struct flush_tlb_data *fd = (struct flush_tlb_data *)info;
local_flush_tlb_one(fd->addr1, fd->addr2);
}
void flush_tlb_one(unsigned long asid, unsigned long vaddr)
{
struct flush_tlb_data fd;
fd.addr1 = asid;
fd.addr2 = vaddr;
smp_call_function(flush_tlb_one_ipi, (void *)&fd, 1, 1);
local_flush_tlb_one(asid, vaddr);
}

18
arch/sh/kernel/syscalls.S
View File

@ -14,24 +14,6 @@
#include <linux/sys.h>
#include <linux/linkage.h>
#if !defined(CONFIG_NFSD) && !defined(CONFIG_NFSD_MODULE)
#define sys_nfsservctl sys_ni_syscall
#endif
#if !defined(CONFIG_MMU)
#define sys_madvise sys_ni_syscall
#define sys_readahead sys_ni_syscall
#define sys_mprotect sys_ni_syscall
#define sys_msync sys_ni_syscall
#define sys_mlock sys_ni_syscall
#define sys_munlock sys_ni_syscall
#define sys_mlockall sys_ni_syscall
#define sys_munlockall sys_ni_syscall
#define sys_mremap sys_ni_syscall
#define sys_mincore sys_ni_syscall
#define sys_remap_file_pages sys_ni_syscall
#endif
.data
ENTRY(sys_call_table)
.long sys_restart_syscall /* 0 - old "setup()" system call*/

3
arch/sh/kernel/timers/timer-tmu.c
View File

@ -173,7 +173,8 @@ static int tmu_timer_init(void)
tmu_timer_stop();
#if !defined(CONFIG_CPU_SUBTYPE_SH7760) && \
#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
!defined(CONFIG_CPU_SUBTYPE_SH7760) && \
!defined(CONFIG_CPU_SUBTYPE_SH7785) && \
!defined(CONFIG_CPU_SUBTYPE_SHX3)
ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);

5
arch/sh/kernel/traps.c
View File

@ -807,12 +807,13 @@ static inline void __init gdb_vbr_init(void)
}
#endif
void __init per_cpu_trap_init(void)
void __cpuinit per_cpu_trap_init(void)
{
extern void *vbr_base;
#ifdef CONFIG_SH_STANDARD_BIOS
gdb_vbr_init();
if (raw_smp_processor_id() == 0)
gdb_vbr_init();
#endif
/* NOTE: The VBR value should be at P1

10
arch/sh/kernel/vmlinux.lds.S
View File

@ -62,6 +62,8 @@ SECTIONS
__nosave_end = .;
PERCPU(PAGE_SIZE)
. = ALIGN(L1_CACHE_BYTES);
.data.cacheline_aligned : { *(.data.cacheline_aligned) }
_edata = .; /* End of data section */
@ -89,7 +91,14 @@ SECTIONS
__con_initcall_end = .;
SECURITY_INIT
/* .exit.text is discarded at runtime, not link time, to deal with
references from .rodata */
.exit.text : { *(.exit.text) }
.exit.data : { *(.exit.data) }
#ifdef CONFIG_BLK_DEV_INITRD
. = ALIGN(PAGE_SIZE);
__initramfs_start = .;
.init.ramfs : { *(.init.ramfs) }
__initramfs_end = .;
@ -107,6 +116,7 @@ SECTIONS
*(.bss.page_aligned)
*(.bss)
. = ALIGN(4);
_ebss = .; /* uClinux MTD sucks */
_end = . ;
}

67
arch/sh/mm/Kconfig
View File

@ -2,7 +2,6 @@
# Processor families
#
config CPU_SH2
select SH_WRITETHROUGH if !CPU_SH2A
bool
config CPU_SH2A
@ -19,6 +18,7 @@ config CPU_SH4
select CPU_HAS_INTEVT
select CPU_HAS_SR_RB
select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
select CPU_HAS_FPU if !CPU_SH4AL_DSP
config CPU_SH4A
bool
@ -32,7 +32,6 @@ config CPU_SH4AL_DSP
config CPU_SUBTYPE_ST40
bool
select CPU_SH4
select CPU_HAS_INTC2_IRQ
config CPU_SHX2
bool
@ -52,26 +51,22 @@ choice
config CPU_SUBTYPE_SH7619
bool "Support SH7619 processor"
select CPU_SH2
select CPU_HAS_IPR_IRQ
# SH-2A Processor Support
config CPU_SUBTYPE_SH7206
bool "Support SH7206 processor"
select CPU_SH2A
select CPU_HAS_IPR_IRQ
# SH-3 Processor Support
config CPU_SUBTYPE_SH7705
bool "Support SH7705 processor"
select CPU_SH3
select CPU_HAS_IPR_IRQ
config CPU_SUBTYPE_SH7706
bool "Support SH7706 processor"
select CPU_SH3
select CPU_HAS_IPR_IRQ
help
Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
@ -91,14 +86,12 @@ config CPU_SUBTYPE_SH7708
config CPU_SUBTYPE_SH7709
bool "Support SH7709 processor"
select CPU_SH3
select CPU_HAS_IPR_IRQ
help
Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
config CPU_SUBTYPE_SH7710
bool "Support SH7710 processor"
select CPU_SH3
select CPU_HAS_IPR_IRQ
select CPU_HAS_DSP
help
Select SH7710 if you have a SH3-DSP SH7710 CPU.
@ -106,24 +99,28 @@ config CPU_SUBTYPE_SH7710
config CPU_SUBTYPE_SH7712
bool "Support SH7712 processor"
select CPU_SH3
select CPU_HAS_IPR_IRQ
select CPU_HAS_DSP
help
Select SH7712 if you have a SH3-DSP SH7712 CPU.
config CPU_SUBTYPE_SH7720
bool "Support SH7720 processor"
select CPU_SH3
select CPU_HAS_DSP
help
Select SH7720 if you have a SH3-DSP SH7720 CPU.
# SH-4 Processor Support
config CPU_SUBTYPE_SH7750
bool "Support SH7750 processor"
select CPU_SH4
select CPU_HAS_INTC_IRQ
help
Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
config CPU_SUBTYPE_SH7091
bool "Support SH7091 processor"
select CPU_SH4
select CPU_HAS_INTC_IRQ
help
Select SH7091 if you have an SH-4 based Sega device (such as
the Dreamcast, Naomi, and Naomi 2).
@ -131,17 +128,14 @@ config CPU_SUBTYPE_SH7091
config CPU_SUBTYPE_SH7750R
bool "Support SH7750R processor"
select CPU_SH4
select CPU_HAS_INTC_IRQ
config CPU_SUBTYPE_SH7750S
bool "Support SH7750S processor"
select CPU_SH4
select CPU_HAS_INTC_IRQ
config CPU_SUBTYPE_SH7751
bool "Support SH7751 processor"
select CPU_SH4
select CPU_HAS_INTC_IRQ
help
Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
or if you have a HD6417751R CPU.
@ -149,13 +143,10 @@ config CPU_SUBTYPE_SH7751
config CPU_SUBTYPE_SH7751R
bool "Support SH7751R processor"
select CPU_SH4
select CPU_HAS_INTC_IRQ
config CPU_SUBTYPE_SH7760
bool "Support SH7760 processor"
select CPU_SH4
select CPU_HAS_INTC2_IRQ
select CPU_HAS_IPR_IRQ
config CPU_SUBTYPE_SH4_202
bool "Support SH4-202 processor"
@ -185,19 +176,21 @@ config CPU_SUBTYPE_SH7770
config CPU_SUBTYPE_SH7780
bool "Support SH7780 processor"
select CPU_SH4A
select CPU_HAS_INTC_IRQ
config CPU_SUBTYPE_SH7785
bool "Support SH7785 processor"
select CPU_SH4A
select CPU_SHX2
select CPU_HAS_INTC2_IRQ
select ARCH_SPARSEMEM_ENABLE
select SYS_SUPPORTS_NUMA
config CPU_SUBTYPE_SHX3
bool "Support SH-X3 processor"
select CPU_SH4A
select CPU_SHX3
select CPU_HAS_INTC2_IRQ
select ARCH_SPARSEMEM_ENABLE
select SYS_SUPPORTS_NUMA
select SYS_SUPPORTS_SMP
# SH4AL-DSP Processor Support
@ -209,7 +202,6 @@ config CPU_SUBTYPE_SH7722
bool "Support SH7722 processor"
select CPU_SH4AL_DSP
select CPU_SHX2
select CPU_HAS_INTC_IRQ
select ARCH_SPARSEMEM_ENABLE
select SYS_SUPPORTS_NUMA
@ -274,7 +266,7 @@ config 32BIT
config X2TLB
bool "Enable extended TLB mode"
depends on CPU_SHX2 && MMU && EXPERIMENTAL
depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
help
Selecting this option will enable the extended mode of the SH-X2
TLB. For legacy SH-X behaviour and interoperability, say N. For
@ -307,6 +299,7 @@ config NUMA
config NODES_SHIFT
int
default "3" if CPU_SUBTYPE_SHX3
default "1"
depends on NEED_MULTIPLE_NODES
@ -323,7 +316,9 @@ config ARCH_SPARSEMEM_DEFAULT
config MAX_ACTIVE_REGIONS
int
default "2" if (CPU_SUBTYPE_SH7722 && SPARSEMEM)
default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
CPU_SUBTYPE_SH7785)
default "1"
config ARCH_POPULATES_NODE_MAP
@ -342,25 +337,27 @@ config ARCH_MEMORY_PROBE
choice
prompt "Kernel page size"
default PAGE_SIZE_8KB if X2TLB
default PAGE_SIZE_4KB
config PAGE_SIZE_4KB
bool "4kB"
depends on !X2TLB
help
This is the default page size used by all SuperH CPUs.
config PAGE_SIZE_8KB
bool "8kB"
depends on EXPERIMENTAL && X2TLB
depends on X2TLB
help
This enables 8kB pages as supported by SH-X2 and later MMUs.
config PAGE_SIZE_64KB
bool "64kB"
depends on EXPERIMENTAL && CPU_SH4
depends on CPU_SH4
help
This enables support for 64kB pages, possible on all SH-4
CPUs and later. Highly experimental, not recommended.
CPUs and later.
endchoice
@ -412,8 +409,17 @@ config SH_DIRECT_MAPPED
Turn this option off for platforms that do not have a direct-mapped
cache, and you have no need to run the caches in such a configuration.
config SH_WRITETHROUGH
bool "Use write-through caching"
choice
prompt "Cache mode"
default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
config CACHE_WRITEBACK
bool "Write-back"
depends on CPU_SH2A || CPU_SH3 || CPU_SH4
config CACHE_WRITETHROUGH
bool "Write-through"
help
Selecting this option will configure the caches in write-through
mode, as opposed to the default write-back configuration.
@ -424,4 +430,9 @@ config SH_WRITETHROUGH
If unsure, say N.
config CACHE_OFF
bool "Off"
endchoice
endmenu

23
arch/sh/mm/Makefile
View File

@ -4,29 +4,32 @@
obj-y := init.o extable.o consistent.o
obj-$(CONFIG_CPU_SH2) += cache-sh2.o
obj-$(CONFIG_CPU_SH3) += cache-sh3.o
obj-$(CONFIG_CPU_SH4) += cache-sh4.o
ifndef CONFIG_CACHE_OFF
obj-$(CONFIG_CPU_SH2) += cache-sh2.o
obj-$(CONFIG_CPU_SH3) += cache-sh3.o
obj-$(CONFIG_CPU_SH4) += cache-sh4.o
obj-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o
endif
mmu-y := tlb-nommu.o pg-nommu.o
mmu-$(CONFIG_CPU_SH3) += fault-nommu.o
mmu-$(CONFIG_CPU_SH4) += fault-nommu.o
mmu-$(CONFIG_MMU) := fault.o clear_page.o copy_page.o tlb-flush.o \
ioremap.o
obj-y += $(mmu-y)
ifdef CONFIG_DEBUG_FS
obj-$(CONFIG_CPU_SH4) += cache-debugfs.o
obj-$(CONFIG_CPU_SH4) += cache-debugfs.o
endif
ifdef CONFIG_MMU
obj-$(CONFIG_CPU_SH3) += tlb-sh3.o
obj-$(CONFIG_CPU_SH4) += tlb-sh4.o pg-sh4.o
obj-$(CONFIG_SH7705_CACHE_32KB) += pg-sh7705.o
obj-$(CONFIG_CPU_SH3) += tlb-sh3.o
obj-$(CONFIG_CPU_SH4) += tlb-sh4.o
ifndef CONFIG_CACHE_OFF
obj-$(CONFIG_CPU_SH4) += pg-sh4.o
obj-$(CONFIG_SH7705_CACHE_32KB) += pg-sh7705.o
endif
endif
obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
obj-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o
obj-$(CONFIG_32BIT) += pmb.o
obj-$(CONFIG_NUMA) += numa.o

81
arch/sh/mm/cache-sh4.c
View File

@ -2,7 +2,7 @@
* arch/sh/mm/cache-sh4.c
*
* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
* Copyright (C) 2001 - 2006 Paul Mundt
* Copyright (C) 2001 - 2007 Paul Mundt
* Copyright (C) 2003 Richard Curnow
*
* This file is subject to the terms and conditions of the GNU General Public
@ -44,7 +44,7 @@ static void (*__flush_dcache_segment_fn)(unsigned long, unsigned long) =
static void compute_alias(struct cache_info *c)
{
c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
c->n_aliases = (c->alias_mask >> PAGE_SHIFT) + 1;
c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
}
static void __init emit_cache_params(void)
@ -54,21 +54,35 @@ static void __init emit_cache_params(void)
ctrl_inl(CCN_CVR),
ctrl_inl(CCN_PRR));
printk("I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
current_cpu_data.icache.ways,
current_cpu_data.icache.sets,
current_cpu_data.icache.way_incr);
boot_cpu_data.icache.ways,
boot_cpu_data.icache.sets,
boot_cpu_data.icache.way_incr);
printk("I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
current_cpu_data.icache.entry_mask,
current_cpu_data.icache.alias_mask,
current_cpu_data.icache.n_aliases);
boot_cpu_data.icache.entry_mask,
boot_cpu_data.icache.alias_mask,
boot_cpu_data.icache.n_aliases);
printk("D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
current_cpu_data.dcache.ways,
current_cpu_data.dcache.sets,
current_cpu_data.dcache.way_incr);
boot_cpu_data.dcache.ways,
boot_cpu_data.dcache.sets,
boot_cpu_data.dcache.way_incr);
printk("D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
current_cpu_data.dcache.entry_mask,
current_cpu_data.dcache.alias_mask,
current_cpu_data.dcache.n_aliases);
boot_cpu_data.dcache.entry_mask,
boot_cpu_data.dcache.alias_mask,
boot_cpu_data.dcache.n_aliases);
/*
* Emit Secondary Cache parameters if the CPU has a probed L2.
*/
if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
printk("S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
boot_cpu_data.scache.ways,
boot_cpu_data.scache.sets,
boot_cpu_data.scache.way_incr);
printk("S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
boot_cpu_data.scache.entry_mask,
boot_cpu_data.scache.alias_mask,
boot_cpu_data.scache.n_aliases);
}
if (!__flush_dcache_segment_fn)
panic("unknown number of cache ways\n");
@ -79,10 +93,11 @@ static void __init emit_cache_params(void)
*/
void __init p3_cache_init(void)
{
compute_alias(&current_cpu_data.icache);
compute_alias(&current_cpu_data.dcache);
compute_alias(&boot_cpu_data.icache);
compute_alias(&boot_cpu_data.dcache);
compute_alias(&boot_cpu_data.scache);
switch (current_cpu_data.dcache.ways) {
switch (boot_cpu_data.dcache.ways) {
case 1:
__flush_dcache_segment_fn = __flush_dcache_segment_1way;
break;
@ -187,13 +202,13 @@ void flush_cache_sigtramp(unsigned long addr)
: "m" (__m(v)));
index = CACHE_IC_ADDRESS_ARRAY |
(v & current_cpu_data.icache.entry_mask);
(v & boot_cpu_data.icache.entry_mask);
local_irq_save(flags);
jump_to_P2();
for (i = 0; i < current_cpu_data.icache.ways;
i++, index += current_cpu_data.icache.way_incr)
for (i = 0; i < boot_cpu_data.icache.ways;
i++, index += boot_cpu_data.icache.way_incr)
ctrl_outl(0, index); /* Clear out Valid-bit */
back_to_P1();
@ -210,7 +225,7 @@ static inline void flush_cache_4096(unsigned long start,
* All types of SH-4 require PC to be in P2 to operate on the I-cache.
* Some types of SH-4 require PC to be in P2 to operate on the D-cache.
*/
if ((current_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) ||
if ((boot_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) ||
(start < CACHE_OC_ADDRESS_ARRAY))
exec_offset = 0x20000000;
@ -232,7 +247,7 @@ void flush_dcache_page(struct page *page)
int i, n;
/* Loop all the D-cache */
n = current_cpu_data.dcache.n_aliases;
n = boot_cpu_data.dcache.n_aliases;
for (i = 0; i < n; i++, addr += 4096)
flush_cache_4096(addr, phys);
}
@ -264,7 +279,7 @@ static inline void flush_icache_all(void)
void flush_dcache_all(void)
{
(*__flush_dcache_segment_fn)(0UL, current_cpu_data.dcache.way_size);
(*__flush_dcache_segment_fn)(0UL, boot_cpu_data.dcache.way_size);
wmb();
}
@ -278,8 +293,8 @@ static void __flush_cache_mm(struct mm_struct *mm, unsigned long start,
unsigned long end)
{
unsigned long d = 0, p = start & PAGE_MASK;
unsigned long alias_mask = current_cpu_data.dcache.alias_mask;
unsigned long n_aliases = current_cpu_data.dcache.n_aliases;
unsigned long alias_mask = boot_cpu_data.dcache.alias_mask;
unsigned long n_aliases = boot_cpu_data.dcache.n_aliases;
unsigned long select_bit;
unsigned long all_aliases_mask;
unsigned long addr_offset;
@ -366,7 +381,7 @@ void flush_cache_mm(struct mm_struct *mm)
* If cache is only 4k-per-way, there are never any 'aliases'. Since
* the cache is physically tagged, the data can just be left in there.
*/
if (current_cpu_data.dcache.n_aliases == 0)
if (boot_cpu_data.dcache.n_aliases == 0)
return;
/*
@ -403,7 +418,7 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long address,
unsigned long phys = pfn << PAGE_SHIFT;
unsigned int alias_mask;
alias_mask = current_cpu_data.dcache.alias_mask;
alias_mask = boot_cpu_data.dcache.alias_mask;
/* We only need to flush D-cache when we have alias */
if ((address^phys) & alias_mask) {
@ -417,7 +432,7 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long address,
phys);
}
alias_mask = current_cpu_data.icache.alias_mask;
alias_mask = boot_cpu_data.icache.alias_mask;
if (vma->vm_flags & VM_EXEC) {
/*
* Evict entries from the portion of the cache from which code
@ -449,7 +464,7 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
* If cache is only 4k-per-way, there are never any 'aliases'. Since
* the cache is physically tagged, the data can just be left in there.
*/
if (current_cpu_data.dcache.n_aliases == 0)
if (boot_cpu_data.dcache.n_aliases == 0)
return;
/*
@ -510,7 +525,7 @@ static void __flush_cache_4096(unsigned long addr, unsigned long phys,
unsigned long a, ea, p;
unsigned long temp_pc;
dcache = &current_cpu_data.dcache;
dcache = &boot_cpu_data.dcache;
/* Write this way for better assembly. */
way_count = dcache->ways;
way_incr = dcache->way_incr;
@ -585,7 +600,7 @@ static void __flush_dcache_segment_1way(unsigned long start,
base_addr = ((base_addr >> 16) << 16);
base_addr |= start;
dcache = &current_cpu_data.dcache;
dcache = &boot_cpu_data.dcache;
linesz = dcache->linesz;
way_incr = dcache->way_incr;
way_size = dcache->way_size;
@ -627,7 +642,7 @@ static void __flush_dcache_segment_2way(unsigned long start,
base_addr = ((base_addr >> 16) << 16);
base_addr |= start;
dcache = &current_cpu_data.dcache;
dcache = &boot_cpu_data.dcache;
linesz = dcache->linesz;
way_incr = dcache->way_incr;
way_size = dcache->way_size;
@ -686,7 +701,7 @@ static void __flush_dcache_segment_4way(unsigned long start,
base_addr = ((base_addr >> 16) << 16);
base_addr |= start;
dcache = &current_cpu_data.dcache;
dcache = &boot_cpu_data.dcache;
linesz = dcache->linesz;
way_incr = dcache->way_incr;
way_size = dcache->way_size;

175
arch/sh/mm/copy_page.S
View File

@ -141,47 +141,38 @@ ENTRY(__copy_user_page)
.long 9999b, 6000f ; \
.previous
ENTRY(__copy_user)
tst r6,r6 ! Check explicitly for zero
bf 1f
rts
mov #0,r0 ! normal return
1:
mov.l r10,@-r15
mov.l r9,@-r15
mov.l r8,@-r15
! Check if small number of bytes
mov #11,r0
mov r4,r3
add r6,r3 ! last destination address
mov #12,r0 ! Check if small number of bytes
cmp/gt r0,r6
bt 2f
bra .L_cleanup_loop
nop
2:
neg r5,r0 ! Calculate bytes needed to align source
add #4,r0
and #3,r0
tst r0,r0
bt .L_jump
mov r0,r1
cmp/gt r0,r6 ! r6 (len) > r0 (11)
bf/s .L_cleanup_loop_no_pop
add r6,r3 ! last destination address
.L_loop1:
! Copy bytes to align source
EX( mov.b @r5+,r0 )
dt r1
EX( mov.b r0,@r4 )
! Calculate bytes needed to align to src
mov.l r11,@-r15
neg r5,r0
mov.l r10,@-r15
add #4,r0
mov.l r9,@-r15
and #3,r0
mov.l r8,@-r15
tst r0,r0
bt 2f
1:
! Copy bytes to long word align src
EX( mov.b @r5+,r1 )
dt r0
add #-1,r6
bf/s .L_loop1
EX( mov.b r1,@r4 )
bf/s 1b
add #1,r4
.L_jump:
mov r6,r2 ! Calculate number of longwords to copy
! Jump to appropriate routine depending on dest
2: mov #3,r1
mov r6, r2
and r4,r1
shlr2 r2
tst r2,r2
bt .L_cleanup
mov r4,r0 ! Jump to appropriate routine
and #3,r0
mov r0,r1
shll2 r1
mova .L_jump_tbl,r0
mov.l @(r0,r1),r1
@ -195,43 +186,97 @@ EX( mov.b r0,@r4 )
.long .L_dest10
.long .L_dest11
/*
* Come here if there are less than 12 bytes to copy
*
* Keep the branch target close, so the bf/s callee doesn't overflow
* and result in a more expensive branch being inserted. This is the
* fast-path for small copies, the jump via the jump table will hit the
* default slow-path cleanup. -PFM.
*/
.L_cleanup_loop_no_pop:
tst r6,r6 ! Check explicitly for zero
bt 1f
2:
EX( mov.b @r5+,r0 )
dt r6
EX( mov.b r0,@r4 )
bf/s 2b
add #1,r4
1: mov #0,r0 ! normal return
5000:
# Exception handler:
.section .fixup, "ax"
6000:
mov.l 8000f,r1
mov r3,r0
jmp @r1
sub r4,r0
.align 2
8000: .long 5000b
.previous
rts
nop
! Destination = 00
.L_dest00:
mov r2,r7
shlr2 r7
shlr r7
tst r7,r7
mov #7,r0
bt/s 1f
and r0,r2
.align 2
! Skip the large copy for small transfers
mov #(32+32-4), r0
cmp/gt r6, r0 ! r0 (60) > r6 (len)
bt 1f
! Align dest to a 32 byte boundary
neg r4,r0
add #0x20, r0
and #0x1f, r0
tst r0, r0
bt 2f
sub r0, r6
shlr2 r0
3:
EX( mov.l @r5+,r1 )
dt r0
EX( mov.l r1,@r4 )
bf/s 3b
add #4,r4
2:
EX( mov.l @r5+,r0 )
EX( mov.l @r5+,r1 )
EX( mov.l @r5+,r2 )
EX( mov.l @r5+,r7 )
EX( mov.l @r5+,r8 )
EX( mov.l @r5+,r9 )
EX( mov.l @r5+,r10 )
EX( mov.l r0,@r4 )
EX( mov.l r8,@(4,r4) )
EX( mov.l r9,@(8,r4) )
EX( mov.l r10,@(12,r4) )
EX( mov.l @r5+,r0 )
EX( mov.l @r5+,r8 )
EX( mov.l @r5+,r9 )
EX( mov.l @r5+,r10 )
dt r7
EX( mov.l r0,@(16,r4) )
EX( mov.l r8,@(20,r4) )
EX( mov.l r9,@(24,r4) )
EX( mov.l r10,@(28,r4) )
EX( mov.l @r5+,r11 )
EX( movca.l r0,@r4 )
add #-32, r6
EX( mov.l r1,@(4,r4) )
mov #32, r0
EX( mov.l r2,@(8,r4) )
cmp/gt r6, r0 ! r0 (32) > r6 (len)
EX( mov.l r7,@(12,r4) )
EX( mov.l r8,@(16,r4) )
EX( mov.l r9,@(20,r4) )
EX( mov.l r10,@(24,r4) )
EX( mov.l r11,@(28,r4) )
bf/s 2b
add #32,r4
tst r2,r2
1: mov r6, r0
shlr2 r0
tst r0, r0
bt .L_cleanup
1:
EX( mov.l @r5+,r0 )
dt r2
EX( mov.l r0,@r4 )
EX( mov.l @r5+,r1 )
dt r0
EX( mov.l r1,@r4 )
bf/s 1b
add #4,r4
@ -250,7 +295,7 @@ EX( mov.l r0,@r4 )
and r0,r2
2:
dt r7
#ifdef __LITTLE_ENDIAN__
#ifdef CONFIG_CPU_LITTLE_ENDIAN
EX( mov.l @r5+,r0 )
EX( mov.l @r5+,r1 )
EX( mov.l @r5+,r8 )
@ -320,7 +365,7 @@ EX( mov.w r0,@(2,r4) )
1: ! Read longword, write two words per iteration
EX( mov.l @r5+,r0 )
dt r2
#ifdef __LITTLE_ENDIAN__
#ifdef CONFIG_CPU_LITTLE_ENDIAN
EX( mov.w r0,@r4 )
shlr16 r0
EX( mov.w r0,@(2,r4) )
@ -342,7 +387,7 @@ EX( mov.w r0,@r4 )
! Read longword, write byte, word, byte per iteration
EX( mov.l @r5+,r0 )
dt r2
#ifdef __LITTLE_ENDIAN__
#ifdef CONFIG_CPU_LITTLE_ENDIAN
EX( mov.b r0,@r4 )
shlr8 r0
add #1,r4
@ -379,6 +424,7 @@ EX( mov.b r0,@r4 )
.L_exit:
mov #0,r0 ! normal return
5000:
# Exception handler:
@ -394,5 +440,6 @@ EX( mov.b r0,@r4 )
.previous
mov.l @r15+,r8
mov.l @r15+,r9
mov.l @r15+,r10
rts
mov.l @r15+,r10
mov.l @r15+,r11

64
arch/sh/mm/fault-nommu.c
View File

@ -1,64 +0,0 @@
/*
* arch/sh/mm/fault-nommu.c
*
* Copyright (C) 2002 - 2007 Paul Mundt
*
* Based on linux/arch/sh/mm/fault.c:
* Copyright (C) 1999 Niibe Yutaka
*
* Released under the terms of the GNU GPL v2.0.
*/
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/hardirq.h>
#include <linux/kprobes.h>
#include <asm/system.h>
#include <asm/ptrace.h>
#include <asm/kgdb.h>
/*
* This routine handles page faults. It determines the address,
* and the problem, and then passes it off to one of the appropriate
* routines.
*/
asmlinkage void __kprobes do_page_fault(struct pt_regs *regs,
unsigned long writeaccess,
unsigned long address)
{
trace_hardirqs_on();
local_irq_enable();
#if defined(CONFIG_SH_KGDB)
if (kgdb_nofault && kgdb_bus_err_hook)
kgdb_bus_err_hook();
#endif
/*
* Oops. The kernel tried to access some bad page. We'll have to
* terminate things with extreme prejudice.
*
*/
if (address < PAGE_SIZE) {
printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
} else {
printk(KERN_ALERT "Unable to handle kernel paging request");
}
printk(" at virtual address %08lx\n", address);
printk(KERN_ALERT "pc = %08lx\n", regs->pc);
die("Oops", regs, writeaccess);
do_exit(SIGKILL);
}
asmlinkage int __kprobes __do_page_fault(struct pt_regs *regs,
unsigned long writeaccess,
unsigned long address)
{
#if defined(CONFIG_SH_KGDB)
if (kgdb_nofault && kgdb_bus_err_hook)
kgdb_bus_err_hook();
#endif
return (address >= TASK_SIZE);
}

2
arch/sh/mm/pmb.c
View File

@ -145,7 +145,7 @@ repeat:
ctrl_outl(vpn | PMB_V, mk_pmb_addr(pos));
#ifdef CONFIG_SH_WRITETHROUGH
#ifdef CONFIG_CACHE_WRITETHROUGH
/*
* When we are in 32-bit address extended mode, CCR.CB becomes
* invalid, so care must be taken to manually adjust cacheable

55
arch/sh/mm/tlb-sh4.c
View File

@ -4,27 +4,14 @@
* SH-4 specific TLB operations
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2002 Paul Mundt
* Copyright (C) 2002 - 2007 Paul Mundt
*
* Released under the terms of the GNU GPL v2.0.
*/
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <linux/mman.h>
#include <linux/mm.h>
#include <linux/smp.h>
#include <linux/smp_lock.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/pgalloc.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>
@ -34,22 +21,27 @@ void update_mmu_cache(struct vm_area_struct * vma,
unsigned long flags;
unsigned long pteval;
unsigned long vpn;
struct page *page;
unsigned long pfn;
/* Ptrace may call this routine. */
if (vma && current->active_mm != vma->vm_mm)
return;
pfn = pte_pfn(pte);
if (pfn_valid(pfn)) {
page = pfn_to_page(pfn);
if (!test_bit(PG_mapped, &page->flags)) {
unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
__flush_wback_region((void *)P1SEGADDR(phys), PAGE_SIZE);
__set_bit(PG_mapped, &page->flags);
#ifndef CONFIG_CACHE_OFF
{
unsigned long pfn = pte_pfn(pte);
if (pfn_valid(pfn)) {
struct page *page = pfn_to_page(pfn);
if (!test_bit(PG_mapped, &page->flags)) {
unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
__flush_wback_region((void *)P1SEGADDR(phys),
PAGE_SIZE);
__set_bit(PG_mapped, &page->flags);
}
}
}
#endif
local_irq_save(flags);
@ -57,16 +49,26 @@ void update_mmu_cache(struct vm_area_struct * vma,
vpn = (address & MMU_VPN_MASK) | get_asid();
ctrl_outl(vpn, MMU_PTEH);
pteval = pte_val(pte);
pteval = pte.pte_low;
/* Set PTEA register */
#ifdef CONFIG_X2TLB
/*
* For the extended mode TLB this is trivial, only the ESZ and
* EPR bits need to be written out to PTEA, with the remainder of
* the protection bits (with the exception of the compat-mode SZ
* and PR bits, which are cleared) being written out in PTEL.
*/
ctrl_outl(pte.pte_high, MMU_PTEA);
#else
if (cpu_data->flags & CPU_HAS_PTEA)
/* TODO: make this look less hacky */
ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA);
#endif
/* Set PTEL register */
pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
#ifdef CONFIG_SH_WRITETHROUGH
#ifdef CONFIG_CACHE_WRITETHROUGH
pteval |= _PAGE_WT;
#endif
/* conveniently, we want all the software flags to be 0 anyway */
@ -93,4 +95,3 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
ctrl_outl(data, addr);
back_to_P1();
}

51
drivers/rtc/rtc-sh.c
View File

@ -1,7 +1,7 @@
/*
* SuperH On-Chip RTC Support
*
* Copyright (C) 2006 Paul Mundt
* Copyright (C) 2006, 2007 Paul Mundt
* Copyright (C) 2006 Jamie Lenehan
*
* Based on the old arch/sh/kernel/cpu/rtc.c by:
@ -23,16 +23,19 @@
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <asm/rtc.h>
#define DRV_NAME "sh-rtc"
#define DRV_VERSION "0.1.2"
#define DRV_VERSION "0.1.3"
#ifdef CONFIG_CPU_SH3
#define rtc_reg_size sizeof(u16)
#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */
#define RTC_DEF_CAPABILITIES 0UL
#elif defined(CONFIG_CPU_SH4)
#define rtc_reg_size sizeof(u32)
#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
#endif
#define RTC_REG(r) ((r) * rtc_reg_size)
@ -80,6 +83,7 @@ struct sh_rtc {
struct rtc_device *rtc_dev;
spinlock_t lock;
int rearm_aie;
unsigned long capabilities; /* See asm-sh/rtc.h for cap bits */
};
static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
@ -319,14 +323,14 @@ static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
tm->tm_mday = BCD2BIN(readb(rtc->regbase + RDAYCNT));
tm->tm_mon = BCD2BIN(readb(rtc->regbase + RMONCNT)) - 1;
#if defined(CONFIG_CPU_SH4)
yr = readw(rtc->regbase + RYRCNT);
yr100 = BCD2BIN(yr >> 8);
yr &= 0xff;
#else
yr = readb(rtc->regbase + RYRCNT);
yr100 = BCD2BIN((yr == 0x99) ? 0x19 : 0x20);
#endif
if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
yr = readw(rtc->regbase + RYRCNT);
yr100 = BCD2BIN(yr >> 8);
yr &= 0xff;
} else {
yr = readb(rtc->regbase + RYRCNT);
yr100 = BCD2BIN((yr == 0x99) ? 0x19 : 0x20);
}
tm->tm_year = (yr100 * 100 + BCD2BIN(yr)) - 1900;
@ -375,14 +379,14 @@ static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
writeb(BIN2BCD(tm->tm_mday), rtc->regbase + RDAYCNT);
writeb(BIN2BCD(tm->tm_mon + 1), rtc->regbase + RMONCNT);
#ifdef CONFIG_CPU_SH3
year = tm->tm_year % 100;
writeb(BIN2BCD(year), rtc->regbase + RYRCNT);
#else
year = (BIN2BCD((tm->tm_year + 1900) / 100) << 8) |
BIN2BCD(tm->tm_year % 100);
writew(year, rtc->regbase + RYRCNT);
#endif
if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
year = (BIN2BCD((tm->tm_year + 1900) / 100) << 8) |
BIN2BCD(tm->tm_year % 100);
writew(year, rtc->regbase + RYRCNT);
} else {
year = tm->tm_year % 100;
writeb(BIN2BCD(year), rtc->regbase + RYRCNT);
}
/* Start RTC */
tmp = readb(rtc->regbase + RCR2);
@ -589,6 +593,17 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
goto err_badmap;
}
rtc->capabilities = RTC_DEF_CAPABILITIES;
if (pdev->dev.platform_data) {
struct sh_rtc_platform_info *pinfo = pdev->dev.platform_data;
/*
* Some CPUs have special capabilities in addition to the
* default set. Add those in here.
*/
rtc->capabilities |= pinfo->capabilities;
}
platform_set_drvdata(pdev, rtc);
return 0;

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