drm/i915: remove confusing GPIO vs PCH_GPIO
Instead of defining all registers twice, define just a PCH_GPIO_BASE that has the same address as PCH_GPIO_A and use that to calculate all the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing the same thing. v2: Fix GMBUS registers to be relative to gpio base; create GPIO() macro to return a particular gpio address and move the enum out of i915_reg.h (suggested by Jani) v3: Move base offset inside the GPIO() macro so the GMBUS defines don't actually need to be changed (suggested by Daniel/Ville) v4: Move definition of i915_gpio to intel_display.h and remove GMBUS/GPIO handling from gvt since now they have their own defines. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180727193647.8639-3-lucas.demarchi@intel.com
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@ -1643,7 +1643,8 @@ struct drm_i915_private {
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struct mutex gmbus_mutex;
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/**
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* Base address of the gmbus and gpio block.
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* Base address of where the gmbus and gpio blocks are located (either
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* on PCH or on SoC for platforms without PCH).
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*/
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uint32_t gpio_mmio_base;
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@ -3082,18 +3082,9 @@ enum i915_power_well_id {
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/*
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* GPIO regs
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*/
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#define GPIOA _MMIO(0x5010)
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#define GPIOB _MMIO(0x5014)
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#define GPIOC _MMIO(0x5018)
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#define GPIOD _MMIO(0x501c)
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#define GPIOE _MMIO(0x5020)
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#define GPIOF _MMIO(0x5024)
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#define GPIOG _MMIO(0x5028)
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#define GPIOH _MMIO(0x502c)
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#define GPIOJ _MMIO(0x5034)
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#define GPIOK _MMIO(0x5038)
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#define GPIOL _MMIO(0x503C)
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#define GPIOM _MMIO(0x5040)
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#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
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4 * (gpio))
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# define GPIO_CLOCK_DIR_MASK (1 << 0)
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# define GPIO_CLOCK_DIR_IN (0 << 1)
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# define GPIO_CLOCK_DIR_OUT (1 << 1)
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@ -7489,6 +7480,8 @@ enum {
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/* PCH */
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#define PCH_DISPLAY_BASE 0xc0000u
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/* south display engine interrupt: IBX */
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#define SDE_AUDIO_POWER_D (1 << 27)
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#define SDE_AUDIO_POWER_C (1 << 26)
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@ -7783,13 +7776,6 @@ enum {
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#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
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#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
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#define PCH_GPIOA _MMIO(0xc5010)
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#define PCH_GPIOB _MMIO(0xc5014)
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#define PCH_GPIOC _MMIO(0xc5018)
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#define PCH_GPIOD _MMIO(0xc501c)
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#define PCH_GPIOE _MMIO(0xc5020)
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#define PCH_GPIOF _MMIO(0xc5024)
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#define _PCH_DPLL_A 0xc6014
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#define _PCH_DPLL_B 0xc6018
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#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
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@ -25,6 +25,22 @@
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#ifndef _INTEL_DISPLAY_H_
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#define _INTEL_DISPLAY_H_
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enum i915_gpio {
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GPIOA,
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GPIOB,
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GPIOC,
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GPIOD,
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GPIOE,
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GPIOF,
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GPIOG,
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GPIOH,
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__GPIOI_UNUSED,
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GPIOJ,
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GPIOK,
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GPIOL,
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GPIOM,
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};
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enum pipe {
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INVALID_PIPE = -1,
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@ -37,7 +37,7 @@
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struct gmbus_pin {
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const char *name;
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i915_reg_t reg;
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enum i915_gpio gpio;
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};
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/* Map gmbus pin pairs to names and registers. */
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@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
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else
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size = ARRAY_SIZE(gmbus_pins);
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return pin < size &&
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i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
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return pin < size && get_gmbus_pin(dev_priv, pin)->name;
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}
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/* Intel GPIO access functions */
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@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
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algo = &bus->bit_algo;
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bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
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i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
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bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
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bus->adapter.algo_data = algo;
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algo->setsda = set_data;
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algo->setscl = set_clock;
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@ -825,9 +823,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
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if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
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else if (!HAS_GMCH_DISPLAY(dev_priv))
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dev_priv->gpio_mmio_base =
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i915_mmio_reg_offset(PCH_GPIOA) -
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i915_mmio_reg_offset(GPIOA);
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/*
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* Broxton uses the same PCH offsets for South Display Engine,
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* even though it doesn't have a PCH.
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*/
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dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
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mutex_init(&dev_priv->gmbus_mutex);
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init_waitqueue_head(&dev_priv->gmbus_wait_queue);
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